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SDI
FOR MESSRS: DATE: OCT.16. 2006
CUSTOMER'S SPECIFICATIONS
160cm (63 Inch) Wide Plasma Display Module
(PAL/NTSC)
MODEL : S63HW-XD04
* Both Customer and Samsung SDI Co.,Ltd will approve this specification.
* Please return one of these specifications with your signature for approval.
Proposed by: Approved by:
Signature Signature .
Vice President Sung Do Kim
Quality Innovation Team
PDP Business Division,
CONFIDENTIAL
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SamsungSDI Corporation Specification Plasma Display Module
Revision History
Revision Date Description Of Changes Approval
Rev. 0.0 2006.06.15 Newly established
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TABLE OF CONTENTS
1. DESCRIPTION ................................................................................................5
2. FEATURES ....................................................................................................5
3. PRODUCT NAME AND MODEL NUMBER.......... ...............................................5
4. FUNCTION OUTLINE .....................................................................................5
5. BLOCK DIAGRAM .........................................................................................6
6. DISPLAY CHARACTERISTICS...............................................................7
6.1 Display Performance ..................................................................................7
6.2 Display Cell Arrangement ..........................................................................................8
6.3 Brightness Measurement Condition ................................................................................9
6.4 Contrast Measurement Condition .................................................................................10
6.5 Display Cell Defect Specification....................................................................................11
6.6 Uniformity Specification...................................................................................................12
6.7 APC(Automatic Power Control) Function.................................. ...............................13
6.8 Brightness and Power Mode Control..........................................................................13
6.9 Gamma Characteristic.........................................................................................15
7. SOUND PRESSURE LEVEL SPECIFICATION...................................................16
7 . 1 M e a s u r e me n t C o n d i t i o n ... ... ... ... ... ... ... ... ... ... ... ... ... . ... ... ... ... . ... ... . . ... ... ... ... . ... ... ... . . 1 6
7.2 Specification..............................................................................................16
8. MECHANICAL CHARACTERISTICS................................................................17
8.1 Mechanical Specification............................................................................................17
8.2 Mechanical Characteristics..........................................................................................17
9. ENVIRONMENTAL CONDITION ....................................................................18
9.1 Operational Environment Condition.....................................................................................18
9.2 Storage Environment Condition .............................................................................18
10. INTERFACE SIGNAL SPECIFICATION .....................................................20
10.1 Configuration Context ........................................................................................20
10.2 Interface function Specification .............................................................................21
10.3 Input Signal Definition ........................................................................................21
10.4 LVDS Signal Definition and Function ................................................................................22
10.5 LVDS Signal Pin Assignment ........................................................................................23
10.6 Video Signal Definition and Function .............................................................................25
10.7Electrical Condition of Interface Signals...............................................................................26
1.8 Video Signal Interface Timing Conditions .............................................................................27
0.9 LVDS Interface Timing Conditions.....................................................................................29
10.10 LVDS Connection Specifications ................................................................................30
10.11 Connector Specifications ...........................................................................................31
10.12 I2C Interface Conditions ............................................................................................32
11. ADDRESS MAP ................................................................................................. 36
11.1 Address map .............................................................................................................36
12. INPUT POWER VOLTAGE SPECIFICATION...........................................................37
12.1 Input Power Connector Location...............................................................................37
12.2 Electrical Characteristic Overview.................................................................................37
12.3 Power Applying Sequence.....................................................................................38
12.4 Pin Assignment of Connectors for Power Supply.............................................................42
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12.5 Pin Assignment of Connectors for Power Supply......................................................................43
12.6 Electrical Characteristic Overview for Image Board ................................................................43
12.7 Power Supply's pin assignment of connectors for AC Input.........................................................44
13. MECHANICAL DIMENSION DRAWING...............................................................45
13.1 Front Side ..................................................................... ..........................45
1 3 . 2 R e a r S i d e ... ......... ... ... . ... ... ... ... .....................................................................45
13.3 Measurement for distance between chassis-base hole and effective dimension....................46
14. LABEL....................................................................................................46
14.1 Label Type ................................................................................................ .46
1 4 . 2 Lab el Lo cation .......................................................................................... .47
14.3 Serial No. ............................................................................................48
15 . PACKING................................................................................................49
1 5 . 1 Pack in g D ime n s io n an d Par ts List .................................................................49
15.2. Packing Assembly Drawing ......................................................................49
16. RELIABILITY ............................................................................................ 50
16.1 MTBF Value...............................................................................................................50
16.2 Expected Service Life .............................................................................................50
16.3 Disclaimer .........................................................................................................50
16.4 Certificate .........................................................................................................51
17. WARNINGS/ CAUTIONS / NOTICE..................................................................52
17. 1 Warning
....................................................................................................................52
17.2 Caution...............................................................................................53
17.3 Notice.............................................................................................. 54
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SamsungSDI Corporation Specification Plasma Display Module
1. Description
The S63HW-XD04 is a 63-inch wide full color plasma display Module with a resolution of
1366(H) 768(V) pixels. The display module includes the Plasma Display Panel(PDP),
the Panel driving electronics, the Logic Control Board.
(PSU & image board supply).
2. FEATURES
x Wide aspect ratio(16:9) 63 inch diagonal display screen. The display area is 1,393
wide and 783 high..
x Slim and light weight. The display Module is 70.1 (TBD) in depth and weight only
approx.44 exclusive of power supply.
x 68719.47 million colors(12Bit), 1073.7 million colors(10Bit), 16.77 million colors(8Bit)
combination of R,G and Bdigital data.(according to LVDS input selection)
x High Luminance, High contrast, Wide viewing angle. The screen has a white peak
Luminance of typical 1,000 cd/ (TBD), contrast of typical 8,500:1(NTSC, TBD)
typical 5,000:1(PAL, TBD) and a viewing angle (of) greater than 160 comparable to
those of CRTs.
3. PRODUCT NAME AND MODEL NUMBER
x Product name : 63 inch Full Color Plasma Display Module1
(abbreviation : PDP Module1)
x Model number : S63HW-XD04
4. FUNCTION OUTLINE
x The plasma display Module has an APC(Automatic Power Control) function which
restricts power consumption within the certain value with regard to each display load
ratio.
x The plasma display Module is operated by following digital video signals; Vertical
synchronous signal, Horizontal synchronous signal, Enable signal and 8, 10, 12 bits data
signal of each R,G, and B color. All signals are based on LVDS level.
x The plasma display Module is operated at 50Hz or 60Hz frame rate. An external frame
rate conversion is required in order to display the other formats.
x The plasma display Module requires several types of input power voltages; voltage for
LOGIC, voltage for COF driving, voltage for gate driver, voltage for sustain, address, set,
scan and x-bias.
x The plasma display Module is operated at progressive signal only.
An external progressive scan conversion is required in order to display the other formats.
x The plasma display Module requires rated 100~240V, 50~60Hz of input power voltage.
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5. BLOCK DIAGRAM
Column Driver
D-RAM Driver
R0 to R11
Timing
G0 to G11 Row
Driver
B0 to B11 LVDS Data Display 1366 768 Pixels X-Pulse
DCLK I/F contro- Data
Y-Pulse 1366 3 768 Cells Generat
Vsync ller Driver
Generator -or
Timing Scan
Hsync
contro- Timing
ENABLE
ller
Column Driver
Vcc Vdd Va Vs Ve Vset Vscan
AC Power
Source
Power Supply
(110/220V) (Optional)
Figure-1. Block Diagram of PDP module
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6. DISPLAY CHARACTERISTICS
6.1 Display Performance
No Item Rating
1 Display Pixels Horizontal 1366 Vertical 768 pixels
(1 pixel = 1 R,G,B cells)
2 Display Cells Horizontal 4,098 Vertical 768 cells
3 Pixel Pitch Horizontal 1.02 Vertical 1.02
R Horizontal 0.34 Vertical 1.02
4 Cell Size G Horizontal 0.34 Vertical 1.02
B Horizontal 0.34 Vertical 1.02
5 Pixel Type R, G, B Stripe (refer to Figure-2)
6 Effective Display Horizontal 1393.3 Vertical 783.4
Size [ 54.86 inch (H) 30.84 inch (V) ]
68719.4 million colors (12Bit), 1073.7 million colors (10Bit)
7 Number of color
16.77 million colors (8Bits)
8 Peak Luminance *1 NT/PAL: min 800 cd/ , typical 1,000cd/
NTSC : Min 5,000:1
Typical 8,500:1
Contrast Ratio *2 PAL : Min 3,000:1 Calculated value Refer to
9 note *2
(in dark room) Typical 5,000:1
at 60Hz Vsync
at 70Hz Vsync
10 Full white Luminance NTSC/PAL: Min 140 cd/ , Typical 170cd/
Color Coordinates White : X=0.290 0.02, Y=0.300 0.02
11
(Typical value) Peak : X=0.290 0.02, Y=0.290 0.02
12 Viewing Angle *3 Over 160
(Note)
* 1. Luminance and Color Coordinates are the values that were measured with 1% load ratio
white pattern. The condition for measurement is shown in Figure-3.
* 2. Contrast Ratio is calculated from the display Luminance and the non-display
Luminance value. Display condition is shown in Figure-4.
* 3. Viewing angle is a critical angle at which the Luminance is reduced to 50% to the
Luminance perpendicular to the PDP Module. The contact luminance meter CA-
100+H is used to measure the Luminance.
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6.2 Display Cell Arrangement
1st 2nd 3rd 1364th 1365th 1366th
Pixel Pixel Pixel Pixel Pixel Pixel
Column Column Column Column Column Column
Pixel Pitch (Width):1.02 mm
1st
Pixel Pixel B G R B G R B G R B G R B G R B G R
Row Pitch
Pitch Height
2nd (1.02 mm)
Pixel B G R B G R B G R B G R B G R B G R
Row
0.340
0.340
0.340 Cell
767th
Pixel B G R B G R B G R B G R B G R B G R
Row
768th
Pixel B G R B G R B G R B G R B G R B G R
Row
Figure-2. Display Cell Arrangement
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6.3 Brightness Measurement Condition
(1) Display Pattern
Effective Display Area
346
Effective Display Area
76
346
615 136 615
Unit : Pixels(=lines)
marked area : White display area by maximum gradation setting
marked area : Black color (non-display area)
Figure-3. Display Pattern for Brightness & Contrast Ratio Measurement
(2) Display Area ratio : 1% white window
(3) Vsync : 16.7ms or 20ms
(4) Measuring equipment : MINOLTA CA-100+H
Pattern Generator(VG-828, LVDS Output)
(5) Ambient Temperature : Room Temperature
(6) Ambient Luminance : Dark Room (<2 lux)
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[ Note]
1. Measurement is done within 5 seconds after Power On. The temperature of panel
before measurement is room temperature (25 ).
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6.4 Contrast Measurement Condition
(1) Measuring point
(2) Vsync : 16.7 ms or 20ms
(3) Measuring Equipment : MINOLTA CA-100+H
Pattern Generator(VG-828, LVDS Output).
(4) Contrast Calculation formula
Brightness of 1% white window Area at the center of the screen
Contrast ratio =
Brightness of Black Area *1
Note
1. For mass production test purposes, it is recommended to measure just 1 point,
P1 of Figure.-4 on display pattern of Fig.-3.
(5) Ambient Light : Dark Room (<2 lux)
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6.5 Display Cell Defect Specification
In some cases, a panel may have defective cells that cannot be controlled.
These defective cells can be categorized into three types;
(1) Non-lighting cell defect : defect in which the cell is always off
(2) Non-extinguishing cell defect : defect in which the cell is always on.
(3) Flickering cell defect : defect in which the cell is flickering.
(4) High intensity cell defect : defect in which the cell is brighter than other cells
The display cell defect specifications define the allowed limits for display cell defects and
are used as the criteria in determining whether a panel should be shipped.
W
Zone B H /4
H
Zone A H /2
H /4
W /4 W /2 W /4
6.6 Uniformity Specifications
Specification
Item
Number of cell defects Distance between cell defects
Non-lighting Zone A: 4 and less
cell defect Zone B: 10 and less
Non- Regardless of A and B zone,
Zone A: 0
extinguishing
Zone B: 1 and less
cell defect
1 Cell Defect in an area of 50mm*50mm
Flickering Zone A: 0
cell defect Zone B: 1 and less
The color-PDP uses ultraviolet light produced by gas discharge to illuminate phosphor.
Uneven phosphor coating and inconsistent discharge characteristics may cause slight
difference in brightness and chromaticity coordinates in a panel.
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The Brightness Uniformity and White Uniformity are measured at Full White of
4095(12Bit) gray level. Its measuring points are defined in Figure-6.
W : Effective Display Area
A1 A2 A3 H * 0.1
H : Effective Display Area
A4 A5 A6
A7 A8 A9
H * 0.1
W * 0.1 W * 0.1
Figure-6. Measuring areas
1) Brightness Uniformity at Full White
Item Definition Specification
The brightness is measured at 9 points (A1~A9 of
Brightness Fig-6) on full white pattern. 10% and less
Uniformity The brightness uniformity is calculated from the
following equations.
Equation Max x Max x
u 100% & u 100%
x x
6.7 APC (Automatic Power Control) Function
The PDP has an APC (Automatic Power Control) function for the total power consumption
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control. When the total display load ratio exceeds approximately 10%, total power
consumption is limited within a specified level(=Lower Power Limit) by APC function.
The operational behavior of APC function is called as SLOW-APC. If the display load-ratio
changes from low to high value, the power-consumption rises instantly to "Upper Power
Limit" and gradually decreases until it reaches to the "Lower Power Limit".
Upper Power
Limit
Power
Load-ratio
Lower Power
Limit
time t
Figure-7 SLOW -APC Behavior
6.8 Brightness and Power Mode Control
This PDP module offers the methods for Brightness and Power mode control..
ASLG(ASL Gain), PUG and PLG are for power mode control. All these ASLG, PUG and
PLG are registers controllable using I2C communication from image B'd side. For a detailed
address and data bits of these registers,
refer to the Chapter 11. Address Map.
1) ASLG ( Power-Mode Control using ASL gain function)
- ASLG variable range : 00~FFh
- Maximum available power increase by decreasing ASLG below 80h
- Maximum available power decrease by increasing ASLG above 80h
Sustain
number ASLG < ASLG'
Max. Sustain ASLG' = 80h
ASLG > ASLG' High-Power Mode
Normal Mode
load at F/W pattern Power-Save Mode
Min. Sustain
Saturated at Min. Sustain
0 Load-ratio 100%
Figure-8. ASLG Behavior
2) Power-Mode Control( Multi APC)
PUG, PLG variable range : 00 ~ FFh(Tentative)
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Maximum available power is Max.(590W), even if PUG value go over that
Max.(590W), the power will not go over the Max.(590W).
Minimum available power is Min.(500W), even if PLG value go down that
Min.(500W), the power will not go down the Min.(500W).
The gap of Upper and Lower can be controlled by set maker.
Max.590W + 10%
Upper.560W
Lower.540W
Min. 500W
Figure-9 APCL Behavior
3) Power Consumption Specification
Typ.560W
Typ.540W
Slow APC Control System
Figure-10. Display load ratio vs. Power consumption
Mode Maximum Typical Minimum Level Remarks
Level Level
Standard 590W +10% 500W Typical level can be controled by
PUG=80h 560W customer.
PLG=80h 540W Maximum level and Minimum level
are not fixed.
[Note]
1. This is the case that the PDP Module includes SDI's Main PSU.
2. The Efficiency of SDI's Main PSU is about 81% under conditions of AC 100V, 60Hz.
It is measured on full screen white pattern with input gray-level 4095(12Bit) in
module. Power consumption is same for PAL and NTSC mode.
6.9 Gamma characteristics
This PDP module offsers Customer's Gamma selection and Gamma control.
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Registers are controllable through I2C communication from image B'd. For a detailed
address and data bits of these registers , refer to the Chapter 11. Address Map.
1) Basis of Gamma Curve
This PDP module is normally applied to the 2.2 gamma curve (refer to Figure-11)
But this specification could be modified on the request of the customer
Figure-11. Gamma Curve
7. SOUND PRESSURE LEVEL SPECIFICATION
7.1 Measurement Condition
(1) Background Noise Level : less than 20dBA
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(2) Measuring Pattern : Dynamic Images (Note3)
(3) Measuring Equipment : Sound level meter Type 2827 made by B&K
(4) Measuring Distance : 1m from the rear side of PDP Module included
standard SDI's PSU.
(5) Measuring point
0.5m
7.2 Sound Pressure Level :
(1) Overall level
- Sound Pressure Level caculated from the individual band levels of 50Hz ~ 8kHz.
- Specification : Max. 31dB(50Hz~8kHz), Max. 23dB(2~3.15kHz)
8. MECHANICAL CHARACTERISTICS
8.1 Mechanical Specifications
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No Item Rating
Outer
1 Width 1484 Height 874 Thickness 70.1
Dimensions
2 Weight Approx. 44.0 kg
* Appendix A1 is included in section 12.1
* Appendix A2 is included in section 12.2.
8.2 Mechanical Characteristics
No Item R ating
Frequency : 10 ~ 55 H z
Sw eep rate : 1 O ctave/m in.
1 V ibration
Stroke : x,y direc tion : 0.35mm
z-direction : 0.175mm
A ccelera tion : less than 20G (X ,Y -direction)
2 Shock less than 10G (Z -dire ction)
D uration tim e : 11ms
* Notes: ( Test condition ) Non-Packaging, Operational
* Test time of Vibration Test is 30 minutes every direction(x,y,z)
* The number of times for shock test is 6 times every direction(x,y,z).
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9. ENVIRONMENTAL CONDITIONS
9.1 Absolute Maximum Ratings
No. Item Rating
Operational -5 to 50
1 Temperature
Storage -20 to 70
Operational 5 to 85 % RH (no condensation)
2 Humidity
Storage 5 to 85 % RH (no condensation)
Operational 830 to 1114 hPa (0~1,700m)
3 Pressure
Storage 300 to 1114 hPa (0~10,000m)
9.2 Recommended Environmental Condition
No. Item Rating
Operational 0 to 35
1 Temperature
Storage -5 to 45
Operational 20 to 70 % RH (no condensation)
2 Humidity
Storage 20 to 80 % RH (no condensation)
Operational
3 Pressure 850 to 1114 hPa (0~1,500m)
Storage
9.3 Panel Surface Condition
9.3.1. Panel surface temperature specification
The panel surface temperature should be kept as below in order to get stable display of
image.
- Tp= below 120 (Absolute Maximum Rating); when small size of image is displayed
- Tp= below 85 ; when Full White is displayed.
If the temperature exceeds above level, it may cause the defects of display image like
dot missing, line missing and/or poor image.
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As the surface temperature of panel has tendency to rise with deduction of display rate,
the relation with temperature can be describe as below:
85 (display load rate is high : Large Area )
~ 120 (display load rate is low : Small Area)
Surface
Temperatur
120
85
15~20% 100%
Displayed
Figure-13. Surface Temperature Vs Displayed Area
It is strongly recommended that the panel surface temperature should be kept as low as
possible, eventhought its maximium rating is descreibed as above.
9.3.2. Panel Surface Temperature for Breaking
The temperature uniformity across panel should be maintained below 20 / not to
occure panel breaking by temperature difference.
This breaking temperature is not absolute temperature, because it depends on condition
of panel production and panel scratch. Please take this value as a reference.
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10. Interface Signal Specifications
10.1 Configuration Context
10.1.1 Configuration Context (8Bit, 10Bit and 12Bit)
LVDS
decoder
SCALER LVDS (8bit) Drive IC
IC encoder
(8bit) LVDS
decoder
(4bit)
LVDS
decoder
SCALER LVDS (8bit) Drive IC
IC encoder
(10bit) LVDS
decoder
(4bit)
LVDS
decoder
SCALER LVDS (8bit) Drive IC
IC encoder
(12bit) LVDS
decoder
(4bit)
10.2 Interface Function Specifications (input data and display processing)
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- 1366*768dots data signals are input to this product to display data.
- The Video signal and control signal input section uses a low voltage differential signaling
(LVDS) interface.
- An I2C bus serial data interface is used for communication between MPU as FTV side and
the CLU (Control LOGIC Unit) of this PDP module.
- I2C_READY signal is used that the CLU(Control LOGIC Unit) of PDP module inform
image scale b'd that CLU is ready for I2C communication.(1 : ready, 0 : not ready)
10.3 Input Signal Definition
No Item Signal name Q Method Definition
1 Display Video RxIN0- 1 LVDS Differential serial data signal.
Signal Signal RxIN0+ 1 Differentials Input video and timing signals after
RxIN1- 1 differential serial conversation using a
RxIN1+ 1 dedicated transceiver. The serial data
RxIN2- 1 signal is transmitted seven times faster than
RxIN2+ 1 the base signal.
RxIN3- 1
RxIN3+ 1
RxIN0b- 1
RxIN0b+ 1
RxIN1b- 1
RxIN1b+ 1
Dot Clock RxCLKIN- 1 LVDS Differential clock signal.
RxCLKIN+ 1 Differential Input the clock signal after differential
RxCLKINb- 1 conversation using a dedicated transceiver.
RxCLKINb+ 1 The clock signal is transmitted at the same
speed as the base signal.
2 MPU Communi SDA 1 LVTTL I2C bus serial data communication signal.
Commu cation SCL 1 (I2C) Communication with the CLU (Control
nication I2C_READY 1 Logic Unit) of this product is enabled.
Figure-13(b). Interface Signal(12Bit)
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10.4 LVDS Signal Definition and Function
A video signal (display data signal and control signal) is converted from parallel data to
serial data with the LVDS transmitter and further converted into four sets of differential
signals before input to this PDP module. These signals are transmitted seven times faster
than dot clock signals. The dot clock signal is converted into one set of differential
signals.
The LVDS signal definition and function as follows in Italic:
Interface Signal Function
Symbol I/O Function Remarks
RxIN0- I Display Data Signal: LVDS signal
RxIN0+ I R0, R1, R2, R3, R4, R5, G0 LVDS signal
RxIN1- I Display Data Signal: LVDS signal
RxIN1+ I G1, G2, G3, G4, G5, B0, B1 LVDS signal
RxIN2- I Display Data Signal: LVDS signal
RxIN2+ I B2, B3, B4, B5, Hsync, Vsync, Enable LVDS signal
RxIN3- I Display Data Signal and Control Signal: LVDS signal
RxIN3+ I R6, R7, G6, G7, B6, B7 LVDS signal
RxCLKin- I Dot Clock Signal: LVDS signal
RxCLKin+ I CLK LVDS signal
SDA I/O I2C serial data 3.3V CMOS
SCL I Clock signal for SDA 3.3V CMOS
I2C_READY O I2C enable signal 3.3V CMOS
[8Bit LVDS Interface]
Interface Signal Function
Symbol I/O Function Remarks
RxIN0- I Display Data Signal: LVDS signal
RxIN0+ I R2, R3, R4, R5, R6, R7,G2 LVDS signal
RxIN1- I Display Data Signal: LVDS signal
RxIN1+ I G3, G4, G5, G6, G7, B2, B3 LVDS signal
RxIN2- I Display Data Signal: LVDS signal
RxIN2+ I B4, B5, B6, B7, Hsync, Vsync, Enable LVDS signal
RxIN3- I Display Data Signal and Control Signal: LVDS signal
RxIN3+ I R8, R9, G8, G9, B8, B9 LVDS signal
RxIN4- I Display Data Signal and Control Signal: LVDS signal
RxIN4+ I R0, R1, G0, G1, B0, B1 LVDS signal
RxCLKin- I Dot Clock Signal: LVDS signal
RxCLKin+ I CLK LVDS signal
SDA I/O I2C serial data 3.3V CMOS
SCL I Clock signal for SDA 3.3V CMOS
I2C_READY O I2C enable signal 3.3V CMOS
[10Bit LVDS Interface]
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Interface Signal Function
Symbol I/O Function Remarks
RxIN0- I Display Data Signal: LVDS signal
RxIN0+ I R4, R5, R6, R7, R8, R9, G4 LVDS signal
RxIN1- I Display Data Signal: LVDS signal
RxIN1+ I G5, G6, G7, G8, G9, B4, B5 LVDS signal
RxIN2- I Display Data Signal: LVDS signal
RxIN2+ I B6, B7, B8, B9, HYNC, VSYNC, DEN LVDS signal
RxIN3- I Display Data Signal and Control Signal: LVDS signal
RxIN3+ I R10, R11, G10, G11, B10, B11 LVDS signal
RxCLKIN- I Dot Clock Signal: LVDS signal
RxCLKIN+ I CLK LVDS signal
RxIN0b- I Display Data Signal: LVDS signal
RxIN0b+ I R2, R3, G2, G3, B3, B3 LVDS signal
RxIN1b- I Display Data Signal: LVDS signal
RxIN1b+ I R0, R1, G0, G1, B0, B1 LVDS signal
RxCLKINb- I Dot Clock Signal: LVDS signal
RxCLKINb+ I CLKb LVDS signal
SDA I/O I2C serial data(Bi-direction) 3.3V CMOS
SCL I Clock signal for SDA 3.3V CMOS
I2C_READY O I2C enable signal 3.3V CMOS
[12Bit LVDS Interface]
10.5 LVDS Signal Pin Assignment
The table below indicates pin assignment of the LVDS IC(Receiver).
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10.6 Video Signal Definition and Function
The table below indicates the definition and functions of input video signals before
LVDS conversion.
Interfaces Signal Functions
Symbol Function Remarks
Display data signal:
R11 to R0 12 bits red video signal (note 1)
R11: MSB*, R0: LSB**
Display data signal:
G11 to G0 12 bits green video signal (note 1)
G11: MSB*, G0: LSB**
Display data signal:
B11 to B0 12 bits blue video signal (note 1)
B11: MSB*, B0: LSB**
This signal specifies the data period
for one horizontal line. Control of
Hsync Horizontal synchronous signal
the next line begins at the rising
edge of Hsync.
Timing signal that controls the start
of the screen. Control of the next
Vsync Vertical synchronous signal
screen begins at the rising edge of
Vsync.
Data
Data enable signal This signal encloses valid data.
Enable
Latch the video signal at falling
DCLK Clock for video signal
edge.
[Note]
* MSB: Most Significant Bit (Highest Intensity Bit)
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** LSB: Least Significant Bit (Lowest Intensity Bit)
10.7 Electrical Condition of Interface Signals
1) Maximum Ratings
Common conditions : Ta = 25 , Vcc = 3.3V
Absolute Ratings
Item Parameter Symbol Ratings Unit
RxIN0-/+,RxIN1-/+,RxIN2-/+, Input Voltage Vi - V
RxIN3-/+,RxCLKIN-/+, 0.3~3.6
LVDS
Input RxINb0-/+,RxINb1-/+,
Signals RxCLKINb-/+
3.3V
SDA, SCL Input Voltage Vi 0.3~3.6 V
CMOS
Output 3.3V
I2C_READY Output Voltage Vo 0.3~3.6 V
Signal CMOS
2) Electrical Characteristics
Common conditions : Ta =25 , Vcc = 3.3V
Electrical Characteristics
Signal Item Symbol Conditions Min. Typ. Max. Unit
Differential input
Vth VCM=1.2V - - 100
High Threshold
LVDS Differential input
Vtl VCM=1.2V -100 - -
Low Threshold
Input current Iin VIN=+3.6/GND - - 10.0
Input Voltage Vih 0.5 Vcc - 4.1 V
Vil -0.5 - 0.3 Vcc V
Input Capacitance Vin - - - 8
I2C
Voh Ioh = 8 2.4 - - V
Output Voltage
Vol - - - 0.4 V
Output Current Iol - - - 10
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10.8 Video Signal Interface Timing Conditions
The table below indicates the conditions of input video signal before LVDS conversion.
These conditions must be satisfied. Refer to figure 16 of timing chart.
Thp
Thbp
Twh
TWV
Tvbp
SAMSUNG PDP HD (42")
Active Display Area
1366*768(Wide XGA) Tvp
Figure-14. Video Input Signal Timing Chart
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[V Sync Behavior]
- PAL long mode : below 48Hz
- PAL Normal Mode : 48 ~ 52Hz
- PAL LB Mode : 52 ~ 55 Hz
- NTSC long Mode : 55 ~ 58 Hz
- NTSC Normal Mode : 58 ~ 62 Hz
- NTSC LB Mode : 62 ~ 65 Hz
- NTSC Mask Mode : above 65 Hz
* LB Mode(=Low Brightness Mode) : By decreasing sustain period on the Tvsync shorter than normal,
brightness is reduced.
* Mask(or Flicker) Mode : Masks abnormally short Vsync, and displays at the frame period twice as
input Vsync period.
* long mode : mode change is not occurred in this peried, the display is normally operation by increasing
the Vsync period.
60Hz
ITEM Symbol Min. Typ. Max. Unit Note
Period Tclk 14.49 - 12.82 ns
DCLK
Frequency 69 74 78 MHz
Period Thp 19.6 - - us @ 78
Hsync Frequency Fh - - - KHz
Width Twh 6 - - Tclk
Period Tvp 810 - - Thp
Vsync Frequency Fv - - - Hz
Width Twv 2 - - Thp
Horiz