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X10
7-1 MAIN BOARD
AQUILA 7-1-1 Schematic Diagrams
CPU :P4-BANIAS
Chip Set :MCH-M ODEM
Remarks :TEMP
Model Name : AQUILA MAIN
PBA Name : BA92-01774A
PCB Code : BA41-#####A
Dev. Step : SR
Revision : 1.0
7 Schematic Diagrams and PCB Silkscreen
DRAW CHECK APPROVAL
7-1
7-2
CPU
479 MICRO FCBGA
PSB 400MHZ SYSTEM MEMORY
2 EA SODIMM
TFT_LCD 14.1" 200 / 266 MHZ MAX 512MBYTE EACH
EXTERNAL MCH-M
AGP 4X , 1.5V DOUBLE DATA RATE
CRT GRAPHIC
ODEM 1.2 V
nvidia MAP31 593 FCBGA USB 0 , 1
2 USB
PORT REPLICATOR
USB 2 USB 4,5
HUB I / F BLUETOOTH
7 Schematic Diagrams and PCB Silkscreen
1.8V 8BIT 66MHZ DC - IN
USB 3
RJ -11 MDC FINGER PRINT
SUPER I/O
INNER SPEAKER AUDIO CODEC PC87393
ICH4 - M
HEAD PHONE CIRRUS LOGIC S AC97 LINK 82801 DBM 1.5V
IDE 0 SERIAL I/O
cs4202 421 FCBGA
EXTERNAL MIC IDE 1 LOW PIN COUNT
PARALLEL I/O
AC97 LINK PCI BUS
FWH PS /2
IDE 0
HDD CARDBUS
TV (S-VHS)
CONTROLLER MINI PCI
RICOH R5C590 MICOM
SLIM HITACHI S SPDIF
DVD-CD/RW IDE 1
HD64F2169
COMBO
RJ -45
CARDBUS WLAN
7-1-1(a) Main Board Schematic Sheet 2 of 39(Operation Block Diagram)
WLAN &
LOM BLUETOOTH KEYBOARD
1394
COMBO
3 COM S
PCI BUS TOUCHPAD
3C920 - ST05 MEMORY STICK
port replicator
X10
X10
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
PCI Devices Voltage Rails
Devices IDSEL# REQ/GNT# Interrupts
Cardbus AD19 0 A,B,C VDC Primary DC system power supply (7 to 21V)
LAN AD21 3 D VCC_CORE Core voltage for BANIAS CPU (1.356 - 0.844V)
MiniPCI SLOT1 AD23 2 E,F VCCP BANIAS/ODEM Processor System Bus(PSB) Termination (1.05V)
USB AD29(internal) - USB2.0 #0 : A VCC_MCH MCH-M Core Voltage (1.2V)
USB2.0 #1 : D
USB2.0 #2 : C P1.5V 1.5V switched power rail (off in S3-S5)
Hub to PCI AD30(internal) - - P1.5V_AUX 1.5V power rail (off in S4-S5)
LPC bridge/IDE/AC97/SMBUS AD31(internal) - B P1.8V 1.8V switched power rail (off in S3-S5)
AGP AD17(internal) - A,B P1.8V_AUX 1.8V power rail(off in S4-S5)
Internal MAC AD24(internal) - E P2.5V 2.5V switched power rail (off in S3-S5)
AC Link - -B P2.5V_AUX 2.5V power rail (off in S4-S5)
P1.25V_AUX 1.25V power rail (off in S4-S5)
MICOM_P3V 3.3V always on power rail for MICOM
P3.3V 3.3V switched power rail (off in S3-S5)
Docking AD30(internal) - - P3.3V_AUX 3.3V power rail (off in S4-S5)
PCI SLOT AD20 - A,B,C,D
P3.3V_ALWAYS 3.3V always on Power Rail
P5V 5.0V switched power rail (off in S3-S5)
P5V_ALWAYS 5.0V always on power
P12V 12.0V switched power rail (off in S3-S5)
CPU Core Voltage Table
2
VID5 VID4 VID3 VID2 VID1 VID0 Voltage VID5 VID4 VID3 VID2 VID1 VID0 Voltage
Northwood-B
I C / SMB Address
0 0 0 0 0 0 0 1.708 V 1 0 0 0 0 1.196 V
0 0 0 0 0 1 1.692 V 1 0 0 0 0 1 1.180 V (Interposer B d) Devices Address Hex Bus
0 0 0 0 1 0 1.676 V 1 0 0 0 1 0 1.164 V
0 0 0 0 1 1 1.660 V 1 0 0 0 1 1 1.148 V ICH4 Master - SMBUS Master
0 0 0 1 0 0 1.644 V 1 0 0 1 0 0 1.132 V ADM1032(CPU Thermal Sensor) 1001 110X 9Ch Thermal Sensor
0 0 0 1 0 1 1.628 V 1 0 0 1 0 1 1.116 V SODIMM0 1010 0000 A0h -
0 0 0 1 1 0 1.612 V 1 0 0 1 1 0 1.100 V SODIMM1 1010 001X A2h -
0
- -
0 0 1 1 1 1.596 V 1 0
- 0 1 1 1 1.084 V CK-408 (Clock Generator) 1101 001x D2h Clock, Unused Clock Output Disable
0 0 1 0 0 0 1.580 V 1 0 1 0 0 0 1.068 V
0 0 1 0 0 1 1.564 V 1 1 0 0 0 1 1.052 V
0 0 1 0 1 0 1.548 V 1 0 1 0 1 0 1.036 V
0 0 1 0 1 1 1.532 V 1 0 1 0 1 1 1.020 V
0 0 1 1 0 0 1.516 V 1 0 1 1 0 0 1.004 V
0 0 1 1 0 1 1.500 V 1 0 1 1 0 1 0.988 V
0 0 1 1 1 0 1.484 V 1 0 1 1 1 0 0.972 V USB PORT Assign
0 0 1 1 1 1 1.468 V 1 0 1 1 1 1 0.956 V
0 1 0 0 0 0 1.452 V 1 1 0 0 0 0 0.940 V PORT NUMBER ASSIGNED TO
0 1 0 0 0 1 1.436 V 1 1 0 0 0 1 0.924 V
0 1 0 0 1 0 1.420 V 1 1 0 0 1 0 0.908 V 0 SYSTEM PORT A
0 1 0 0 1 1 1.404 V 1 1 0 0 1 1 0.892 V 1 SYSTEM PORT B
0 1 0 1 0 0 1.388 V 1 1 0 1 0 0 0.876 V 2 BLUETOOTH
0 1 0 1 0 1 01.372 V 1 1 0 1 1 0.860 V 3 FINGER PRINT
Highest Freq. 0 1 0 1 1 1 0 1.356 V 1 0 1 1 0 0.844 V Lowest Freq. 4 PORT REPLICATOR
0
- 1 0 1 1 1 11.340 V 1 1 0 1 1 1 0.828 V 5 PORT REPLICATOR
0 1 1 0 0 0 1.324 V 1 1 1 0 0 0 0.812 V
0 1 1 0 0 1 1.308 V 1 1 1 0 0 1 0.796 V
0 1 1 0 1 0 1.292 V 1 1 1 0 1 0 0.780 V
0 1 1 0 1 1 1.276 V 1 1 1 0 1 1 0.764 V System Power States
0 1 1 1 0 0 1.260 V 1 1 1 1 0 0 0.748 V Deeper Sleep
0 1 1 1 0 1 1.244 V 1 1 1 1 0 1 0.732 V CHP3_SLPS1* S1, Powered-On-Suspend(POS) : In this state, all clocks(except the 32.768KHz clock) are stopped.
0 1 1 1 1 0 11.228 V 1 1 1 1 0 0.716 V The system context is maintained in system DRAM. Power is maintained to PCI, the CPU, memory controller, memory, and all other criticial subsystems.
7-1-1(b) Main Board Schematic Sheet 3 of 39(Board Information)
0 1 1 1 1 1 1.212 V 1 1 1 1 1 1 0.700 V Note that this state does not preclude power being removed from non-essential devices, such as disk drives. During this state, CPU can be selected
for either Deep Sleep or Deeper Sleep.
In Deeper Sleep, CPU voltage reduced in this state to reduce the leakage power.
CHP3_SLPS3* S3, Suspend-To-RAM(STR) : The system context is maintained in system DRAM, but power is shut off to non-critical circuits.
Memory is retained, and refreshes continue. All clocks stop except RTC clock.
CHP3_SLP4S* S4, Suspend-To-Disk(STD) : The Context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume.
Externally appears same as S5, but may have different wake events.
CHP3_SLPS5* S5, Soft Off(SOFF) : System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking.
REVISION HISTORY
See rev notes in the changes file for more information.
7-3
7 Schematic Diagrams and PCB Silkscreen
7-4
CY28346
option ICS950810
7 Schematic Diagrams and PCB Silkscreen
No Stuff
CLK0_HCLK2*
CLK0_HCLK2
CLK0_ITP*
CLK0_ITP No Stuff
OPTION
682088
NO STUFF
P/N : 1209-001370
NO STUFF
7-1-1(c) Main Board Schematic Sheet 4 of 39(Clock Generator)
SEL1 SEL0 HOST CLK
0 0 66MHz
0 1 100MHz
1 0 200MHz
1 1 133MHz
X10
7 Schematic Diagrams and PCB Silkscreen
7-1-1(d) Main Board Schematic Sheet 5 of 39(Banias CPU)
X10 7-5
7-6
7 Schematic Diagrams and PCB Silkscreen
CLK0_HCLK2
CLK0_HCLK2*
Placed as close as possible to
each of the four VCCA pins.
7-1-1(e) Main Board Schematic Sheet 6 of 39(Banias CPU)
VCCA, VCCQ CHECK ??
CPU1_PREQ*
CPU1_PRDY*
CPU1_BPM3*
CPU1_BPM2*
CPU1_BPM1*
CPU1_BPM0*
GTLREF : Keep the Voltage divider within 0.5"
of the First GTLREF0 with Z0= 55 ohm trace CPU1_TDO
Minimize coupling of any switching signals to this net
COMP 0 , 2 <(COMP 1,3) should be connected
NO STUFF Z0=27.4 ohm (55 ohm) trace shorter than
NO STUFF
1/2 " to their respective Banias Pins
STUFFING OPTION
NO STUFF
X10
X10
Refer To Thermal Sensor Layout Guidelines.
- Place the Thermal Sensor close to a remote diode.
- Keep traces away from high voltage (+12V bus)
- Keep traces away from fast data buses and CRT signal.
- Use recommended trace widths and spacings (10mil)
- Place a ground plane under the traces.
- Use guard traces flanking DXP and DXN and connecting to GND
OPTION
near the CPU
CPU1_PREQ*
CPU1_PRDY*
CPU1_BPM3*
CPU1_BPM2*
CPU1_BPM1*
CPU1_BPM0* CPU1_TCK
CPU Core Voltage Table CPU1_TDI
CLK0_ITP CPU1_TDO
VID5 VID4 VID3 VID2 VID1 VID0 Voltage VID5 VID4 VID3 VID2 VID1 VID0 Voltage CLK0_ITP* CPU1_TMS
CPU1_TRST*
0 0 0 0 0 0 1.708 V 1 0 0 0 0 0 1.196 V Northwood-B CPU1_TCK
0 0 0 0 0 1 1.692 V 1 0 0 0 0 1 1.180 V (Interposer B d) CPU1_CPURST*
0 0 0 0 1 0 1.676 V 1 0 0 0 1 0 1.164 V
0 0 0 0 1 1 1.660 V 1 0 0 0 1 1 1.148 V ITP3_DBRESET*
0 0 0 1 0 0 1.644 V 1 0 0 1 0 0 1.132 V
0 0 0 1 0 1 1.628 V 1 0 0 1 0 1 1.116 V
0 0 0 1 1 0 1.612 V 1 0 0 1 1 0 1.100 V
0
- -
0 0 1 0 1 1 1.596 V 1 - 0 1 1 1 1.084 V
0 0 1 0 0 0 1.580 V 1 0 1 0 0 0 1.068 V
7-1-1(f) Main Board Schematic Sheet 7 of 39(Thermal Sensor & VID)
0 0 1 0 0 1 1.564 V 1 0 1 0 0 1 1.052 V
0 0 1 0 1 0 1.548 V 1 0 1 0 1 0 1.036 V
0 0 1 0 1 1 1.532 V 1 0 1 0 1 1 1.020 V
0 0 1 1 0 0 1.516 V 1 0 1 1 0 0 1.004 V ITP - FLEX700
0 0 1 1 0 1 1.500 V 1 0 1 1 0 1 0.988 V
0 0 1 1 1 0 1.484 V 1 1 0 1 1 0 0.972 V
0 0 1 1 1 1 1.468 V 1 0 1 1 1 1 0.956 V
0 1 0 0 0 0 1.452 V 1 1 0 0 0 0 0.940 V
0 1 0 0 0 1 1.436 V 1 1 0 0 0 1 0.924 V
0 1 0 0 1 0 1.420 V 1 1 0 0 1 0 0.908 V
0 1 0 0 1 1 1.404 V 1 1 0 0 1 1 0.892 V
0 1 0 1 0 0 1.388 V 1 1 0 1 0 0 0.876 V
0 1 0 1 0 1 1.372 V 1 1 0 1 0 1 0.860 V
Highest Freq. 0 1 0 1 1 0 1.356 V 1 1 0 1 1 0 0.844 V Lowest Freq.
-
0 1 0 1 1 1 1.340 V 1 1 0 1 1 1 0.828 V
0 1 1 0 0 0 01.324 V 1 1 1 0 0 0.812 V
0 1 1 0 0 1 01.308 V 1 1 1 0 1 0.796 V
0 1 1 0 1 0 1.292 V 1 1 1 0 1 0 0.780 V
0 1 1 0 1 1 1.276 V 1 1 1 0 1 1 0.764 V
0 1 1 1 0 0 1.260 V 1 1 1 1 0 0 0.748 V Deeper Sleep
0 1 1 1 0 1 1.244 V 1 1 1 1 0 1 0.732 V
0 1 1 1 1 0 1.228 V 1 1 1 1 1 0 0.716 V
0 1 1 1 1 1.212 V 1 1 1 1 1 1 0.700 V
1
7-7
7 Schematic Diagrams and PCB Silkscreen
7 Schematic Diagrams and PCB Silkscreen
7-1-1(g) Main Board Schematic Sheet 8 of 39(MCH-M)
Reference Voltage Input for Compensation Logic.
Routing : 12 mil trace, 10 mil space
7-8 X10
X10
7-1-1(h) Main Board Schematic Sheet 9 of 39(MCH-M)
Value Check?
Place the R,C within 1" of the MCH-M.
DDR Feedback Routing
MCH signal ball to signal Via = Max 40 mil
DDR Clocks Routing MCH output signal via to input signal via = 95mil ~ 105 mil
> SCK/SCK#[0] = SCK/SCK#[1] = SCK/SCK#[2] RCVEN Sinal must be routed on the same layer as the memory clocks.
> SCK/SCK#[3] = SCK/SCK#[4] = SCK/SCK#[5]
> Differential clock length must be 1~2" longer than Strobe signals.
> Differential clock length must be 1~3" longer than Control and Command signals.
7-9
7 Schematic Diagrams and PCB Silkscreen
7-10
NO STUFF
40.2 ohm(HeatherCanyon0.9)
7 Schematic Diagrams and PCB Silkscreen
NO STUFF
RSVD1, RSVD2, ETS CHECK ??
Place near MCH Place near AGP
7-1-1(i) Main Board Schematic Sheet 10 of 39(MCH-M)
NO STUFF
ST1 ST2 MCH Strap
X 1 DDR
0 X TEST
1 X 400 MHz
X10
7 Schematic Diagrams and PCB Silkscreen
7-1-1(j) Main Board Schematic Sheet 11 of 39(DDR-SODIMM)
P/N : 3709-001196
P/N : 3709-001193
X10 7-11
7 Schematic Diagrams and PCB Silkscreen
7-1-1(k) Main Board Schematic Sheet 12 of 39(DDR-S Termination)
7-12 X10
7 Schematic Diagrams and PCB Silkscreen
7-1-1(l) Main Board Schematic Sheet 13 of 39(DDR-P Termination)
Place 1 Cap close to every 2 pullup resisters terminated to +V1.25
X10 7-13
7-14
NO STUFF
Place resistor near ICH4-m
Place series termination within
2 inches of ICH4-m. Value check?
7 Schematic Diagrams and PCB Silkscreen
Hub I/F : Route Signal with 5/20 trace/space routing.
Signals must match +/- 0.1" of Strobe signals.
PLACE RCOMP Resistor within 0.5" of ICH pad using thick trace
RCOMP R should be 2/3 board impedance
NO STUFF
7-1-1(m) Main Board Schematic Sheet 14 of 39(ICH-4)
X10
X10
NO STUFF
ICH4-m Strapping Options
Function Default
ICH_SPKR No Reboot No Stuff
AC97_SDOUT Safe Mode No Stuff
PC/PCI GNTA* A16 swap override No Stuff
EEP_DOUT Reserved No Stuff
Primary CODEC : AUDIO
Secondary CODEC : MODEM
NO STUFF
USB PORT
USB0 Port A
USB1 Port B
USB2 Bluetooth
USB3 Finger Print
7-1-1(n) Main Board Schematic Sheet 15 of 39(ICH-4)
No stuff
7-15
7 Schematic Diagrams and PCB Silkscreen
7 Schematic Diagrams and PCB Silkscreen
7-1-1(o) Main Board Schematic Sheet 16 of 39(ICH-4)
0 ~ 5V
0 ~ 3.3V
7-16 X10
7 Schematic Diagrams and PCB Silkscreen
7-1-1(p) Main Board Schematic Sheet 17 of 39(Firmware HUB)
X10 7-17
7-18
VGA3_GPIO0
VGA3_VIPHAD1 VGA3_BKLTON
VGA3_VIPHAD0 VGA3_LCDVDDON
VGA3_VIPD(0:7) VGA3_SSON
CHP3_SUSSTAT*
AGP1_GSTOP*
VGA3_GPIO7
AGP1_GAD(31:0)
AGP1_ADSTB0*
AGP1_ADSTB1*
USER(3)
USER(2)
Option USER(1)
USER(0)
VGA3_RED Test Option
VGA3_GREEN
VGA3_VIPHAD1 VGA3_BLUE
VGA3_VIPHAD0
VGA3_VIPD(1) VGA3_C
VGA3_VIPD(0) VGA3_Y
VGA3_GPIO7
VGA3_HSYNC
7 Schematic Diagrams and PCB Silkscreen
VGA3_VSYNC CHP3_SUSSTAT*
Option
Panel ID Switch VGA3_CLK+
VGA3_CLK-
VGA3_A0+
VGA3_A0-
VGA3_A1+ VGA3_GPIO0
VGA3_A1-
VGA3_A2+
VGA3_A2-
AGP1_GCBE*(0)
AGP1_GCBE*(1) MAP17 232
AGP1_GCBE*(2)
GPIO(7) - Gfx Core Voltage Switching
AGP1_GCBE*(3)
(Geforce4Go 420) GPIO(6) 0 Hardware suspend
CLK3_AGP66
PCI3_RST* GPIO(5) - Spread spectrum support
AGP1_GREQ* - Panel power Good signal
GPIO(4)
AGP1_GGNT*
AGP1_GPAR GPIO(3) - Panel power enable
AGP1_GSTOP* -
AGP1_GDEVSEL*
GPIO(2) Backlight enable
AGP1_GIRDY* GPIO(1:0) - GPIO
AGP1_GTRDY*
AGP1_GFRAME*
PCI3_INTB*
CHP3_C3STAT*
AGP3_BUSY*
AGP1_RBF*
AGP1_WBF*
7-1-1(q) Main Board Schematic Sheet 18 of 39(Nvida Map31)
AGP1_PIPE*
AGP1_ST(0) VGA3_SSOUT
AGP1_ST(1)
AGP1_ST(2)
VGA3_GPIO0 VGA3_SSOUT
AGP1_VREF VGA3_SSON
CHP3_SUSSTAT*
AGP1_ADSTB0
AGP1_ADSTB0*
AGP1_ADSTB1
AGP1_ADSTB1*
VGA3_DDCD
VGA3_DDCC
X10
X10
Place close to GPU Place close to the BGA
Place on bottom : North-West
Place closest to the GPU
Place under the GPU
Place on bottom : South-West
Place close to GPU
Place on the bottom side under the BGA
FBVDD (VDDFBC) : 2.0 ~2.5V
FBVDDQ (VDDFBIO) : 1.8 ~2.5V
Place bottom, center of GPU
Place bottom, close to GPU
No Stuff
MSTRAPSEL(0)
MSTRAPSEL(1)
MSTRAPSEL(2)
MSTRAPSEL(3)
7-1-1(r) Main Board Schematic Sheet 19 of 39(Nvidia Map31)
MIC5205BM5 (Adjustable)
VGA3_DVOD(0:11)
Ra
ADJ
Ra Rb Vout VGA3_DVOHSYNC
Rb
12k 15k 2.79V
11.5k 15k 2.86V
12k 17.4k 3.04V
12k 20k 3.31V
Vout = 1.242V x (1+R2/R1)
7-19
7 Schematic Diagrams and PCB Silkscreen
7-20
Strapping Option
VIPD(2):DVOD(10) xx00 ROM Type ( 00 : Parallel )
DVOD(11) xxx1 BUS Type ( 1 : AGP mode, 0 : PCI mode )
HSYNC,VIPD 0110 PCI_DEV_ID ( 0110 : NV17-MAP)
CKE
VIPD(7) xxx0 AGP Fastwrite ( 0 : Enable, 1 : Disable )
DVOD[9] xxx0 AGP4X ( 0 : 4X enable, 1 : 4X disable )
DVOD[8:7] xx01 TV Mode ( 01 : NTSC )
VIPD(6):DVOD(6) xx10 Crystal ( 10 : 27 MHz )
DVOD[5:2] 1101 RAM Cfg ( 1101 : 4Mx32 DDR SDRAM )
DVOD(1) xxx0 Sub Vendor ( 0 : System BIOS, 1: Adapter BIOS )
DVOD(0) xxx1 PCI_AD_Swap ( 1 : Normal, 0 : Reverse )
VGA3_VIPD(7)
32MB 64MB
VGA3_DVOHSYNC
VGA3_DVOHSYNC LOW HIGH
VGA3_VIPD(3) HIGH LOW
VGA3_VIPD(3)
VGA3_VIPD(5) HIGH LOW
VGA3_VIPD(4) LOW HIGH
7 Schematic Diagrams and PCB Silkscreen
VGA3_VIPD(5)
VGA3_VIPD(4)
VGA3_VIPD(6)
VGA3_DVOD(6)
VGA3_VIPD(2)
VGA3_DVOD(10)
VGA3_DVOD(11)
VGA3_DVOD(9)
VGA3_DVOD(8)
7-1-1(s) Main Board Schematic Sheet 20 of 39(Nvidia Map31)
VGA3_DVOD(7)
MSTRAPSEL(0)
VGA3_DVOD(2)
MSTRAPSEL(1)
VGA3_DVOD(3)
MSTRAPSEL(2)
VGA3_DVOD(4)
MSTRAPSEL(3)
VGA3_DVOD(5)
VGA3_DVOD(1)
VGA3_DVOD(0)
X10
7 Schematic Diagrams and PCB Silkscreen
7-1-1(t) Main Board Schematic Sheet 21 of 39(LCD_Connector)
LCD CONNECTOR
X10 7-21
7-22
* GUARD GROUND *
Apply Guard Grounding to Following Signals
1) Xtal for X1/X0 (Y1 24.576MHz) and its capacitors
2) FIL0, REXT and VREF
3) TPBIAS0, TPAP0, TPAN0, TPBP0, and TPBN0
4) TPBIAS1, TPAP1, TPAN1, TPBP1, and TPBN1
Terminators -> Close to R5C590
Max.:10mm, Typ: 5mm
Should be compact circuit area
PCI3_AD(0:31)
For Internal Analog
7 Schematic Diagrams and PCB Silkscreen
--> Place XTAL near R5C590 as close as possible
682097
CLK3_PCLKCB
PCI3_RST*
KBC3_PWRGD
No Stuff
PCI3_CLKRUN*
CHP3_PME*
PCI3_CBE0*
PCI3_CBE1*
PCI3_CBE2*
PCI3_CBE3*
PCI3_PAR
PCI3_DEVSEL*
PCI3_FRAME*
7-1-1(u) Main Board Schematic Sheet 22 of 39(Cardbus & 1394)
PCI3_GNT0*
PCI3_AD(19)
PCI3_IRDY*
PCI3_PERR*
PCI3_REQ0*
PCI3_SERR*
PCI3_STOP*
PCI3_TRDY*
CBS3_SPKR
Capacitors should be located near R5C590 chipset
PCI3_INTA*
PCI3_INTB*
PCI3_INTC*
X10
X10
CARDBUS SOCKET CONNECTOR
CA3_VCC
CB3_D5
CB3_B4
CB3_J1
CB3_B8
Capacitors should be located Capacitors should be located
near R5C590 near R5C590
A_MC_CD*
A_CD2*
MS_SCLK
CB3_CAD(0:31)
MS_RFU7
MemoryStick Socket
CB3_CRST*
A_CD2*
A_CD1*
No Stuffing
CB3_CCLK MS_SCLK
CB3_CCLKRUN*
CB3_CRST*
Switched Power Output Group
CB3_CCBE0* MS_RFU7
CB3_CCBE1*
CB3_CCBE2* CA3_VCC
CB3_CCBE3*
CB3_CPAR
CA3_VPP
CB3_CAUDIO is removed
CB3_CCD1* A_CD1*
CB3_CCD2* A_CD2*
CB3_CDEVSEL* CB3_VCC
CB3_CFRAME*
CB3_CGNT* CB3_AVCC3*
CB3_CINT* CB3_AVCC5* CB12_VPP
CB3_CIRDY* CB3_AVPP0
CB3_CPERR* CB3_AVPP1
CB3_CREQ*
CB3_CSERR* CB3_BVCC3*
CB3_BVCC5*
7-1-1(v) Main Board Schematic Sheet 23 of 39(Cardbus Socket)
CB3_CSTOP* CB3_BVPP0
CB3_CSTSCHG CB3_BVPP1
CB3_CTRDY* A_MC_CD*
CB3_CVS1 A_CD1*
CB3_CVS2
CB3_BVPP1 CB3_AVPP1
CB3_BVPP0 CB3_AVPP0
CB3_BVCC3* CB3_AVCC3*
CB3_BVCC5* CB3_AVCC5*
emarF tekcoS
* SHIELD GROUND *
Apply Shiled Grounding to Following Signals;
1) CB3_CCLK (A1) 2) A_MS_SCLK (J20)
7-23
7 Schematic Diagrams and PCB Silkscreen
7 Schematic Diagrams and PCB Silkscreen
7-1-1(w) Main Board Schematic Sheet 24 of 39(Mini PCI)
MINIPCI
5.3mm
7-24 X10
X10
Place each caps near the pinof CS4299
NO STUFF
682097
HP_IN
AUD5_SPK_R-
AUD5_SPK_L-
AUD5_MIC_CODEC
NO STUFF LID3_SWITCH*
NO STUFF
7-1-1(x) Main Board Schematic Sheet 25 of 39(Audio Codec & AMP)