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Global LCD Panel Exchange Center www.panelook.com
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Global LCD Panel Exchange Center www.panelook.com
Issued Date: Sep. 22, 2005
Model No.: N154I1-L0A
Approval
- CONTENTS -
REVISION HISTORY ------------------------------------------------------- 3
1. GENERAL DESCRIPTION ------------------------------------------------------- 5
1.1 OVERVIEW
1.2 FEATURES
1.3 APPLICATION
1.4 GENERAL SPECIFICATIONS
1.5 MECHANICAL SPECIFICATIONS
2. ABSOLUTE MAXIMUM RATINGS ------------------------------------------------------- 6
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
2.2 ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
2.2.2 BACKLIGHT UNIT
3. ELECTRICAL CHARACTERISTICS ------------------------------------------------------- 8
3.1 TFT LCD MODULE
3.2 BACKLIGHT UNIT
4. BLOCK DIAGRAM ------------------------------------------------------- 10
4.1 TFT LCD MODULE
4.2 BACKLIGHT UNIT
5. INPUT TERMINAL PIN ASSIGNMENT ------------------------------------------------------- 11
5.1 TFT LCD MODULE
5.2 BACKLIGHT UNIT
5.3 TIMING DIAGRAM OF LVDS INPUT SIGNAL
5.4 COLOR DATA INPUT ASSIGNMENT
5.5 EDID DATA STRUCTURE
5.6 EDID SIGNAL SPECIFICATION
6. INTERFACE TIMING ------------------------------------------------------- 19
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
6.2 POWER ON/OFF SEQUENCE
7. OPTICAL CHARACTERISTICS ------------------------------------------------------- 21
7.1 TEST CONDITIONS
7.2 OPTICAL SPECIFICATIONS
8. PRECAUTIONS ------------------------------------------------------- 25
8.1 HANDLING PRECAUTIONS
8.2 STORAGE PRECAUTIONS
8.3 OPERATION PRECAUTIONS
9. PACKING ------------------------------------------------------- 26
9.1 CARTON
9.2 PALLET
10. DEFINITION OF LABELS ------------------------------------------------------- 29
10.1 CMO MODULE LABEL
10.2 CARTON LABEL
11.Outline Drawing ------------------------------------------------------- 30
2 /30
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Issued Date: Sep. 22, 2005
Model No.: N154I1-L0A
Approval
REVISION HISTORY
Page
Version Date Section Description
(New)
Ver 3.0 Jun.13,'05 All All Approval specification first issued.
Ver 3.1 July. 05,'05 4 1.4 Modify Surface Treatment from 3H to 2H
5 2.1 Modify Shock (Non-Operating) from 200G/2ms to 210G/3ms
Modify Humidity (%RH) from 5->90 to 8->95
6 2.2.2 Modify IL from 6.5mA to 6.0mA
7 3.1 Add Window XP pattern 390mA(typ) and 460mA(max)
Modify Power Supply Current at White from 400(typ) to 360(typ)
Add Max=420mA
Modify Power Supply Current at Black from 520(typ) to 430(typ)
Add Max=510mA
Modify Power Supply Current at Vertical Stripe from 560(typ) to 480(typ)
Add Max=560mA
8 3.2 Modify IL from 6.5mA to 6.0mA
11 5.1 Remove "or equivalent" of Connector Part No
Add description for "NC".
12 5.2 Remove "or equivalent" of Connector Part No
19 6.1 Add min of Clock Frequency = 47.4MHz
Add min of Vsync Frequency = 40Hz
Add Note(3) for min of Vsync Frequency.
Modify max of Frame Frequency from 2000lines to 1300lines.
20 6.2 Modify all of power on/off sequence timing spec.
21 7.2 Modify min of Average Luminance of White from 260nits to 270nits
Modify typical of Average Luminance of White from 300nits to 320nits
Modify Color Chromaticity (White) WX Min/Typ/Max from
0.283/0.313/0.343 to 0.285/0.313/0/341.
Modify Color Chromaticity (White) Wy Min/Typ/Max from
0.283/0.313/0.343 to 0.309/0.329/0/349.
Modify typical of Viewing Angle from 60/60/40/50 to 65/65/50/50.
24 7.2 Modify the Definition of White Variation (GW)
Ver 3.2 July. 12,'05 5 2.1 Modify Humidity (%RH) of operating temperature from 5->90 to 8->95
8 3.1 Remove pattern drawing.
18 6.1 Remove description for Hsync and Vsync of Note (1).
19 6.2 Modify power on/off sequence timing definition.
Ver 3.3 Aug.04,'05 4 1.4 Add Nitto denko "ARC150T" into surface treatment.
5 2.1 Add 5%<= %RH <= 95% (Ta<= 40degC) for storage temperature.
27 10.1 Modify the module label for Lenovo include descriptions.
28 10.2 Modify the carton label for Lenovo.
Ver 3.4 Aug.22, `05 5 2.1 Add "5%<= %RH <=95% (Ta<= 40 deg C) for storage temperature."
Into item (a) and remove item (e).
28 10.2 Modify the carton label again same as current model for Lenovo.
Ver 3.5 Sep.02,'05 All All Modify all of symbol of unit for read by different OS.
3 /30
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Issued Date: Sep. 22, 2005
Model No.: N154I1-L0A
Approval
Ver 3.6 Sep.22,'05 29 10.2 Change carton label type.
30 11 Add the tolerance of active area as "+/- 0.3mm" which is VESA
standard value.
Modify "Screw Hole Thread Depth xx MIN" instead of "DP=xx MAX".
Add the cross section picture of screw hole.
4 /30
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Issued Date: Sep. 22, 2005
Model No.: N154I1-L0A
Approval
1. GENERAL DESCRIPTION
1.1 OVERVIEW
N154I1 -L0A is a 15.4" TFT Liquid Crystal Display module with single CCFL Backlight unit and 30 pins
LVDS interface. This module supports 1280 x 800 Wide-XGA mode and can display 262,144 colors. The
optimum viewing angle is at 6 o'clock direction. The inverter module for Backlight is not built in.
1.2 FEATURES
- Thin and light weight
- WXGA (1280 x 800 pixels) resolution
- 3.3V LVDS (Low Voltage Differential Signaling) interface with 1 pixel/clock
- DE only mode
- Meet RoHS requirement
1.3 APPLICATION
- TFT LCD Notebook
1.4 GENERAL SPECIFICATI0NS
Item Specification Unit Note
Active Area 331.2 (H) x 207.0 (V) (15.4" diagonal) mm
(1)
Bezel Opening Area 335.0 (H) x 210.7 (V) mm
Driver Element a-si TFT active matrix - -
Pixel Number 1280 x R.G.B. x 800 pixel -
Pixel Pitch 0.2588 (H) x 0.2588 (V) mm -
Pixel Arrangement RGB vertical stripe - -
Display Colors 262,144 color -
Transmissive Mode Normally white - -
Hard coating (2H), AG Type, Nitto Denko
Surface Treatment - -
"ARC150T"
1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal(H) 343.5 344.0 344.5 mm
Module Size Vertical(V) 221.5 222.0 222.5 mm (1)
Depth(D) - 6.2 6.5 mm
Weight - 600 620 g -
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
5 /30
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Issued Date: Sep. 22, 2005
Model No.: N154I1-L0A
Approval
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Value
Item Symbol Unit Note
Min. Max.
Storage Temperature TST -20 +60 Deg C (1)
Operating Ambient Temperature TOP 0 +50 Deg C (1), (2)
Shock (Non-Operating) SNOP - 210 G (3), (5)
Vibration (Non-Operating) VNOP - 1.5 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 8%<= %RH <=95 %. (Ta <= 40 deg C) for operating temperature.
5%<= %RH <=95% (Ta<= 40 deg C) for storage temperature.
(b) Wet-bulb temperature should be 39 deg C Max. (Ta > 40 deg C).
(c) No condensation.
Relative Humidity (%RH)
100
95
80
60
Operating Range
40
20
8
Storage Range
-40 -20 0 20 40 60 80
Temperature (deg C)
Note (2) The temperature of panel surface should be 0 deg C Min. and 50 deg C Max.
Note (3) 3ms, half sine wave, 1 time for +/- X, +/- Y, +/- Z.
Note (4) 10 ~ 200 Hz, 0.5 Hr / Cycle, 1 cycles for each X, Y, Z. The fixing condition is shown as below:
At Room Temperature LCD Module
Side Mount Fixing Screw Side Mount Fixing Screw
Stage
Gap=2mm Bracket
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough
so that the module would not be twisted or bent by the fixture.
6 /30
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Model No.: N154I1-L0A
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2.2 ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
Value
Item Symbol Unit Note
Min. Max.
Power Supply Voltage Vcc -0.3 +4.0 V
(1)
Logic Input Voltage VIN -0.3 Vcc+0.3 V
2.2.2 BACKLIGHT UNIT
Value
Item Symbol Unit Note
Min. Max.
Lamp Voltage VL - 2.5K VRMS (1), (2), IL = 6.0 mA
Lamp Current IL - 7.0 mARMS
(1), (2)
Lamp Frequency FL - 80 KHz
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) Specified values are for lamp (Refer to Section 3.2 for further information).
7 /30
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Model No.: N154I1-L0A
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE Ta = 25 +/- 2 deg C
Value
Parameter Symbol Unit Note
Min. Typ. Max.
Power Supply Voltage Vcc 3.0 3.3 3.6 V -
Ripple Voltage VRP - - 100 mV -
Rush Current IRUSH - - 1.5 A (2)
White - 360 420 mA
Power Supply Current Black lcc - 430 510 mA
Window XP - 390 460 mA
Differential Input Voltage for "H" Level VIH - - +100 mV -
LVDS Receiver Threshold "L" Level VIL -100 - - mV -
Terminating Resistor RT - 100 - Ohm -
Note (1) The module should be always operated within above ranges.
Note (2) Measurement Conditions:
+3.3V
Q1 2SK1475
Vcc
C3
FUSE (LCD Module Input)
R1 1uF
47K
(High to Low)
(Control Signal)
Q2
R2
SW 2SK1470
1K
+12V
47K C2
VR1
C1
0.01uF
1uF
Vcc rising time is 470us
+3.3V
0.9Vcc
0.1Vcc
GND
470us
8 /30
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Model No.: N154I1-L0A
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3.2 BACKLIGHT UNIT Ta = 25 +/- 2 deg C
Value
Parameter Symbol Unit Note
Min. Typ. Max.
Lamp Input Voltage VL 612 680 748 VRMS IL = 6.0 mA
Lamp Current IL 2.0 6.0 6.5 mARMS (1)
- - 1110, 25 deg C VRMS (2)
Lamp Turn On Voltage VS
- - 1300, 0 deg C VRMS (2)
Operating Frequency FL 50 - 80 KHz (3)
Lamp Life Time LBL 10,000 - - Hrs (5)
Power Consumption PL - 4.08 - W (4), IL = 6.0 mA
Note (1) Lamp current is measured by utilizing a high frequency current meter as shown below:
HV (White)
LCD 1
LV (Black) Inverter
Module 2 A
Current Meter
Note (2) The voltage shown above should be applied to the lamp for more than 1 second after startup.
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may generate interference with horizontal synchronous frequency from the
display, and this may cause line flow on the display. In order to avoid interference, the lamp
frequency should be detached from the horizontal synchronous frequency and its harmonics as far
as possible.
Note (4) PL = IL x VL
Note (5) The lifetime of lamp is defined as the time when it continues to operate under the conditions at Ta
= 25 +/-2 degC and IL = 6.0 mARMS until one of the following events occurs:
(a) When the brightness becomes <= 50% of its original value.
(b) When the effective ignition length becomes <= 80% of its original value. (Effective ignition
length is defined as an area that the brightness is less than 70% compared to the center point.)
Note (6) The waveform of the voltage output of inverter must be area-symmetric and the design of the
inverter must have specifications for the modularized lamp. The performance of the Backlight,
such as lifetime or brightness, is greatly influenced by the characteristics of the DC-AC inverter for
the lamp. All the parameters of an inverter should be carefully designed to avoid generating too
much current leakage from high voltage output of the inverter. When designing or ordering the
inverter please make sure that a poor lighting caused by the mismatch of the Backlight and the
inverter (miss-lighting, flicker, etc.) never occurs. If the above situation is confirmed, the module
should be operated in the same manners when it is installed in your instrument.
9 /30
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Model No.: N154I1-L0A
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4. BLOCK DIAGRAM
4.1 TFT LCD MODULE
Rxin0(+/-)
SCAN DRIVER IC
Rxin1(+/-) LVDS INPUT /
TIMING CONTROLLER TFT LCD PANEL
(JAE-FI-XB30SL-HF10)
Rxin2(+/-)
INPUT CONNECTOR
(1280x3x800)
CLK(+/-)
Vcc
GND DC/DC CONVERTER &
REFERENCE VOLTAGE
DataEDID GENERATOR DATA DRIVER IC
CLKEDID
VEDID
VL LAMP CONNECTOR
(JST-BHSR-02VS-1) BACKLIGHT UNIT
4.2 BACKLIGHT UNIT
1 HV (White)
2 LV (Black)
10 /30
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Model No.: N154I1-L0A
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE
Pin Symbol Description Polarity Remark
1 Vss Ground -
2 Vcc Power Supply +3.3 V -
3 Vcc Power Supply +3.3 V -
4 VEDID DDC +3.3 V
5 NC - - -
6 CLKEDID DDC Clock
7 DataEDID DDC Data
8 Rxin0- LVDS Differential Data Input Negative -
9 Rxin0+ LVDS Differential Data Input Positive R0~R5,G0
10 Vss Ground
11 Rxin1- LVDS Differential Data Input Negative -
12 Rxin1+ LVDS Differential Data Input Positive G1~G5,B0,B1
13 Vss Ground
14 Rxin2- LVDS Differential Data Input Negative -
15 Rxin2+ LVDS Differential Data Input Positive B2~B5,Hsync,Vsync,DE
16 Vss Ground
17 CLK- LVDS Clock Data Input Negative
18 CLK+ LVDS Clock Data Input Positive LVDS Level
19 Vss Ground
20 NC - - -
21 NC - - -
22 NC - - -
23 NC - - -
24 NC - - -
25 NC - - -
26 NC - - -
27 NC - - -
28 NC - - -
29 NC - - -
30 NC - - -
Note (1) Connector Part No.: JAE-FI-XB30SL-HF10
Note (2) User's connector Part No: JAE-FI-X30C2L or equivalent
Note (3) NC means no further connection is suggested.
11 /30
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5.2 BACKLIGHT UNIT
Pin Symbol Description Color
1 HV High Voltage White
2 LV Ground Black
Note (1) Connector Part No.: JST-BHSR-02VS-1
Note (2) User's connector Part No.: JST-SM02B-BHSS-1-TB or equivalent
5.3 TIMING DIAGRAM OF LVDS INPUT SIGNAL
CLK+
T/7
Rxin2 IN20 IN19 IN18 IN17 IN16 IN15 IN14
DE Vsync Hsync B5 B4 B3 B2
Rxin1 IN13 IN12 IN11 IN10 IN9 IN8 IN7
B1 B0 G5 G4 G3 G2 G1
Rxin0
IN6 IN5 IN4 IN3 IN2 IN1 IN0
G0 R5 R4 R3 R2 R1 R0
Signal for 1 DCLK Cycle (T)
12 /30
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Model No.: N154I1-L0A
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5.4 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 6-bit gray scale data input for
the color. The higher the binary input the brighter the color. The table below provides the assignment of
color versus data input.
Data Signal
Color Red Green Blue
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Green 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0
Basic Blue 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Colors Cyan 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Magenta 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1
Yellow 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Red(0)/Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red(1) 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Gray Red(2) 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Scale : : : : : : : : : : : : : : : : : : :
Of : : : : : : : : : : : : : : : : : : :
Red Red(61) 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Red(62) 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Red(63) 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Green(0)/Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green(1) 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Gray Green(2) 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Scale : : : : : : : : : : : : : : : : : : :
Of : : : : : : : : : : : : : : : : : : :
Green Green(61) 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0
Green(62) 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0
Green(63) 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0
Blue(0)/Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Blue(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Gray Blue(2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Scale : : : : : : : : : : : : : : : : : : :
Of : : : : : : : : : : : : : : : : : : :
Blue Blue(61) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
Blue(62) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0
Blue(63) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Note (1) 0: Low Level Voltage, 1: High Level Voltage
13 /30
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Model No.: N154I1-L0A
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5.5 EDID DATA STRUCTURE
The EDID (Extended Display Identification Data) data formats are to support displays as defined in the
VESA Plug & Display and FPDI standards.
Byte # Byte # Value Value
Field Name and Comments
(decimal) (hex) (hex) (binary)
00
FF
FF
FF
FF
FF
FF
00
ID system Manufacturer Name 24
Compressed ASCII 4D
ID Product Code 74
ID Product Code 23
00
00
00
00
00
00
01
03
80
21
15
78
0A
63
45
9A
55
51
89
28
23
50
54
00
00
00
Standard timing ID # 1 01
Standard timing ID # 1 01
Standard timing ID # 2 01
Standard timing ID # 2 01
14 /30
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Standard timing ID # 3 01
Standard timing ID # 3 01
Standard timing ID # 4 01
Standard timing ID # 4 01
Standard timing ID # 5 01
Standard timing ID # 5 01
Standard timing ID # 6 01
Standard timing ID # 6 01
Standard timing ID # 7 01
Standard timing ID # 7 01
Standard timing ID # 8 01
Standard timing ID # 8 01
Detailed timing description # 1 Pixel clock ("71.11MHz", According
to VESA CVT Rev1.1) C7
1B
00
A0
50
20
17
30
30
20
36
00
4B
CF
10
00
00
1C
Pixel Clock/10,000 (LSB) 26
Pixel Clock/10,000 (MSB) / 17
00
A0
50
20
17
30
30
20
36
00
4B
CF
15 /30
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10
00
00
1C
00
00
00
0F
00
Refresh Rate #1 81
Refresh Rate #1 0A
Refresh Rate #1 32
Refresh Rate #2 81
Refresh Rate #2 0A
Refresh Rate #2 28
1E
01
00
EISA manufacturer code(3 Character ID) -CMO 0D
Compressed ASCII AF
Panel Supplier Reserved - Product code -1509 09
(Hex, LSB first) 15
00
00
00
FE
00
4E
31
35
34
49
31
0A
20
20
20
20
20
20
00
4B
16 /30
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5.6 EDID SIGINAL SPECIFICATION
(1) EDID Power
Parameter Symbol Test Condition Min. Typ. Max. Unit
Power supply
Vcc -- 2.7 -- 5.5 V
voltage
(2) DC characteristics
Parameter Symbol Test Condition Min Typ Max Unit
Supply current Vcc=5.0V Icc READ at 100kHz -- 0.4 1.0 mA
Supply current Vcc=5.0V Icc WRITE at 100kHz -- 2.0 3.0 mA
Standby Current ISB Vin=Vcc or Vss -- 1.6 4.0 A
Input Leakage Current ILI Vin=Vcc or Vss -- 0.1 3.0 A
Onput Leakage Current ILO Vout=Vcc or Vss -- 0.05 3.0 A
Input Low Level VIL -- -1.0 -- Vcc x 0.3 V
Input High Level VIH -- Vcc x 0.7 -- Vcc+0.5 V
Output Low Level Vcc=1.8V VOL1 IOL=0.15mA -- -- 0.2 V
Output Low Level Vcc=3.0V VOL2 IOL=2.1mA -- -- 0.4 V
17 /30
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(3) AC characteristics (VCC=2.5~5.5V standard operation mode)
Parameter Symbol Min Max Unit
Clock Frequency, SCL FSCL -- 100 kHz
Clock Pulse Width Low TLOW 4.7 -- s
Clock Pulse Width High THIGH 4.0 -- s
Noise Suppression Time TI -- 100 ns
Clock Low to Data Out Valid TAA 0.1 4.5 s
Time the bus must be free
before a new transmission TBUF 4.7 -- s
can start
Start Hold Time THD.STA 4.0 -- s
Start Set-up Time TSU.STA 4.7 -- s
Data in Hold Time THD.DAT 0 -- s
Data in Set-up Time TSU.DAT 200 -- ns
Inputs Rise Time TR -- 1.0 s
Inputs Fall Time TF -- 300 ns
Stop Set-up Time TSU.STO 4.7 -- s
Data Out Hold Time TDH 100 -- ns
Write Cycle Time TWR -- 10 ms
18 /30
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
Frequency 1/Tc 47.4 71 80 MHz -
Clock High Time TCH 13 - - nsec -
Low Time TCL 13 - - nsec -
Setup Time TDS 4 - - nsec -
Data
Hold Time TDH 4 - - nsec -
Vsync Frequency Frequency Vsync 40 60 - Hz (2)
Hsync Frequency Frequency Hsync - 49.4 - KHz
Data Enable Pulse width TDEP 100 - - clocks
Data Enable Setup Time TES 3.5 4.0 - nsec
Frame Frequency Cycle TV 804 823 1300 lines -
Vertical Active Display Term Display Period TVD 800 800 800 lines -
One Line Scanning Time Cycle TH 1350 1440 2000 clocks (1)
Horizontal Active Display Term Display Period THD 1280 1280 1280 clocks -
Note (1) The duration of DE signal must be longer than 1 clock period at every horizontal sync. period.
Note (2) If frame rate is operated at 40Hz, flicker phenomenon may be observed.
INPUT SIGNAL TIMING DIAGRAM
TVD
DE
TH
DCLK
TC
THD
DE
DATA Valid display data (1280 pixels)
SIGNAL
TC
TCH TCL
50%
DCLK
TDS TDH
DISPLAY
50%
DATA
TES
DE 50%
19 /30
Version 3.6
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
Global LCD Panel Exchange Center www.panelook.com
Issued Date: Sep. 22, 2005
Model No.: N154I1-L0A
Approval
6.2 POWER ON/OFF SEQUENCE
Timing Specifications:
t1 <= 10 msec
0 < t2 <= 50 msec
t3 >= 0 msec
t4 >= 150 msec
t5 >= 200 msec
t6 >= 0 msec
t7 <= 10 msec
Note (1) Please avoid floating state of interface signal at invalid period.
Note (2) When the interface signal is invalid, be sure to pull down the power supply of LCD Vcc to 0 V.
Note (3) The Backlight inverter power must be turned on after the power supply for the logic and the
interface signal is valid. The Backlight inverter power must be turned off before the power supply
for the logic and the interface signal is invalid.
Note (4) Sometimes some slight noise shows when LCD is turned off (even backlight is already off). To
avoid this phenomenon, we suggest that the Vcc falling time had better to follow
t7 >= 5 msec
20 /30
Version 3.6
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
Global LCD Panel Exchange Center www.panelook.com