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Customer's Acceptance Specification
TO: LG Electronics Inc.
Accepted By: Date :
Customer's Acceptance Specification
Type 15.0 UXGA Color TFT/LCD Module
Model Name:IAUX14P
Document Control Number : CAS I-914P-L01
Issued By : T. TOKUDA Date: December 5,2002
Sales Support
International Display Technology
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Customer's Acceptance Specification
i Contents
i Contents
ii Record of Revision
1.0 Handling Precautions
2.0 General Description
2.1 Characteristics
2.2 Functional Block Diagram
3.0 Absolute Maximum Ratings
4.0 Optical Characteristics
4.1 Luminance Uniformity
5.0 Signal Interface
5.1 Connectors
5.2 Interface Signal Connector
5.3 Interface Signal Description
5.3.1 E-EDID
5.4 Interface Signal Electrical Characteristics
5.4.1 Signal Electrical Characteristics for LVDS Receiver
5.4.2 LVDS Receiver Internal Circuit
5.4.3 Recommended Guidelines for Motherboard PCB Design and Cable Selection
5.5 Signal for Lamp connector
6.0 Pixel format image
7.0 Parameter guide line for CFL Inverter
8.0 Interface Timings
8.1 Timing Characteristics
8.2 Timing Definition
9.0 Power Consumption
10.0 Power ON/OFF Sequence
11.0 Mechanical Characteristics
12.0 National Test Lab Requirement
13.0 Packaging Specification
14.0 Label
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ii Record of Revision
Date Document Revision Page Summary
December 5,2002 CAS I-914P-L01 All First Edition for LG Electronics Inc.
Based on Engineering Spec. OEM I-914P-01.
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1.0 Handling Precautions
O If any signals or power lines deviate from the power on/off sequence, it may cause shorten the life of the
LCD module.
O The LCD panel and the CFL are made of glass and may break or crack if dropped on a hard surface, so
please handle them with care.
O CMOS-ICs are included in the LCD panel. They should be handled with care, to prevent electrostatic
discharge.
O Do not press the reflector sheet at the back of the LCD module to any directions.
O Do not stick the adhesive tape on the reflector sheet at the back of the LCD module.
O Please handle care when mount in the system cover. Mechanical damage for lamp cable and for lamp
connector may cause safety problems.
O Small amount of materials having no flammability grade is used in the LCD module. The LCD module
should be supplied by power complied with requirements of Limited Power Source (2.5, IEC60950 or
UL60950), or be applied exemption conditions of flammability requirements (4.7.3.4, IEC60950 or
UL60950) in an end product.
O The LCD module is designed so that the CFL in it is supplied by Limited Current Circuit (2.4, IEC60950 or
UL60950).
O The fluorescent lamp in the liquid crystal display(LCD) contains mercury. Do not put it in trash that is
disposed of in landfills. Dispose of it as required by local ordinances or regulations.
O Never apply detergent or other liquid directly to the screen.
O Wipe off water drop immediately. Long contact with water may cause discoloration or spots.
O When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth; do not use solvents or
abrasives.
O Do not touch the front screen surface in your system, even bezel.
O The information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by International Display Technology for any
infringements of patents or other right of the third partied which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of International
Display Technology or others.
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2.0 General Description
This specification applies to the Type 15.0 Color TFT/LCD Module 'IAUX14P'.
This module is designed for a display unit of notebook style personal computer.
The screen format and electrical interface are intended to support the UXGA (1600(H) x 1200(V)) screen.
Support color is native 262K colors(RGB 6-bit data driver).
All input signals are LVDS(Low Voltage Differential Signaling) interface compatible.
This module does not contain an inverter card for backlight.
2.1 Characteristics
The following items are characteristics summary on the table under 25 degree C condition:
CHARACTERISTICS ITEMS SPECIFICATIONS
Screen Diagonal [mm] 381
Pixels H x V 1600(x3) x 1200
Active Area [mm] 304.8(H) x 228.6(V)
Pixel Pitch [mm] 0.1905(per one triad) x 0.1905
Pixel Arrangement R,G,B Vertical Stripe
Weight [grams] 690 Typ., 725 Max.
Physical Size [mm] 317.3(W) x 242.0(H) x 7.2(D) Typ./7.5(D) Max.
Display Mode Normally Black
Support Color Native 262K colors(RGB 6-bit data driver)
White Luminance [cd/m 2] (center) 200 Typ.
Contrast Ratio 400 : 1 Typ.
Optical Rise Time + Fall Time [msec] 60 Typ., 150 Max.
Nominal Input Voltage VDD [Volt] +3.3 Typ.
Power Consumption [Watt](VDD) 2.9 Typ., 3.8 Max.
4.5 Typ.,(W/o inverter loss)
Lamp Power Consumption [Watt]
5.0 Max.,(W/o inverter loss)
Typical Power Consumption [Watt] 7.4 Typ., 8.8 Max.(W/o inverter loss)
Electrical Interface 8 pairs LVDS(Even/Odd R/G/B Data(6bit), 3sync signals, Clock)
Temperature Range [degree C]
Operating 0 to +50
Storage (Shipping) -20 to +60
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2.2 Functional Block Diagram
The following diagram shows the functional block of this Type 15.0 Color TFT/LCD Module.
The first LVDS port transmits even pixels while the second LVDS port transmits odd pixels.
X-Driver
Y-Driver
< 8 pairs LVDS > LCD DRIVE
CARD
6bit color data
for R/G/B
(even/odd)
EVEN
PIXEL LCD TFT ARRAY/CELL
Controller
DTCLK(even/odd)
ODD
PIXEL
1600(R/G/B) x 1200
DSPTMG
Dual LVDS
Vsync RECEIVER
Hsync
G/A
VEEDID
CLKEEDID DC-DC
DataEEDID EEDID
Chip Converter Backlight Unit
Ref circuit
VDD
GND Lamp Connector
LCD-DRIVE Connector JST BHSR-02VS-1 (2pin)
JAE FI-XB30S-HF10 (30pin)
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3.0 Absolute Maximum Ratings
Absolute maximum ratings of the module is as follows :
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage VDD -0.3 +4.0 V
Input Signal Voltage VIN -0.3 VDD+0.3 V
CFL Ignition Voltage Vs - +1,600 Vrms (Note 2)
CFL Current ICFL - 8 mAms
CFL Peak Inrush Current ICFLP - 20 mA
Operating Temperature TOP 0 +50 deg.C (Note 1)
Operating Relative Humidity HOP 8 95 %RH (Note 1)
Storage Temperature TST -20 +60 deg.C (Note 1)
Storage Relative Humidity HST 5 95 %RH (Note 1)
Vibration 1.5 10-200 G Hz
Shock 50 18 G ms Rectangle wave
Note :
1. Maximum Wet-Bulb should be 39 degree C and No condensation.
2. Duration : 50msec Max. Ta=0 degree C
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4.0 Optical Characteristics
The optical characteristics are measured under stable conditions as follows under 25 degree C condition:
Item Conditions Specification
Typ. Note
Viewing Angle Horizontal (Right) 85 -
(Degrees) K}10 (Left) 85 -
Vertical (Upper) 85 -
K:Contrast Ratio K}10 (Lower) 85 -
Contrast ratio 400 -
Response Time Rising 30 -
(ms) Falling 30 -
Color Red x 0.569 +0.030
Chromaticity Red y 0.332 +0.030
(CIE) Green x 0.312 +0.030
Green y 0.544 +0.030
Blue x 0.149 +0.030
Blue y 0.132 +0.030
White x 0.313 +0.030
White y 0.329 +0.030
White Luminance (cd/m2) 200 Typ. 170 Min.
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The following is the note for the Optical Characteristics:
Z
Viewing or Measuring
Direction
Viewing or Measuring
Direction
-v +h
LEFT
UPPER
LOWER RIGHT
Y
X
CENTER OF LCD
(X=0,Y=0,Z=0)
w Chromaticity and White Balance are defined as the C.I.E. 1931 x,y coordinates at the center of
LCD. The Standard Equipments are as shown below table.
Item Standard Equipment
Viewing Angle MCPD-7000 by Ohtsuka Elec
Contrast MCPD-7000 by Ohtsuka Elec
Response Time BM5A by TOPCON OPTICAL Co.,Ltd.
White Luminance MCPD-7000 by Ohtsuka Elec
Luminance Uniformity MCPD-7000 by Ohtsuka Elec
Chromaticity MCPD-7000 by Ohtsuka Elec
White Balance MCPD-7000 by Ohtsuka Elec
The measurement is to be done after 30 minutes of Power-on of BackLight.
Unless otherwise specified, the ambient conditions are as following.
Ambient Temperature : 25 _ 2
+ ( degreeC )
Ambient Humidity : 25 - 85 (%)
Atmospheric Pressure : 86.0 - 104.0 ( kPa )
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4.1 Luminance Uniformity
When the backlight is on with all pels in the unselected state (white), the luminance uniformity is defined as
follows;
Average luminance is defined as follows.
L1 + L2 + L3 + L4 + L5
Average Luminance =
5
Luminance variation is measured by dividing the maximum luminance values of the 13 or 5 test points by the
minimum luminance of the 13 or 5 test points.
Maximum Luminance 13 Points (L1-L13)
Luminance Uniformity w1.65
Minimum Luminance 13 Points (L1-L13)
Maximum Luminance 5 Points (L1-L5)
Luminance Uniformity w1.25
Minimum Luminance 5 Points (L1-L5)
Figure. Average luminance and Luminance uniformity test points
10mm
L6 L7 L8
L1 L2
300
L9 L5 L10
600
L3 L4
900
L11 L12 L13
10mm
10mm 400 800 1200 10mm
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5.0 Signal Interface
5.1 Connectors
Physical interface is described as for the connector on module.
These connectors are capable of accommodating the following signals and will be following components.
Connector Name / Designation For Signal Connector
Manufacturer JAE
Type / Part Number FI-XB30S-HF10
Mating Receptacle Manufacture JAE
Mating Receptacle/Part Number FI-X30M
Connector Name / Designation For Lamp Connector
Manufacturer JST
Type / Part Number BHSR-02VS-1
Mating Type / Part Number SM02B-BHSS-1
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5.2 Interface Signal Connector
Pin # Signal Name Pin # Signal Name
1 GND 16 GND
2 VDD 17 ReCLKIN-
3 VDD 18 ReCLKIN+
4 VEEDID (Note 2,3) 19 GND
5 Reserved (Note 1) 20 RoIN0-
6 CLKEEDID (Note 2,4) 21 RoIN0+
7 DataEEDID (Note 2,4) 22 GND
8 ReIN0- 23 RoIN1-
9 ReIN0+ 24 RoIN1+
10 GND 25 GND
11 ReIN1- 26 RoIN2-
12 ReIN1+ 27 RoIN2+
13 GND 28 GND
14 ReIN2- 29 RoCLKIN-
15 ReIN2+ 30 RoCLKIN+
Note :
1. 'Reserved' pins are not allowed to connect any other line.
2. This LCD Module complies with "VESA ENHANCED EXTENDED DISPLAY IDENTIFICATION DATA
STANDARD Release A, Revision 1" and supports "EEDID version 1.3".
This module uses Serial EEPROM BR24C02FV (ROHM) or compatible as a EEDID function.
3. VEEDID power source shall be the current limited circuit which has not exceeding 1A. (Reference Document :
"Enhanced Display Data Channel (E-DDCTM) Proposed Standard", VESA)
4. Both CLKEEDID line and DataEEDID line are pulled-up with 10K ohm resistor to VEEDID power source line at LCD
panel, respectively.
Voltage levels of all input signals are LVDS compatible (except VDD,EEDID). Refer to "Signal Electrical
Characteristics for LVDS", for voltage levels of all input signals.
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5.3 Interface Signal Description
The LVDS receiver equipped in this LCD module is compatible with ANSI/TIA/TIA-644 standard.
PIN SIGNAL Description
# NAME
1 GND Ground
2 VDD +3.3V Power Supply
3 VDD +3.3V Power Supply
4 VEEDID EEDID 3.3V Power Supply
5 Reserved Reserved
6 CLKEEDID EEDID Clock
7 DataEEDID EEDID Data
8 ReIN0- Negative LVDS differential data input (Even R0-R5, G0)
9 ReIN0+ Positive LVDS differential data input (Even R0-R5, G0)
10 GND Ground
11 ReIN1- Negative LVDS differential data input (Even G1-G5, B0-B1)
12 ReIN1+ Positive LVDS differential data input (Even G1-G5, B0-B1)
13 GND Ground
14 ReIN2- Negative LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG)
15 ReIN2+ Positive LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG)
16 GND Ground
17 ReCLKIN- Negative LVDS differential clock input (Even)
18 ReCLKIN+ Positive LVDS differential clock input (Even)
19 GND Ground
20 RoIN0- Negative LVDS differential data input (Odd R0-R5, G0)
21 RoIN0+ Positive LVDS differential data input (Odd R0-R5, G0)
22 GND Ground
23 RoIN1- Negative LVDS differential data input (Odd G1-G5, B0-B1)
24 RoIN1+ Positive LVDS differential data input (Odd G1-G5, B0-B1)
25 GND Ground
26 RoIN2- Negative LVDS differential data input (Odd B2-B5)
27 RoIN2+ Positive LVDS differential data input (Odd B2-B5)
28 GND Ground
29 RoCLKIN- Negative LVDS differential clock input (Odd)
30 RoCLKIN+ Positive LVDS differential clock input (Odd)
Note :
1. Input signals of odd and even clock shall be the same timing.
2. The module uses a 100ohm resistor between positive and negative data lines of each receiver input.
3. Even : First Pixel data Odd : Second Pixel Data
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SIGNAL NAME Description
+RED 5 RED Data 5 (MSB)
+RED 4 RED Data 4
+RED 3 RED Data 3
+RED 2 RED Data 2
+RED 1 RED Data 1
+RED 0 RED Data 0 (LSB)
(EVEN/ODD)
Red-pixel Data: Each red pixel's brightness data consists of these 6 bits pixel data.
+GREEN 5 GREEN Data 5 (MSB)
+GREEN 4 GREEN Data 4
+GREEN 3 GREEN Data 3
+GREEN 2 GREEN Data 2
+GREEN 1 GREEN Data 1
+GREEN 0 GREEN Data 0 (LSB)
(EVEN/ODD)
Green-pixel Data: Each green pixel's brightness data consists of these 6 bits pixel data.
+BLUE 5 BLUE Data 5 (MSB)
+BLUE 4 BLUE Data 4
+BLUE 3 BLUE Data 3
+BLUE 2 BLUE Data 2
+BLUE 1 BLUE Data 1
+BLUE 0 BLUE Data 0 (LSB)
(EVEN/ODD)
Blue-pixel Data: Each blue pixel's brightness data consists of these 6 bits pixel data.
-DTCLK Data Clock: The typical frequency is 81MHz.
(EVEN/ODD) The signal is used to strobe the pixel +data and the +DSPTMG
+DSPTMG Display Timing:
When the signal is high, the pixel data shall be valid to be displayed.
VSYNC Vertical Sync: This signal is synchronized with -DTCLK. Both active high/low signals are
acceptable.
HSYNC Horizontal Sync: This signal is synchronized with -DTCLK. Both active high/low signals are
acceptable.
VDD Power Supply
GND Ground
VEEDID EEDID Power Supply
CLKEEDID EEDID Clock
DataEEDID EEDID Data
Note : Output signals except VEEDID ,CLKEEDID and DataEEDID from any system shall be Hi-Z state when VDD is off.
VSYNC should start with active high ( positive pulse ) signal from when VDD is supplied and its polarity
should not be changed.
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5.3.1 E-EDID
E-EDID detail in this LCD module is in the following table.
Addres Description Data (hex) Remark
s (hex)
00 - 07 Header 00 FF FF FF FF FF FF 00 Header, Fixed
08 - 09 ID Manufacturer Name 24 94 "IDT"
0A - 0B ID Product code D2 22 Product code "8914"
0C - 0F ID Serial Number 01 01 01 01 Unused
10 Week of Manufacture 00 Unused
11 Year of Manufacture 00 Unused
12 - 13 EDID Structure Version/Revision 01 02 Ver1.2
14 - 18 Basic Display Parameters/Features 80 1E 17 78 0A
19 - 22 Color Characteristics CD 75 91 55 4F 8B 26 21 50 54
23 - 25 Established Timings 00 00 00 Unused
26 - 35 Standard Timing Identification A9 40 01 01 01 01 01 01 01 01
01 01 01 01 01 01
36 - 47 Detailed Timing/Monitor Description #1 48 3F 40 30 62 B0 32 40 40 C0 VESA 1600x1200 @ 60Hz, Negative H/V-sync
13 00 31 E5 10 00 00 18 polarity
48 - 59 Detailed Timing/Monitor Description #2 00 00 00 0F 00 3B 3D 4A 4C 11 Video timing min/max parameters,EDID version=1
00 0A 20 20 20 20 20 01
5A - 6B Detailed Timing/Monitor Description #3 00 00 00 FE 00 49 44 54 45 43 Supplier Name "IDTECH"
48 0A 20 20 20 20 20 20
6C - 7D Detailed Timing/Monitor Description #4 00 00 00 FE 00 49 41 55 58 31 Monitor Name "IAUX14P"
34 50 0A 20 20 20 20 20
7E Extension Flag 00 No extension
7F Checksum 86
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5.4 Interface Signal Electrical Characteristics
5.4.1 Signal Electrical Characteristics for LVDS Receiver
The LVDS receiver equipped in this LCD module is compatible with ANSI/TIA/TIA-644 standard.
Table. Electrical Characteristics
Parameter Symbol Min Typ Max Unit Conditions
Differential Input High Threshold Vth +100 mV Vcm=+1.2V
Differential Input Low Threshold Vtl -100 mV Vcm=+1.2V
Magnitude Differential Input Voltage |Vid| 100 600 mV
Common Mode Voltage Vcm 1.0 1.2 1.4 V Vth - Vtl = 200mV
Common Mode Voltage Offset Vcm -50 +50 mV Vth - Vtl = 200mV
Note:
O Input signals shall be low or Hi-Z state when VDD is off.
O All electrical characteristics for LVDS signal are defined and shall be measured at the interface
connector of LCD (see Figure "Measurement system").
Figure. Voltage Definitions
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Figure. Measurement system
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Table. Switching Characteristics
Parameter Symbol Min Typ Max Unit Conditions
Clock Frequency fc 53.0 81.0 83.0 MHz
Cycle Time tc 12.0 12.3 18.9 ns
Data Setup Time(Note 1) Tsu 500 ps fc = 81MHz, tCCJ < 50ps,
Data Hold Time(Note 2) Thd 500 ps Vth-Vtl = 200mV,
Vcm = 1.2V, Vcm = 0
Cycle-to-cycle jitter(Note 3) tCCJ -150 +150 ps fc = 81MHz
Cycle Modulation Rate(Note 4) tCJavg 20 ps/clk fc = 81MHz
Note 1: All values are at VDD=3.3V, Ta=25 degree C.
Note 2: See figure "Timing Definition" and "Timing Definition(detail A)" for definition.
Note 3: Jitter is the magnitude of the change in input clock period.
Note 4: This specification defines maximum average cycle modulation rate in peak-to-peak transition within
any 100 clock cycles.
This specification is applied only if input clock peak jitter within any 100 clock cycles is greater than
300ps.
Figure. Timing Definition (Even)
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Figure. Timing Definition (Odd)
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Figure. Timing Definition(detail A)
Note: Tsu and Thd are internal data sampling window of receiver. Trskm is the system skew margin; i.e., the sum
of cable skew, source clock jitter, and other inter-symbol interference, shall be less than Trskm.
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5.4.2 LVDS Receiver Internal Circuit
Below figure shows the internal block diagram of the LVDS receiver.
5.4.3 Recommended Guidelines for Motherboard PCB Design and Cable Selection
Following the suggestions below will help to achieve optimal results.
O Use controlled impedance media for LVDS signals. They should have a matched differential
impedance of 100ohm.
O Match electrical lengths between traces to minimize signal skew.
O Isolate TTL signals from LVDS signals.
O For cables, twisted pair, twinax, or flex circuit with close coupled differential traces are recommended.
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5.5 Signal for Lamp Connector
Pin # Signal Name
1 Lamp High Voltage
2 Lamp Low Voltage
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6.0 Pixel format image
Following figure shows the relationship of the input signals and LCD pixel format image. Even and odd pair of
RGB data are sampled at a time.
Even Odd Even Odd
0 1 1598 1599
1st Line R G B R G B R G B R G B
1200th Line R G B R G B R G B R G B
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7.0 Parameter guide line for CFL Inverter
PARAMETER MIN DP-1 MAX UNITS CONDITION
White Luminance
- 200 - cd/m2 (Ta=25 deg.C)
CFL current(ICFL) 3.0 7.65 8.0 mArms (Ta=25 deg.C)
(Ta=25 deg.C)
CFL Frequency(FCFL) 40 60 KHz
(Note 1)
- (Ta= 0 deg.C)
CFL Ignition Voltage(Vs) 1,500 - Vrms
(Note 3)
(Ta=25 deg.C)
CFL Voltage (Reference)(VCFL) - 590 - Vrms
(Note 2)
(Ta=25 deg.C)
CFL Power consumption(PCFL) - 4.5 5.0 W
(Note 2)
Note 1: CFL discharge frequency should be carefully determined to avoid interference between inverter and TFT
LCD.
Note 2: Calculated value for reference (ICFL x VCFL = PCFL).
Note 3: CFL inverter should be able to give out a power that has a generating capacity of over 1,500 voltage.
Lamp units need 1,500 voltage minimum for ignition.
Note 4: DP-1(Design Point-1) is recommended Design Point.
*1 All of characteristics listed are measured under the condition using the Test inverter.
*2 In case of using an inverter other than listed, it is recommended to check the inverter
carefully. Sometimes, interfering noise stripes appear on the screen, and substandard
luminance or flicker at low power may happen.
*3 In designing an inverter, it is suggested to check safety circuit very carefully.
Impedance of CFL, for instance, becomes more than 1 [M ohm] when CFL is damaged.
*4 Generally, CFL has some amount of delay time after applying kick-off voltage. It is recommended
to keep on applying kick-off voltage for 1 [Sec] until discharge.
*5 Reducing CFL current increases CFL discharge voltage and generally increases CFL discharge
frequency. So all the parameters of an inverter should be carefully designed so as not to produce
too much leakage current from high-voltage output of the inverter.
*6 It should be employed the inverter which has 'Duty Dimming', if ICFL is less than 4[mA].
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The following chart is Luminance versus Lamp Power for your reference.
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8.0 Interface Timings
Basically, interface timings described here is not actual input timing of LCD module but output timing of
SN75LVDS86(Texas Instruments) or equivalent.
8.1 Timing Characteristics
Signal Item Symbol MIN. TYP. MAX. Unit
DTCLK Freqency Fdck 53.0 81.0 83.0 [MHz]
Tck 12.0 12.3 18.9 [ns]
+V-Sync Frame Rate Fv - 60.0 - [Hz]
Tv - 16.67 - [ms]
Nv 1208 1250 2046 [lines]
V-Active Level Tva 13.33 40.0 839.8 [us]
Nva 1 3 63 [lines]
V-Back Porch Nvb 6 46 125 [lines]
V-Front Porch Nvf 1 1 125 [lines]
+DSPTMG V-Line m 1200 [lines]
+H-Sync Scan Rate Fh - 75.0 - [KHz]
Th - 13.33 - [us]
Nh 1024 1080 2046 [Tck]
H-Active Level Tha 1.185 [us]
Tha 8 96 255 [Tck]
H-Back Porch Thb 8 152 511 [Tck]
H-Front Porch Thf 8 32 [Tck]
+DSPTMG Display Thd 9.877 [us]
+DATA Data Even/Odd n 1600 [dots]
Note: Both positive Hsync and positive Vsync polarity is recommended.
Disp Timing Period (Th, Nh) must be constant by each every line.
If Disp timing are not constant due to Spread Spectrum, the following expression has to be satisfied.
DeltaDT x Tvblk < 300 [Tck]
DTmax : Disp Timing Period MAX [Tck]
DTmin : Disp Timing Period MIN [Tck]
DeltaDT = DTmax - DTmin
Tvblk : V Blanking [lines]
Tck : DTCLK
When there are invalid timing, Display appears black pattern.
Synchronous Signal Defects and enter Auto Refresh for LCD Module protection Mode.
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8.2 Timing Definition
Vertical Timing
Support mode Tvblk m Tvf VSYNC Tv,Nv Tva Tvb
Vertical Active Field Front Porch Frame VSYNC VSYNC
Blanking Time Width Back Porch
1600 x 1200 at 60Hz 0.667 ms 16.000 ms 0.013 ms 16.667 ms 0.040 ms 0.613 ms
(H line rate : 13.3 us) (50 lines) (1200 lines) (1 line) (1250 lines) (3 lines) (46 lines)
DSPTMG
Tv
Tvblk m
Tvf Tva Tvb
+VSYNC
Horizontal Timing
Thblk Thd Thf Th,Nh Tha Thb
Support mode
Horizontal Active Field HSYNC H Line HSYNC HSYNC
Blanking Front Porch Time Width Back Porch
1600 x 1200
3.457 us 9.877 us 0.395 us 13.333 us 1.185 us 1.877 us
Dotclock : 162.000
(560 dots) (1600 dots) (64 dots) (2160 dots) (192 dots) (304 dots)
MHz (81.000MHz x2)
DSPTMG
Th
Thblk Thd
Thf Tha Thb
-HSYNC
+HSYNC
Tck
VIDEO(Even) 0 2 4 n-4 n-2
VIDEO(Odd) 1 3 5 n-3 n-1
DTCLK
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9.0 Power Consumption
Input power specifications are as follows;
SYMBOL PARAMETER Min Typ Max UNITS CONDITION
VDD Logic/LCD Drive 3.0 3.3 3.6 V Load Capacitance
Voltage 68uF
PDD VDD Power 3.8 W MAX Pattern
VDD=3.6V
PDD VDD Power 2.9 W All White Pattern
VDD=3.3V
IDD VDD Current 1,250 mA MAX Pattern
VDD=3.0V
IDD VDD Current 880 mA All White Pattern
VDD=3.3V
VDDrp Allowable Logic/LCD 100 mVp-p
Drive Ripple Voltage
VDDns Allowable Logic/LCD 100 mVp-p
Drive Ripple Noise
Note : Max Pattern: Sub-pixel checker
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10.0 Power ON/OFF Sequence
VDD power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals from
any system shall be Hi-Z state or low level when VDD is off.
150ms min.
90% 90%
VDD 10% 10%
10%
0V
10ms max. 0 min.
0 min.
90% 90%
Signals 10% 10%
0V
100ms min.
20ms min.
180ms min.
(Recommended).
On
Lamp
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11.0 Mechanical Characteristics
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12.0 National Test Lab Requirement
The display module is authorized to Apply the UL Recognized Mark.
Conditions of Acceptability
Conditions of Acceptability - When installed on the end-product, consideration shall be given to the
following;
1. This component has been judged on he basis of he required spacings in the Standard for Safety of
Information Technology Equipment, CAS/CSA C22.2 No. 60950-00 *UL 60950, Third Edition, which are
based on the IEC 60950, Third Edition, which would cover the component itself if submitted for Listing.
2. The unit is supplied by Limited Power Sources.
3. The terminals and connectors are suitable for factory wiring only.
4. The terminals and connectors have not been evaluated for field wiring.
5. A suitable Electrical and Fire enclosure shall be provided.
Panel back should be separated from source of fire at least 13 mm of air or solid barrier of material of
Flammability Class V-1.
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13.0 Packaging Specification
The packaging of the LCD meets 75 cm drop test.
The following is the drawing of the package.
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14.0 Label
There are labels on the rear side of the Module.
Serial Number Label
BARCODE CHARACTER AREA
11S ppppppp Z 1Z hhh SSSSSS
1 2 3 4 5 6
1 11S = FIXED 4 1Z = FIXED
Starting identifier which Location code
is common to component
level serial numbers.
2 Seven digit IBM part number 5 hhh = Header code
Assigned by the IBM laboratory (Depend on EC Level and
releasing the part Manufacturing Location)
3 Z = FIXED 6 SSSSSS = Serial Number
Automatically given
when using the
11S-Z format
Date Label
YY and WW of the Week Code stand for the Year and the Week of the Year of manufacturing of the Module
respec