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T315HW07 VD Product Specification
Rev.0 0




Model Name: T315HW07 VD
Issue Date : 2010/09/20

( )Preliminary Specifications
( )Final Specifications



Customer Signature Date AUO Date

Approved By Approval By PM Director

Yen Ting Chiu
_________________________________ ____________________________________


Note Reviewed By RD Director
Eugene CC Chen
____________________________________

Reviewed By Project Leader
Shinli Chen
____________________________________


Prepared By PM

Joanne Hsu
____________________________________




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T315HW07 VD Product Specification
Rev.0 0


Contents
No
CONTENTS

RECORD OF REVISIONS

1 GENERAL DESCRIPTION

2 ABSOLUTE MAXIMUM RATINGS

3 ELECTRICAL SPECIFICATION

3-1 ELECTRIACL CHARACTERISTICS

3-2 INTERFACE CONNECTIONS

3-3 SIGNAL TIMING SPECIFICATION

3-4 SIGNAL TIMING WAVEFORM

3-5 COLOR INPUT DATA REFERENCE

3-6 POWER SEQUENCE

3-7 BACKLIGHT SPECIFICATION

4 OPTICAL SPECIFICATION

5 MECHANICAL CHARACTERISTICS

6 RELIABILITY TEST ITEMS

7 INTERNATIONAL STANDARD

7-1 SAFETY

7-2 EMC

8 PACKING

8-1 DEFINITION OF LABEL

8-2 PACKING METHODS

8-3 PALLET AND SHIPMENT INFORMATION

9 PRECAUTION

9-1 MOUNTING PRECAUTIONS

/9-2 OPERATING PRECAUTIONS

9-3 ELECTROSTATIC DISCHARGE CONTROL

9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE

9-5 STORAGE

9-6 HANDLING PRECAUTIONS FOR PROTECT FILM




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T315HW07 VD Product Specification
Rev.0 0


Record of Revision
Version Date Page Description
0.0 2010/09/20 First release




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T315HW07 VD Product Specification
Rev.0 0


1. General Description
This specification applies to the 32.0 inch Color TFT-LCD Module T315HW07 VD. This LCD module has a TFT
active matrix type liquid crystal panel 1,920x1,080 pixels, and diagonal size of 32.0 inch. This module supports
1,920x1,080 mode. Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical
stripes. Gray scale or the brightness of the sub-pixel color is determined with a 10-bit gray scale signal for each dot.
The T315HW07 VD has been designed to apply the 10-bit 4 channel LVDS interface method. It is intended to
support displays where high brightness, wide viewing angle, high color saturation, and high color depth are very
important.




* General Information


Items Specification Unit Note
Active Screen Size 32.00 inch
Display Area 698.40(H) x 392.85(V) mm
Outline Dimension 735.4(H) x 433.0 (V) x 20.9(D) mm D: front bezel to T-con cover
Driver Element a-Si TFT active matrix
Bezel Opening TBD mm
Display Colors 10 bit(8+FRC), 1073.7M Colors
Number of Pixels 1,920x1,080 Pixel
Pixel Pitch 0.36375 (H) x 0.36375 (W) mm
Pixel Arrangement RGB vertical stripe
Display Operation Mode Normally Black
Surface Treatment Anti-Glare, 3H Haze=2%




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T315HW07 VD Product Specification
Rev.0 0


2. Absolute Maximum Ratings
The followings are maximum values which, if exceeded, may cause faulty operation or damage to the unit


Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage Vcc -0.3 14 [Volt] Note 1
Input Voltage of Signal Vin -0.3 4 [Volt] Note 1
o
Operating Temperature TOP 0 +50 [ C] Note 2
Operating Humidity HOP 10 90 [%RH] Note 2
o
Storage Temperature TST -20 +60 [ C] Note 2
Storage Humidity HST 10 90 [%RH] Note 2
o
Panel Surface Temperature PST 65 [ C] Note 3

Note 1: Duration:50 msec.
Note 2 : Maximum Wet-Bulb should be 39 and No condensation.
The relative humidity must not exceed 90% non-condensing at temperatures of 40 or less. At temperatures greater
than 40 , the wet bulb temperature must not exceed 39 .
Note 3: Surface temperature is measured at 50 Dry condition




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T315HW07 VD Product Specification
Rev.0 0


3. Electrical Specification
The T315HW07 VD requires two power inputs. One is employed to power the LCD electronics and to drive the TFT
array and liquid crystal. The second input for BLU is to power inverter.


3.1 Electrical Characteristics


3.1.1: DC Characteristics

Value
Parameter Symbol Unit Note
Min. Typ. Max
LCD
Power Supply Input Voltage VDD 10.8 12 13.2 VDC
Power Supply Input Current IDD - 0.5 0.6 A 1
Inrush Current IRUSH -- -- 6 A 2

Input Differential Voltage VID 200 400 600 mVDC 3

LVDS Differential Input High Threshold Voltage VTH +100 -- +300 mVDC 3
Interface
Differential Input Low Threshold Voltage VTL -300 -- -100 mVDC 3

Input Common Mode Voltage VICM 1.1 1.25 1.4 VDC 3
VIH
CMOS Input High Threshold Voltage 2.7 -- 3.3 VDC 4
(High)
Interface VIL
Input Low Threshold Voltage 0 -- 0.6 VDC 4
(Low)


3.1.2: AC Characteristics

Value
Parameter Symbol Unit Note
Min. Typ. Max

Input Channel Pair Skew Margin tSKEW (CP) -500 -- +500 ps 5

Receiver Clock : Spread Spectrum Fclk Fclk
Fclk_ss -- MHz 6
Modulation range -3% +3%
LVDS
Interface Receiver Clock : Spread Spectrum
Fss 30 -- 200 KHz 6
Modulation frequency
Receiver Data Input Margin
Fclk = 85 MHz tRMG -0.4 -- 0.4 ns 7
Fclk = 65 MHz -0.5 -- 0.5




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T315HW07 VD Product Specification
Rev.0 0

Note :
1. Test Condition:
(1) VDD = 12.0V
(2) Fv = Type Timing, 60Hz
(3) Fclk= Max freq.
(4) Temperature = 25
(5) Typ. Input current : White Pattern
Max. Input current: Heavy loading pattern defined by AUO
2. Measurement condition : Rising time = 400us

9''




*1'

s

3. VICM = 1.25V

LVDS -
V IC M V TH
|V ID |
V TL
LVDS +



GND




|V ID |

0V

|V ID |




4. The measure points of VIH and VIL are in LCM side after connecting the System Board and LCM.
5. Input Channel Pair Skew Margin




Note: x = 0, 1, 2, 3, 4


6. LVDS Receiver Clock SSCG (Spread spectrum clock generator) is defined as below figures



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T315HW07 VD Product Specification
Rev.0 0


)66
)FONB
)FONBVV PD[


)FON


)FONB
)FONBVV PLQ




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T315HW07 VD Product Specification
Rev.0 0

7. Receiver Data Input Margin
Rating
Parameter Symbol Unit Note
Min Type Max
Input Clock Frequency Fclk Fclk (min) -- Fclk (max) MHz T=1/Fclk
Input Data Position0 tRIP1 -|tRMG| 0 |tRMG| ns
Input Data Position1 tRIP0 T/7-|tRMG| T/7 T/7+|tRMG| ns
Input Data Position2 tRIP6 2T/7-|tRMG| 2T/7 2T/7+|tRMG| ns
Input Data Position3 tRIP5 3T/7-|tRMG| 3T/7 3T/7+|tRMG| ns
Input Data Position4 tRIP4 4T/7-|tRMG| 4T/7 4T/7+|tRMG| ns
Input Data Position5 tRIP3 5T/7-|tRMG| 5T/7 5T/7+|tRMG| ns
Input Data Position6 tRIP2 6T/7-|tRMG| 6T/7 6T/7+|tRMG| ns




W5,3
W5,3
W5,3
W5,3
W5,3
W5,3
W5,3
/9'6 5[
5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[
,QSXW 'DWD
/9'6 5[
,QSXW &ORFN 9GLII 9


)FON 7




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T315HW07 VD Product Specification
Rev.0 0

3.2 Interface Connections
LCD connector: 187059-51221 (P-TWO, LVDS connector)
187060-41221 (P-TWO, LVDS connector)
PIN Symbol Description PIN Symbol Description
1 N.C. No connection 21 CH3_3+ LVDS Channel 3, Signal 3+
2 N.C. No connection 22 CH3_4- LVDS Channel 3, Signal 4-
3 N.C. No connection 23 CH3_4+ LVDS Channel 3, Signal 4+
4 N.C. No connection 24 GND Ground
5 N.C. No connection 25 GND Ground
6 N.C. No connection 26 CH4_0- LVDS Channel 4, Signal 0-
7 N.C. No connection 27 CH4_0+ LVDS Channel 4, Signal 0+
8 N.C. No connection 28 CH4_1- LVDS Channel 4, Signal 1-
9 GND Ground 29 CH4_1+ LVDS Channel 4, Signal 1+
10 CH3_0- LVDS Channel 3, Signal 0- 30 CH4_2- LVDS Channel 4, Signal 2-
11 CH3_0+ LVDS Channel 3, Signal 0+ 31 CH4_2+ LVDS Channel 4, Signal 2+
12 CH3_1- LVDS Channel 3, Signal 1- 32 GND Ground
13 CH3_1+ LVDS Channel 3, Signal 1+ 33 CH4_CLK- LVDS Channel 4, Clock -
14 CH3_2- LVDS Channel 3, Signal 2- 34 CH4_CLK+ LVDS Channel 4, Clock +
15 CH3_2+ LVDS Channel 3, Signal 2+ 35 GND Ground
16 GND Ground 36 CH4_3- LVDS Channel 4, Signal 3-
17 CH3_CLK- LVDS Channel 3, Clock - 37 CH4_3+ LVDS Channel 4, Signal 3+
18 CH3_CLK+ LVDS Channel 3, Clock + 38 CH4_4- LVDS Channel 4, Signal 4-
19 GND Ground 39 CH4_4+ LVDS Channel 4, Signal 4+
20 CH3_3- LVDS Channel 3, Signal 3- 40 GND Ground
41 GND Ground
Note: N.C. : please leave this pin unoccupied. It can not be connected by any signal
(Low/GND/High).




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T315HW07 VD Product Specification
Rev.0 0

PIN Symbol Description PIN Symbol Description
1 N.C. No connection 26 N.C. No connection
2 N.C. No connection 27 N.C. No connection
3 N.C. No connection 28 CH2_0- LVDS Channel 2, Signal 0-
4 N.C. No connection 29 CH2_0+ LVDS Channel 2, Signal 0+
5 N.C. No connection 30 CH2_1- LVDS Channel 2, Signal 1-
Panel Rotation Display Control
6 ROTATE High(3.3V) : Rotate Enable 31 CH2_1+ LVDS Channel 2, Signal 1+
Open/Low(GND) : Rotate Disable
Open/High(3.3V) for NS,
7 LVDS_SEL 32 CH2_2- LVDS Channel 2, Signal 2-
Low(GND) for JEIDA
8 N.C. No connection 33 CH2_2+ LVDS Channel 2, Signal 2+
9 N.C. No connection 34 GND Ground
10 N.C. No connection 35 CH2_CLK- LVDS Channel 2, Clock -
11 GND Ground 36 CH2_CLK+ LVDS Channel 2, Clock +
12 CH1_0- LVDS Channel 1, Signal 0- 37 GND Ground
13 CH1_0+ LVDS Channel 1, Signal 0+ 38 CH2_3- LVDS Channel 2, Signal 3-
14 CH1_1- LVDS Channel 1, Signal 1- 39 CH2_3+ LVDS Channel 2, Signal 3+
15 CH1_1+ LVDS Channel 1, Signal 1+ 40 CH2_4- LVDS Channel 2, Signal 4-
16 CH1_2- LVDS Channel 1, Signal 2- 41 CH2_4+ LVDS Channel 2, Signal 4+
17 CH1_2+ LVDS Channel 1, Signal 2+ 42 N.C. No connection
18 GND Ground 43 N.C. No connection
19 CH1_CLK- LVDS Channel 1, Clock - 44 GND Ground
20 CH1_CLK+ LVDS Channel 1, Clock + 45 GND Ground
21 GND Ground 46 GND Ground
22 CH1_3- LVDS Channel 1, Signal 3- 47 N.C. No connection
23 CH1_3+ LVDS Channel 1, Signal 3+ 48 VDD Power Supply, +12V DC Regulated
24 CH1_4- LVDS Channel 1, Signal 4- 49 VDD Power Supply, +12V DC Regulated
25 CH1_4+ LVDS Channel 1, Signal 4+ 50 VDD Power Supply, +12V DC Regulated
51 VDD Power Supply, +12V DC Regulated
Note: N.C. : please leave this pin unoccupied. It can not be connected by any signal (Low/GND/High).




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T315HW07 VD Product Specification
Rev.0 0