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LM1893 LM2893 Carrier-Current Transceiver

April 1995

LM1893 LM2893 Carrier-Current Transceiver
General Description
Carrier-current systems use the power mains to transfer information between remote locations This bipolar carriercurrent chip performs as a power line interface for half-duplex (bi-directional) communication of serial bit streams of virtually any coding In transmission a sinusoidal carrier is FSK modulated and impressed on most any power line via a rugged on-chip driver In reception a PLL-based demodulator and impulse noise filter combine to give maximum range A complete system may consist of the LM1893 a COPSTM controller and discrete components

Output power easily boosted 10-fold 50 to 300 kHz carrier frequency choice TTL and MOS compatible digital levels Regulated voltage to power logic Drives all conventional power lines




Noise resistant FSK modulation User-selected impulse noise filtering Up to 4 8 kBaud data transmission rate Strings of 0's or 1's in data allowed Sinusoidal line drive for low RFI

Energy management systems Home convenience control Inter-office communication Appliance control Fire alarm systems Security systems Telemetry Computer terminal interface

Typical Application

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FIGURE 1 Block diagram of carrier current chip with a complement of discrete components making a complete FO e 125 kHz fDATA e 360 Baud transceiver Use caution with this circuit dangerous line voltage is present
BI-LINETM and COPSTM are trademarks of National Semiconductor Corp Carrier-Current Transceivers are also called Power Line Carrier (PLC) transceivers C1995 National Semiconductor Corporation

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RRD-B30M115 Printed in U S A

Absolute Maximum Ratings
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply voltage Voltage on pin 12 Voltage on pin 10 (Note 1) Voltage on pins 5 and 17 5 6 V DC zener current Junction temperature transmit mode receive mode Electro-Static Discharge (120 pF 1500X) 30 V 55 V 41 V 40 V 100 mA 150 C 125 C 1KV Maximum continuous dissipation TA e 25 C plastic DIP N (Note 2) transmit mode 1 66 W receive mode 1 33 W b 40 to 85 C Operating ambient temp range b 65 to 150 C Storage temperature range Lead temp soldering 7 seconds 260 C Note Absolute maximum ratings indicate limits beyond which damage to the device may occur Electrical specifications are not ensured when operating the device above guaranteed limits but below absolute maximum limits but there will be no device degradation

General Electrical Characteristics
(Note 3) The test conditions are V a e 18V and FO e 125 kHz unless otherwise noted
Parameter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 5 6 V Zener voltage VZ 5 6 V Zener resistance RZ Carrier I O peak survivable transient voltage VOT Carrier I O clamp voltage VOC Carrier I O clamp resistance R10 TX RX low input voltage VIL TX RX high input voltage VIH TX RX low input current IIL TX RX high input current IIH RX b TX switch-over time TRT TX b RX switch-over time TTR ICO initial accuracy of FO ICO temperature coefficient of FO Temperature drift of FO Pin 11 IZ e 2 mA Pin 11 RZ e (VZ 10 mA b VZ 1 mA) (10 mA b 1 mA) Pin 10 discharge 1 mF cap charged to VOT thru k 1X Pin 10 IOC e 10 mA RX mode 2N2222 diode pin 8 to 9 Pin 10 IOC e 10 mA Pin 5 Pin 5 (Note 9) Pin 5 at 0 8 V Pin 5 at 40 V 10 b 4 Time to develop 63% of full current drive thru pin 10 1 bit time TB e 1 (2FDATA) Time TTR is user controlled with CM see Apps Info TX mode RO e 6 65 kX CO e 560 pF F0 e (F1 a F2) 2 TX or RX mode (FOMAX b FOMIN) (TJMAX b TJMIN) TX or RX mode b 40 s TJ s TJMAX 10 2 125
b 100
g2 0 g5 0


Typical 56 5 80 44 20 18 22

Test Limit (Note 4) 52 59 60 41 50 08 28
b 20

Design Limit (Note 5)

Limit Units V min V max X V max V min V max X V max V min mA min mA max




mA min mA max ms bit

113 137

kHz min kHz max PPM C % max

(Note 3) The test conditions are V a e 18 V and FO e 125 kHz unless otherwise noted The transmit center frequency is FO FSK low is F1 and FSK high is F2
Parameter 15 Supply voltage V a range Conditions Meets test 17 spec at TJ e 25 C and l(F1 14V bF1 18V ) F1 18V l k0 01 l(F1 24V bF1 18V ) F1 18V l k0 01 Pin 15 Pin 12 high IQT is IQ through pin 15 and the average current IODC of the Carrier I O through pin 10 100X load on pin 10 Pin 10 Set internally be ALC 2N2222 diode pin 8 to 9 Q of 10 tank driving 10X line 100X load no tank (F2 b F1) ( F2 a F1 2) Pin 17 Pin 17 (Note 9) Pin 17 at 0 8 V Pin 17 at 40 V 10 b 4 Typical 13 40 52 Test Limit (Note 4) 14 24 79 Design Limit (Note 5) 15 23 Limit Units V min V max mA max

Transmitter Electrical Characteristics


Total supply current IQT

17 18 19 20 21 22 23 24

Carrier I O output current IO Carrier I O lower swing limit VALC THD of IO (Note 6) FSK deviation F2 b F1 Data In low input voltage VIL Data In high input voltage VIH Data In low input current IIL Data In high input current IIH

70 47 06 55 44 17 21

45 40 57 50 9 37 52 08 28
b 10

mApp min V min V max % max % max % min % max V max V min mA min mA max 0 mA min mA max




Receiver Electrical Characteristics (Note 3) The test conditions are V a e 18 V FO e 125 kHz g 2 2% deviation FSK FDATA e 2 4 kHz VIN e 100 mVpp in the receive mode unless otherwise noted
Parameter 25 26 27 28 Supply voltage V a range Supply current IQT Carrier I O input resistance R10 Max data rate FMD Conditions Functional receiver (Note 7) IQT is pin 15 (V a ) plus pin 10 (Carrier I O) current 2 4 kX Pin 13 to GND Pin 10 Functional receiver (Note 7) CF e 100 pF RF e 0X no tank 2 4 kHz e 4 8 kBaud CF e 100 pF RF e 0 X CF e 100 pF RF e 0 X For a functional receiver (Note 8) Referred to chip side (pin 10) of the line-coupling XFMR FO e 50 kHz FO e 300 kHz Referred to line side of XFMR (assuming a 7 07 1 XFMR) FO e 50 kHz FO e 300 kHz Pin 10 lower than pin 15 by VINDC Pin 12 leakage I s 20 mA Pin 12 sat voltage at IOL e 2 mA Pin 13 charge and discharge current Pin 6 Pin 6 V(pin 3) b V(pin 4) e g 250 mV Pin 6 TX mode Bias pin 6 as it selfbiased during test 31 Bias pins 3 and 4 at 8 5 V IPC e I(pin 3) a I(pin 4) TX mode Pins 3 and 4 RPD e (V 100mA b V 50mA) (50mA) Pin 3 to 4 measured after filtering out the 2FO component VPIN3 b VPIN4 e g VWINDOW a DC offset Drive for g 1 mA pin 6 current CL e 0 1 mF PSRR e CMRR 120 Hz Typical 12 37 11 19 5 10 Test Limit (Note 4) 13 30 5 14 14 30 48 24 Design Limit (Note 5) 13 5 28 Limit Units V min V max mA min mA max kX min kX max kBaud

29 30 31

PLL capture range FC PLL lock range FL Receiver input sensitivity SIN

g 40 g 45

g 15 g 15

g 10

% min % min

18 20 14 0 26 0 29 0 20 2 70 0 15
g 55



mVRMS mVRMS mVRMS mVRMS mVRMS mVRMS V max V min V max mA min mA max V min V max mA min mA max

32 33 34 35 36 37 38 39 40 41 42 43

Tolerable input dc voltage offset range VINDC Data Out breakdown voltage Data Out low output VOL Impulse noise filter current II Offset hold cap bias voltage VCM Offset hold capacitor max drive current IMCM Offset hold bias current IOHB Phase comparator current IPC Phase detector output resistance RPD Phase detector demodulated output voltage VPD Fast offset cancel voltage ``window'' -to-VPD ratio VW VPD Power supply rejection PSRR

01 55 04
g 45 g 85

g 55

13 35
g 25 g 80

b0 5

b 20

b 40

40 100 10 100 0 95 80 50 200 6 18 60 180 0 70 1 20

nA min nA max mA min mA max kX min kX max mVpp min mVpp max V V min V V max dB min

Note 1 More accurately the maximum voltage allowed on pin 10 is VOC and VOC ranges from 41 to 50V Also transients may reach above 60V see the transient peak voltage characteristic curve Note 2 The maximum power dissipation rating should be derated for device operation above 25 C to insure that the junction temperature remains below the maximum rating Use a iJA of 75 C W for the N package using a socket in still air (which is the worst case) Consult the Application Information section for more detail Note 3 The boldface values apply over the full junction temperature range for the specified supply voltage range All other numbers apply at TA e TJ e 25 C Pin numbers refer to LM1893 LM2893 tested by shorting Carrier In to Carrier Out and testing it as an LM1893 Note 4 Guaranteed and 100% production tested Note 5 Guaranteed (but not 100% production tested) over the temperature and supply voltage ranges These limits are not used to calculate outgoing quality levels Note 6 Total harmonic distortion is measured using THD e IRMS (all components at or above 2FO) IRMS (fundamental) Note 7 Receiver function is defined as the error-free passage of 1 cycle of 50% duty-cycle 2 4 kHz square-wave data (2 sequential 208 mS bits) with the first bit being a ``1 '' All of the data transitions (edges) must fall within g 10% ( g 20 8 ms) of their noise-free positions RX time delay is minimized by using no impulse noise filter cap CI for this test Note 8 During the sensitivity check note 7 requirements are followed with these exceptions (1) data rate FDATA e 1 2 kHz (2) all of the data transitions must fall bit or 208 ms (CI is within g 20% ( g 41 6 ms) of their noise-free positions and (3) a time-domain filter capacitor (CI) is used The time delay of CI is approximately 6200 pF) Note 9 For TTL compatibility use a pull-up resistor to increase min VOH to above 2 8 V


Typical Performance Characteristics (V a e 18V

FO e 125 kHz circuit of Figure 1 pin numbers for

Total Current Consumption IQT vs Supply Voltage

Total Current Consumption IQT vs Junction Temperature

Chip Bias Current iQ vs Supply Voltage

Chip Bias Current IQ vs Junction Tempurature

Output Stage DC Current IODC vs Output Voltage

Output Stage DC Current IODC vs Junction Temperature

Transient Voltage Survival vs Pulse Time

Transmitter AC Output Current vs Junction Temperature

Transmitter Sinusoid THD vs Junction Temperature

ALC Voltage vs Junction Temperature

ICO Frequency vs Junction Temperature

Transmitter FSK Deviation vs Junction Temperature

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Typical Performance Characteristics
Maximum Data Rate vs Junction Temperature


Receiver Sensitivity vs Junction Temperature

PLL Lock Range vs Junction Temperature and FO

PLL Capture Lock Range vs Junction Temperature

Receiver Sensitivity vs PLL Lock Range and FO

Receiver Sensitivity vs PLL Lock Range and Loop Filter

Impulse Noise Filter Current vs Junction Temperature

Phase Detector Output Voltage vs Junction Temperature

Offset Hold Cap Charge Currents vs Junction Temperature

Offset Hold Cap Bias Current vs Junction Temperature

Data Out Low Voltage vs Pull Down Current

Pin 7 Bias Voltage vs Junction Temperature

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Application Information
THE DATA PATH The BI-LINETM chip serves as a power line interface in the carrier-current transceiver (CCT) system of Figure 3 Figure 4 shows the interface circuit now discussed The controller may select either the transmit (TX) or receive (RX) mode Serial data from the controller is used to generate a FSKmodulated 50 to 300 kHz carrier on the line in the TX mode In the RX mode line signal passes through the coupling transformer into the PLL-based receiver The recreated serial bit stream drives the controller With the IC in the TX mode (pin 5 a logic high) baseband data to 5 kHz drive the modulator's Data In pin to generate a switched 0 978I 1 022I control current to drive the low TC triangle-wave current-controlled oscillator to g 2 2% deviation The tri-wave passes through a differential attenuator and sine shaper which deliver a current sinusoid through an automatic level control (ALC) circuit to the gain of 200 current output amplifier Drive current from the Carrier I O develops a voltage swing on T1's (Figure 4 ) resonant tank proportional to line impedance then passes through the step-down transformer and coupling capacitor CC onto the line Progressively smaller line impedances cause reduced signal swing but never clipping-thus avoiding potential radio frequency interference When large line impedances threaten to allow excessive output swing on pin 10 the ALC shunts current away from the output amplifier holding the voltage swing constant and within the amp's compliance limit The amplifier is stable with a load of any magnitude or phase angle In the RX mode (pin 5 a logic low) the TX sections on the chip are disabled Carrier signal broad-band noise transient spikes and power line component impinge of the receiver's input highpass filter made up of CC and T1 and the tank bandpass filter In-band carrier signal band-limited noise heavily attenuated line frequency component and attenuated transient energy pass through to produce voltage swing on the tank swinging about the positive supply to drive the Carrier I O receiver input The balanced Norton-input limiter amplifier removes DC offsets attenuates line frequency performs as a bandpass filter and limits the signal to drive the PLL phase detector differentially The differential demodulated output signal from the phase detector containing AC and DC data signal noise system DC offsets and a large twice-the-carrier-frequency component passes through a 3-stage RC lowpass filter to drive the offset cancel circuit differentially The offset cancelling circuit works by insuring that the (fixed) g 50 mV signal delivered to the data squaring (``slicing'') comparator is centered around the 0 mV comparator switch point Whenever the comparator signal plus DC offset and noise moves outside the carefully matched g 50 mV voltage ``window'' of the offset cancel circuit it adjusts its DC correction voltage in series with the differential signal to force the signal back into the window While the signal is within the g 50 mV window the DC offset is stored on capacitor CM By grace of the highly non-linear offset hold capacitor charging during offset cancelling the DC cancellation is done much more quickly than with an AC coupling capacitor normally used in place of the offset cancel circuit Since impulse noise spikes normally ring the signal symmetrically around 0 V the fully bilateral offset cancel topology affords excellent noise rejection The switched current output of the comparator drives the impulse noise filter integrator capacitor that rejects all data pulses of less than the integrator charge time Noise appears as duty-cycle jitter at the open collector serial data output 6

Dual-In-Line Package

Top View Order Number LM1893N See NS Package Number N18A Small Outline

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Dual-In-Line Package

Top View

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Order Number LM2893M or LM2893N See NS Package Number M20B or N20A FIGURE 2 Connection Diagrams

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FIGURE 3 The block diagram of a carrier-current system using the Bi-Line chip to interface digital controllers via the power line
Unless otherwise noted all pin references refer to LM1893 but hold true for equivalent LM2893 pin

Application Information (Continued)

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FIGURE 4 Block diagram of a CCT system with the boost and 5V supply options shown in dashed boxes

Application Information (Continued)
Recommended Value CO 560 pF RO 6 2 kX CF 0 047 mF RF 3 3 kX CC 0 22 mF Purpose Effect of making the component value Smaller Together CO and RO Increases FO set ICO FO Increases FO k 5 6 k not recommended PLL loop filter pole PLL loop filter zero Couples FO to line CC and T1 low-pass attenuates 60 Hz Tank matches line Z bandpass filters isolates from line and attenuates transients ALC pole ALC zero Limiter 50 kHz pole 60 Hz rejection Holds RX path VOS Less noise immune higher fDATA more PLL stability PLL less stable allows less CF Less ringing Low TX line amplitude Less 60 Hz T1 current Less stored charge Tank FO up or increase L of T1 for constant FO Smaller L higher FO or increase CC decreased FO line pull Noise spikes turn ALC off Less stable ALC Higher pole F more 60 Hz reject FO attenuation Larger Decreases FO Decreases FO l 7 6 k not recommended More noise immune lower fDATA less PLL stability PLL more stable allows more CF More ringing Drives lower line Z More 60 Hz T1 current More stored charge Tank FO down or decrease L of T1 for constant FO Larger L lower FO or decrease CC increased FO line pull Slower ALC response More stable ALC Lower pole F less 60 Hz reject more noise BW
g 5% NPO ceramic Use low TC 2 k pot and 5 6 k fixed R Poor FO TC with k5 6 k RO


Depending on RF value and FO PLL unstable with large CF See Apps Info CF and RF values not critical
t 250 V non-polar Use 2CC on hot and neutral for max line isolation safety

CQ 0 033 mF T1 Use recommended XFMR CA 0 1 mF RA 10 kX CL 0 047 mF CM 0 47 mF

100 V nonpolar low TC g 10% High large-signal Q needed Optimize for low FO line pull with control of FO TC and Q RA optional ALC stable for CAt100 pF Any reasonably low TC cap 300 pF guarantees stability

Less noise immune shorter More noise immune longer Low leakage g 20% cap VOS hold faster VOS aqui- VOS hold slower VOS aqui- Scale with fDATA sition shorter preamble sition longer preamble More impulse reject more CI charge time bit nom delay less pulse jitter Must be k1 bit worst-case Less available source I Smaller shunt current less V a current draw ZT costly lower series R gives enhanced transient clamp more ruggedness Excessive TX attenuation Costly Inadequate turn-off speed More rugged but costly Less IO lower min hfe Less supply spike ALC RX charging not inhibited over TJ RCt1 5 kX on 5 6 V 1kIZk30 mA recommended (Chip power-up needs 5 6 V) Recommend Zener rated for t500 W for 1 ms

CI 0 047 mF RC 10 kX RZ 12 kX ZT t44 V BV k 60 V peak

Rejects short pulses Less impulse reject less like impulse noise delay more pulse jitter Open-col pull-up 5 6 V Zener bias Transient clamp Less available sink I Larger shunt current more chip dissipation ZT failure higher series R-excess peak V Zener and chip damage less ruggedness Damage ZT pull up V a Failure on Transient Faster lower THD IO Excessive TJ and VSAT More IO need higher hfe Transients destroy chip Excess ALC current flow

RT 4 7 X DT t44V BV RB 180 X QB Power NPN RG 1 1 X CB t47 mF ZA 5 1V

Transient I limit Over-drive Clamp Base bleed Boost gain device Current setting R Supply bypass Stop ALC charge in RX mode

Carbon comp recommended IRF 11DQ05 or 1N5819 Boost optional QB F(b3 dB) of l200 MHz RB l 24 Ohm IO e 70 (10 a RG) RG mApp V a never over abs max ZA optional - 5 1V g 20% low leakage type

FIGURE 5 A quick explanation of the external component function using the circuit of Figure 4 Values given are for V a e 18 V FO e 125 kHz fDATA e 360 Baud (180 Hz) using a 115 V 60 Hz power line

Component Selection
Assuming the circuit of Figure 4 is used with something other than the nominal 125 kHz carrier frequency 180 Hz data rate 18V supply voltage etcetera the component values listed in Figure 5 will need changing This section will help direct the CCT designer in finding the required component values with emphasis placed on look-up tables and charts It is assumed that the designer has selected values for carrier center frequency FO data rate fDATA supply voltage V a power line voltage VL and power line frequency FL If one or more of those parameters is not defined one may read the data sheet and make an educated guess Maxims to keep in mind based on CCT electrical perform8 ance considerations only are 1) the higher the FO the better 2) the lower the maximum data rate the better and 3) the more time and frequency filtering the better Use Figure 5 as a quick reference to the external component function THE TRANSMITTER CO Central to chip operation is the low TC of FO emitter-coupled oscillator With proper CO the FO of the 2VBE amplitude triangle-wave oscillator output may vary from near DC to above 300 kHz While CO may have any value CO should

Component Selection (Continued)
be made above 10 pF so that parasitic capacitance is not dominant Excessive or unbalanced common-mode-toground capacitance should be avoided A low temperature coefficient (TC) of capacitance (k100 PPM C) such as a monolithic NPO ceramic multilayer type preserves low TC of FO Figure 6 finds a CO value given FO RO Resistor RO is used by the IC to generate a VBE R related current that is multiplied by 2 to produce the 200 mA ICO control current that sets FO The control current TC ``bucks'' the VBE related tri-wave amplitude across CO to effect a low TC of FO Vary RO to trim FO within limits Raising FO more than 20% above its untrimmed value by means of decreasing RO more than 20% is not recommended Low RO and so high control current risks ICO saturation and poor TC under worst-case conditions Raising RO reduces the demodulated signal amplitude from the phase detector raising RO by more than a factor of 2 (1 octave) is not recommended Since lower TC pots are relatively costly it is recommended that RO be made up of a 5 6 k fixed (k100 PPM C) resistor with a 2 kX (k250 PPM C) series pot CA and RA Components CA and RA control the dynamic characteristics of the transmitter output envelope Their values are not critical Use the values given in Figure 5 CA and RA are functions of loaded T1 tank Q RO fDATA and line impulse noise Any changes made in CA and RA should be made based on empirical measurements of a CCT on the line Roughly CA acts as an ALC pole and RA an ALC zero T1 At this point the CCT system designer may choose to use one of the recommended transformers or to design custom T1 Consult ``The Coupling Transformer'' section to help with the design of T1 if a new or boost-capable transformer is needed The recommended 125 kHz transformer functions with an IO of up to 600 mApp It is recommended that CCT systems use the recommended transformers described in Figure 7 for T1 The 3 transformers are optimized for use in the ranges of 50 100 kHz 100 200 kHz and 200 400 kHz with unloaded Q's (QU) of about 35 and loaded Q's (QL) of about 12 Three secondary taps are supplied with nominal 7 07 10 and 14 1 turns ratios (N) to drive industrial and residential power line impedances of 3 5 7 and 14X respectively All are inexpensive all have the same pin-outs for easy exchange in a PC board and all are small - on the order of 10 mm diameter at the base CQ Tank resonant frequency FQ must be correct to allow passage of transmitter signal to the line Use Figure 8 to find CQ's value Trimming FQ to equal FO is done with T1's trimming slug The inductance of T1 has a TC of a 150 PPM C which may be cancelled by using a b150 PPM C cap such as polystyrene Since circulating current in the tank is ARMS CQ should have a low series resistance (a 1 X series resistance is too much) Polypropelene caps are excellent ``orange drop'' mylars are adequate while many other mylars are inadequate A 100V rating is needed for transient protection

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FIGURE 6 Find CO's value knowing FO

FIGURE 8 Find CO's value given FO

Bottom View
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125 kHz Toko 707VX-A042YUK

50 kHz Toko 707VX-A043YUK

300 kHz Toko 161XN-A207YUK

FIGURE 7 The recommended T1 transformers available through Toko America 1250 Feehanville Drive Mount Prospect IL 60056 (312) 297-0070


Component Selection (Continued)
CC Capacitor CC's primary function is to block the power line voltage from T1's line-side winding Also CC and T1's lineside winding comprise a LC highpass filter The self-inductance of T1 is far too low to support a direct line connection CC must have a low enough impedance at FO to allow T1 to drive transmitted energy onto the line To drive a 14X power line the impedance of CC should be below 14X Use Figure 9 to find the reactive impedance of CC to check that it is less than the line impedance Then check Figure 10 to see that the power line current is small enough to keep T1 well out of saturation the recommended transformers can withstand a 10 Amp-turn magnetizing force (1 Amp through the worst-case 10 turn line-side winding) Caution is required when choosing CC to avoid series resonance of the series combination of CC the transformer inductance and the reflected tank impedance The low resistance of the network under series resonance will load the line possibly decreasing range For your particular line coupling circuit measure for series resonance using some expected line impedance load RB This base-bleed resistor turns QB off quickly - important since the amplifier output swing is about 200V ms An RB below about 24X will conduct excessive current and overload the chip amplifier and is not recommended neous power of greater than 1 kW has been measured using the recommended transformers) For self protection the Carrier I O has an internal 44V voltage clamp with a 20X series resistance A parallel low impedance 44V external transient suppression diode will then conduct the lion's share of any current when transients force the Carrier I O to a high voltage

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FIGURE 10 The AC line-induced current passed by CC

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FIGURE 11 Output amplifier current and required min QB hfe versus gain-setting resistor RG

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FIGURE 9 CC's impedance should be as a rule-of-thumb smaller than the lowest expected line impedance RG This resistor in parallel with the internal 10X resistor fixes the current gain of the output amplifier and so the output current amplitude Figure 11 gives output current and minimum AC current gain hfe for QB when RG is used to boost output current QB The boost gain transistor QB must be fast Double-diffused devices with 50 MHz FT's work slower transistors (epi-base types) do not preserve a sinusoidal waveform when FO is high or will cause the output amp to oscillate QB must have a certain minimum hfe for given boost levels as shown in Figure 11 Figure 12 shows the power QB must dissipate continuously operating with a shorted output BVCER (R e RB) must be 60V or greater and QB must have adequate SOA for transient survival ZT Unfortunately potentially damaging transient energy passes through transformer T1 onto the Carrier I O pin (instanta10
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FIGURE 12 Boost transistor power dissipation versus amplifier output current ZT must be used unless some precaution is taken to protect the Carrier I O pin from line transients or transients caused when stored line energy in CC is discharged by the random phase of power line connection and disconnection Worst case CC may discharge a full peak-to-peak line voltage into the tuned circuit Another way to reduce the need for ZT is by placing another magnetic circuit in the signal path that relies on a high but easily saturated permeability to couple a primary and secondary winding - a toroidal transformer for example Toroids cost more than ZT Use an avalanche diode designed specifically for transient suppression they have orders of magnitude higher pulse

Component Selection (Continued)
power capability than standard avalanche diodes rated for equal DC dissipation Metal oxide varistors have not proven useful because of their inferior clamping coefficient and are not recommended Specifications for an example minimum diode are given in Figure 13 Breakdown Voltage 4449V 1 mA Maximum Leakage 1mA 40V Capacitance 300 pF BV Maximum Clamp Voltage 64 5V 7 8A Peak Non-Repetitive Pulse Power 10 kW for 1 ms (REA Standard Exponential Pulse) Surge Current 70A for 1 120s FIGURE 13 Key specifications for a recommended transient suppressor ZT available from General Semiconductor 2001 West Tenth Place Tempe AZ 85281 602968-3101 part no SA40A RT RT acts as a voltage divider with ZT absorbing transient energy that attempts to pull the Carrier Input pin above 44V Make the resistor a carbon composition 1 4W When experiments discharging CC charged to the peak-to-peak 620V AC thru a 1X power line were carried out film resistors blew open-circuit DT This Schottky diode is placed in parallel with the CCT chip's substrate diode to pass the majority of the current drawn from ground when the Carrier Input or Carrier Output is pulled below ground by a larger-than-twice-the supply-swing on the tank Note that ZT is in parallel with the substrate diode but is ineffective due to its high forward voltage drop and high diffusion capacitance caused by its low forward speed Tests proved that a 1N5818 kept a receive-path functional with a 20X boost transmitter with a 7 1 transformer attempted to swing the receiver's Carrier I O to g 100V (300 mA peak ground current in the receiver) Without DT the receiver momentarily stops functioning at a 100 times lower ground current This diode is not needed if the Carrier I O never swings below ground If your CCT systems all run on the same regulated voltage with all matched transformers and turns ratios it is not needed Otherwise it is THE RECEIVER The receiver and transmitter share components CC T1 CQ RT ZT CO RO and peripheral supply and bias components that are not in need of change for RX mode operation Values for the balance of the components are now found Line-Frequency Rejection To use the ultimate sensitivity of the device fully 110 dB of 115 V 60 Hz attenuation is required between the line and the limiter amplifier output Using the circuit topology of Figure 4 the combined attenuation of the CC T1 highpass the tuned transformer and the bandpass filter attenuation of the limiter amplifier give far more line rejection than the above-stated minimum However if some other CCT line coupling circuit is used line rejection will become important to the system designer Receiver input power supply rejection (PSRR) and commonmode rejection (CMRR) are one-in-the-same using the supply-referenced signal input of Figure 4 Ripple swings both
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differential inputs of the Norton amp equally while the single-ended input signal swings only the positive input Overall PSRR consists of the input CMRR (set by the input stage component matching) and the ripple-frequency attenuation of the input amplifier bandpass response that passes carrier frequency but stops low frequencies A typical 1% resistor and 1 mV n-p-n mirror offsets give 26 dB of attenuation the bandpass gives 54 dB 120 Hz attenuation for an overall 80 dB PSRR to allow tens of volts of ripple before impacting ultimate sensitivity CC A value was chosen earlier Knowing T1's secondary inductance allows a check of LC line attenuation using Figure 14 CL The Norton input limiter amplifier has a bandpass filter for enhanced receiver selectivity noise immunity and line frequency rejection The nominal response curve for FO e 50 kHz is shown in Figure 15 The 300 kHz pole is fixed The 50 kHz pole is set by CL's value After CL is found the resulting line frequency attenuation is found for the bandpass filter Use Figure 15 to find a CL value given for FO The approximate line frequency attenuation of the bandpass filter may then be found in Figure 16 Figure 15 returns a value for CL 33% larger than nominal giving a low frequency pole 33% low to allow for component tolerances

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FIGURE 14 The 60 Hz line rejection of the highpass filter made up of CC and T1's line-side winding (neglecting capacitive coupling)

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FIGURE 15 Given FO CL is found Also shown is the input amplifier's small signal amplitude response 11

Component Selection (Continued)
CF and RF These phase-locked loop (PLL) loop filter components remove some of the noise and most of the 2FO components present in the demodulated differential output voltage signal from the phase detector They affect the PLL capture range loop bandwidth damping and capture time Because the PLL has an inherent loop pole due to the integrator action of the ICO (via CO) the loop pole set by CF and the zero set by RF gives the loop filter a classical 2nd-order response obvious way out is to then reduce the unfiltered loop bandwidth That bandwidth is approximately proportional to the value of CO For a fixed FO unfiltered loop bandwidth reduction requires a larger CO and larger control current With this chip changing the control current is not allowed So one is forced to choose a CF RF combination with some minimum capture range say g 20% that is within some guardband from the point of loop instability Happily impulse noise tends to last only fractions of a millisecond so that the lack of low bandwidth loop response with low data rates is not a heavy penalty As long as there is adequate capture range the impulse noise filter performs admirably Note that reducing FO will reduce the no-filter loop bandwidth and indeed the maximum data rate falls below the limit set by the RC lowpass filter as FO falls below 100 kHz (Figure 19 ) The tuned transformer characteristics will affect the demodulated data waveform more than CF and RF at low data rates Tank Q and off-tuning will affect overshoot during the FSK frequency steps This is a property of tuned circuits The maximum data rate of Figure 19 is measured from the receiver input to the Data Out and does not include the data bandwidth reducing effects of TI CM Capacitor CM stores a voltage corresponding to a correction factor required to cancel the phase detector differential output DC offsets The stored voltage is of the DC offset plus some bias level of about 2 2 V A large CM value increases the time required to bias-up the receive path at the beginning of transmission A large CM does filter well and store its bias voltage long Because of the initial random charge of CM the receiver must be given a data transition to charge to the proper bias voltage Therefore reducing CM's value to one that may be charged in less than 2 bit-times will not save biasing time and is not recommended

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FIGURE 16 The Norton-input limiter amplifier bandpass filter line-frequency signal attenuation given CL

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FIGURE 17 Find CF given FO Figure 19 gives the maximum data rate No CF and RF give the most stable PLL with the fastest response Large CF's with a too-small RF cause PLL loop instability leading to poor capture range and poor step response or oscillation Calculation of CF and RF is quite difficult involving not only the 2nd-order loop step response but also the PLL nondominant poles the tuned transformer stepped-frequency response and the RC lowpass step response (for data rates approaching 1 kHz) CF and RF values are best found empirically Tolerance is not critical Component values are selected to give the best possible impulse noise rejection while preserving a g 20% capture range and wide stability margin Figures 17 and 18 give CF and RF values versus FO where ``fDATA kk MAX DATA RATE'' means that fDATA should be less than the maximum data rate in kHz from Figure 19 divided by 10 Note that CF and RF are a function of data rate only for high data rates and are not plotted against data rate - as one might expect The reason for this is important to understand if the CCT system designer wishes to find CF and RF empirically Data signal is loosely speaking passed through the PLL loop and is therefore potentially attenuated if the loop bandwidth is on the order of the 3rd harmonic of the data rate or less Overall loop bandwidth is held as low as possible for maximum noise rejection while passing the data Loop bandwidth is roughly proportional to the geometric mean of the unfiltered loop bandwidth and the filter pole set by CF Therefore CF is related to data rate Unfortunately the loop capture range falls to critically low values when large enough values of CF are used to reduce loop bandwidth down to the 100's of Hz range for low data rates The 12

TL H 6750 20

FIGURE 18 Find RF given FO with FDATA a parameter

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FIGURE 19 The maximum data rate versus FO using loop filter components optimized for max noise performance while retaining a min g 20% capture range (large signal) Use Figure 20 to find CM's value knowing fDATA assuming the standard 2 bit receive charge time is desired The cap value and TC are not critical but the capacitor should have low leakage

Component Selection (Continued)
ZA The 5 1V silicon zener diode ZA is required when a short RX-to-TX switch-over time is needed at the same time that the chip is operating in the RX mode with a pin 10 input signal swing approaching or exceeding twice the supply voltage Predominant causes of these large swings impinging on the RX input are 1) a transmitter's supply voltage higher than the receiver's supply voltage 2) a TX and RX pair that are electrically close or 3) a higher RX T1 step-up turns ratio than the TX T1 step-down ratio Normally when in the RX mode with small incoming signal on pin 10 the ALC remains off with pin 7 at a 6V (VZb2VBE) bias voltage CA is then charged to 6V TX mode may then be selected with 6V on CA allowing 100% TX power to pump T1's tuned circuit and so the AC line quickly for fast RX-to-TX switch time As TX output swing increases so that pin 10 swings below VALC (4 7V typically) that ALC activates to charge CA to about 6 6V to reduce TX output drive However if in the RX mode pin 10 ever swings below VALC CA will charge to above 6 6V Now when the TX mode is selected with CA at 6 6V somewhere from 0 to 100% TX output drive is available to pump T1's tuned circuit resulting in a slower rising line signal - effectively reducing the RX-to-TX switch time Use a 5 1V ZA driven by a 0 to 0 8V logic low signal to guarantee over-temp operation RA must be in series with ZA to limit current flow and should never fall below 1 kX If RA is less than 1 kX then put a 2 kX resistor in series with ZA Logic high voltages above 10V will cause current flow into pin 7 that must be limited to 1 mA (with RA or a series R)

TL H 6750 22

FIGURE 20 Size CM assuming a 2 bit-time receive bias time CI The impulse noise filter integrator capacitor CI is used to disallow the passage of any pulse shorter than the integrator charge time That charge time set to a nominal bit time is the time required for a g 50 mA charge current to swing CI over a 2 VBE range Charge time under worst case conditions must never be greater than a bit time since no signal could then pass Using a g 10% capacitor full junction temperature range and full specified current range a maximum nominal charge time of bit is recommended Figure 21 gives CI versus data rate under those conditions RC The collector pull-up resistor is sized to supply adequate pull-up current drive and speed while preserving adequate output low current drive

Breadboarding Tips
During CCT system evaluation some techniques listed below will simplify certain measurements Use caution when working on this circuit - dangerous line voltages may be present When evaluating PLL operation offset cancel circuit operation and loop filter values use the filter of Figure 22 to view the demodulated signal minus the 2FO and noise components This filter models the RC lowpass filter on chip

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FIGURE 21 Impulse noise filter cap CI versus FDATA where the charge time is bit time

TL H 6750 25

FIGURE 22 Circuit to view the differential demodulated data signal minus the noise and 2FO components conveniently with a single-ended gain-of-one output


Breadboarding Tips (Continued)
When evaluating CCT system noise performance on a real power line it is desirable to vary the signal amplitude to the receiver This is not easy An in-line lineproof L-pad is fine except that the line impedance is unknown and variable and so the L-pad will rarely match Instead the power output of a chip transmitter may be controlled using the circuit of Figure 23 This circuit controls the ALC It is sometimes desirable to place impulse noise on the line A simple light dimmer with a 100 W light bulb load produces representative impulse noise Do not allow peak currents of over 1 A through the 5 6 V Zener In other words don't short charged capacitors into this low-impedance device Take care not to momentarily short pins 10 and 11 - chip damage may result representing an average line impedance may be connected to the line side of T1 The circuit of Figure 23 should then be used to defeat the leveling effect of the ALC

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FIGURE 23 A means of transmitter output amplitude control is shown

Figure 24 shows some typical signals beginning with serial data transmitted to received signal

Thermal Considerations
It is desirable to place the largest possible signal on the power line for maximum range limited only by the chip power dissipation and maximum junction temperature TJ The falling output power at elevated TJ allows a more optimal power output - high power at low TJ and lower power at high TJ for chip self-protection However it is still possible to exceed the maximum TJ within the specified ambient temperature limit (TA e 85 C) under worst case conditions of 100% TX duty cyle high supply shorted load poor PC board layout (with small copper foil area) and an above nominal current part Under those conditions a part may dissipate 2140 mW reaching a TJ e 170 C worst-case (admittedly a rare occurrence) Proper system design includes the measurement or calculation of TJ max to guarantee function under worst-case operation Like all devices with failure modes modeled by the Arrhenius model the high chip reliability is further enhanced by keeping the die temperature mercifully below the absolute maximum rating A direct method of measuring operating junction temperature is to measure the VBE voltage on pin 18 which is always available under all operating modes The graph of Figure 25 may be used to find TJ knowing VBE at the operating point in question and VBE at TA e TJ e 25 C VBE is found by powering up a chip (in RX mode) that has been dissipating zero power at some TA for some time and measuring VBE in less than 1 s (for better than 5 C accuracy) Alternately TJ may be calculated using (1) TJ e TA a iJAPD where iJA is 75 C W for the plastic (N) package using a socket That iJA value is for a high confidence level nomi-

Tuning Procedure
This procedure applies to circuits similar to Figure 4 LM1893 or LM2893 circuit First trim FO by putting the chip in the TX mode setting a logical high data input and measuring the TX high frequency 1 022 FO on the Carrier I O using these steps 1 Take pin 17 to a logic low 2 Take pin 5 to a logic high 3 Place a counter on pin 10 4 Adjust RO on pin 18 for F e 1 022FO Second the line transformer is tuned The chip is placed in the TX mode a resistive line load is connected to disable the ALC by reducing tank voltage swing below its limit FSK data is then passed through the tank so that the tank envelope may be adjusted for equal amplitude for high and low data frequency 1 Take pin 5 to a logic high 2 Place a logic-level square wave at or below the receiver's maximum data rate on pin 17 3 Temporarily place a 330 X resistor across the tank 4 Place a scope on pin 10 5 Adjust the transformer slug for the least envelope modulation In lieu of the 330 X resistive load T1 may be coupled to the power line to better simulate actual load and tank pull conditions during tank tuning Alternatively a passive network

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FIGURE 24 Oscillogram revealing signals at several important nodes under weak signal (0 5 mVRMS) conditions with SCR spikes on an otherwise quiet 115 V 60 Hz power line The signals are 1) transmitted data 2) RX carrier on the tuned transformer 3) demodulated signal from the PLL after passing thru circuit of Figure 22 4) signal after RC lowpass 5) data at impulse noise filter integrator and 6) received data Horizontal scale is 10 ms per div


Thermal Considerations (Continued) nal iJA for an N package is 60 C W lower with good PC board layout Since PD is a relatively strong function of TJ an iterative solution process starting with an initial guess for TJ is used With the estimated TJ find the total supply current found in the typical performance characteristics

TL H 6750 27

FIGURE 25 TJ may be found by using the temperature coefficient of pin 18 VBE if VBE is known at 25 C

Transmit-To-Receive Switch-Over Time
An important figure-of-merit for a half-duplex CCT link affecting effective data rate is the TX-to-RX switch time TTR Using the recommended component values gives this part a nominal 2 bit-time (1 bit time e 1 2fDATA ) over a wide range of operating conditions where the receiver requires 1 data transition TTR cannot be decreased significantly but does increase as noise filtering especially via CM is increased Impulse noise at switch signals near the limiting sensitivity poor FO match between receiver and transmitter because of poor trim or worst-case conditions and the statistical nature of PLL signal acquisition may all contribute to increase TTR to possibly 4 bit-times TTR is lower when a pair of LM1893's handshake rapidly The receiver was designed to ``remember'' the RX-mode DC operating points on CM and CF while in the TX mode Under noisy worst case conditions CM will discharge to the point of false operation after 35 bit-times in the TX mode (1400 bit times with no noise and a nominal part fDATA e 180 Hz) TTR is about 0 8 ms (proportional to the selected FO) plus bit-time The major components of TTR are described below for a nominal 125 kHz FO 180 Hz fDATA lightly-loaded tank with a Q of 20 and the circuit of Figure 4 The remote CCT has been operating in the TX mode with a 26 6 VPP tank swing and is now selected as a receiver An incoming signal requiring the ultimate receiver sensitivity immediately is placed on the line First the tank stored energy at the transmit frequency must decay to a level below the 2 8 mVPP swing caused by the 0 14 mVRMS incoming line signal containing the information to be received decay time e

mended CF and RF (47 nF and 6 2 kX) with a g 4 4% DFO (a g 100 mV DC offset on CF and RF) lock was measured to take less than 50 cycles of FO That is a 0 40 ms delay (proportional to 1 FO) Acquisition is incomplete until the second order PLL loop settles For the above-mentioned CF and RF the loop natural frequency FN and damping factor are found to be 2 3 kHz and 1 0 respectively Settling to within g 25 mV of the g 100 mV DC offset change requires 2 7 periods of FN or 1 2 ms (a function of CF and RF) Third the RC lowpass filter introduces a 0 12 ms delay Fourth CM must charge up to g ( )100 e 83 mV depending on the polarity of FO Borderline data squaring with zero noise immunity is possible with only g ( ) 50 mV of charging CM charge current is an asymptotic function approximated by assuming a 50 mA charge current and the full 83 mV charge voltage CM charge time is then 1 7 ms (proportional to 1 fDATA) Fifth the impulse noise filter adds a bit-time delay Total TTR is 3 9 ms plus bit-time for a total of 1 9 bit-times at 360 Baud

Receive-To-Transmit Switch-Over Time
Assume the chip has been in the RX mode and the TX mode is now selected In less than 10 ms full output current is exponentially building tank swing 50% of full swing is achieved in less than 10 cycles - or under 80 ms at 125 kHz In the same 10 ms that the output amp went on the phase detector and loop filter are disconnected and the modulator input is enabled FSK modulation is produced in 10 ms after switching to TX mode

Power Line Impedance
Irrespective of how wide the limits on power line impedance ZL are placed there are no guarantees However since the CCT design requires an estimate of the lowest expected line impedance ZLN encountered for the most efficient transmitter-to-line coupling line impedance should be measured and ZL limits fixed to a given confidence level Reasonable values for T1 turns ratio loaded Q and tank resonant frequency pull FQ may be found to enable a CCT system design that functions with the overwhelming majority of power lines A limited sampling of ZL was made during the LM1893 design of residential and commercial 115V 60 Hz power line Data was also drawn from the research of Nicholson and Malack (reference 1) among others to produce Figures 26 and 27 All measured impedances are contained within the shaded portions of Figure 27 A nominal 3 5 7 0 and 14 X ZLN is used throughout the application information with a nominal 45 phase angle (0 is sometimes used for simplicity)


V J 20 26 6 ln 125 000 0 0028 J






e 0 466 ms


That is 0 47 ms of delay (proportional to I FO and Q) Second the PLL must acquire the signal it must lock and settle Acquisition time is statistical and may take any length of time but average acquisition time depends on the loop filter components CF and RF and the difference in center frequencies DFO of the TX RX pair Using the recom15

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FIGURE 26 Measured line impedance range for residential and commercial 115V 60 Hz lines

Power Line Impedance (Continued)

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FIGURE 27 Complex-plane plots of measured 115V 60 Hz line impedance where ZL e RL a jXL

Power Line Attenuation
The wiring in most US buildings is a flat 3 conductor cable called Amerflex BX or Romex All referenced line impedances refer to hot-to-neutral impedances with a grounded center conductor The cable has a 100 X characteristic impedance a 125 kHz quarter-wavelength of 600 m (250 m at 300 kHz) and a measured 7 dB attenuation for a 50 m run with a 10 X termination Generally line loads may be treated as lumped impedances Instrument line cords exhibit about 0 7 mH and 30 pF per meter Limited tests of CCT link range using this chip show extensive coverage while remaining on one phase of a distribution transformer (100's of m) with link failure often occuring across transformer phases or through transformers unless coupling networks are utilized Total line attenuation allowed from full signal to limiting sensitivity is more than 70 dB Typically signal is coupled across transformer phases by parasitic winding capacitance typically giving 40 dB attenuation between phased 115 V windings Coupling capacitors may be installed for improved link operation across phases Power factor correcting capacitor banks on industrial lines or filter capacitors across the power lines of some electronic gear short carrier signal and should be isolated with inductors Increasing range is sometimes accomplished by electing to install the isolating inductors (Figure 28 ) and coupling capacitors as well as by electing to use the boost option Frequency translating or time division multiplexed repeaters will also increase range T1 with a stable resonant frequency FQ that is little affected by the de-tuning effect of the line impedance ZL and of 2) building a tightly line-coupled transformer for transmitted carrier with loose coupling for transients are somewhat mutually exclusive The tradeoffs are exposed in the following example for the CCT designer attempting a new boost-capable or different core transformer design The compromises are eased by separating the TX output and RX input in the LM2893 An untuned TX coupling transformer with only core coupling (not air-coupled solenoid windings) would employ a high permeability high magnetic field low loss square saturating toroidal core The resonant RX path would be isolated from line-pull problems by a unilateral amplifier that operates at line voltages with much more than 110 dB of dynamic range or by a capacitively coupled pulse transformer driving a unilateral amplifier and filter for increased selectivity See the LM2893-specific applications section For a LM1893-style transformer application first choose the turns ratio N based on an estimated lowest ZL likely encountered ZLN Figure 29 shows graphically how N affects line signal N should be as large as possible to drive ZLN with full signal If T1 has an unloaded Q QU of well less than 35 a guess of N somewhat high should be used and later checked for accuracy The recommended transformers have secondary taps giving a choice of N e 7 07 10 and 14 1 (nominally) for driving ZLN's of 14 7 0 and 3 5 X respectively (at TJ e 25 C V a e 18V and QU e 35) The resonating inductance of the tuned primary L1 is sought Note that while standard transformer design gives a transformer self-inductance with an impedance at operating frequency well above load impedance the tuned transformer requires a low L1 for adequate QU and minimum line pull Result relatively poor mutual coupling R (3) 2qFOQ It is known that resonant frequency FQ e FO and some minimum bandwidth or maximum Q will be required to pass signal under full load conditions L1 e L1 e RQ ll lZLNl (4) 2q FOQL lZLNl is the reflected ZLN QL is the loaded Q and parallel resistance RQ models all transformer losses and sets QO RQ ll lZLNl is found knowing that it absorbs full rated power

TL H 675040

FIGURE 28 An isolation network to prevent 1) noise from some device from polluting the AC line and 2) to stop some low impedance device (measured at Fo) from shorting carrier signal Component values given as an example for Fo e 125 kHz on residential power lines

The Coupling Transformer
The design arrived at for T1 is the result of an unhappy compromise - but a workable one The goals of 1) building


The Coupling Transformer (Continued)
Line pull DFQ was calculated (reference 3) for a ZL magnitude of 14X and up with any phase angle from b90 to 90 DFQ was 6 4% - well above the 3 3% estimate Referring to (11) an 11 8% bandwidth is required forcing L1 to be reduced to reduce Q That fix was not implemented some signal attenuation under worst-case drift and DFQ is allowed L1 is already so small that the 31 gauge winding conducts a ARMS circulating current

Line Carrier Detection
TL H 6750 32

FIGURE 29 Impressed line voltage for a given ZL for each of the 3 taps available on the recommended transformers PO e IOVO e IOPP 2(bVALC a V a ) (b4 7 a V a )IO e (5) 2 02 2 02 4 where IO is in amps peak-to-peak at an elevated TJ (18 b 4 7) 0 06 e 0 200 W PO e (6) 4 VO2 (bVALC a V a )02 e e 442 X (7) RQ ll lZLNl e PO IO RQ is found using ZLN and the value for N found when assuming QU e 35 (8) lZLNl e N2 ZLN e (7 07)2 13 9 e 695 X 1 1 e e 1210 X (9) RQ e 1 1 1 1 b b RQ ll lZLNl lZLNl 442 695 RQ 1210 e e1X RQS e (10) 1 a QU2 1 a 352 Only QL remains to be found to calculate L1 QL is related to the b3 dB (half-power) bandwidth by 1 (11) QL e BW (% of FO) An iterative solution is forced where line pull DFQ must be guessed to find QL and L1 L1 is then used to check the line pull guess a large error requires a new guess Try a BW of 8 7% - that is 4 4% for deviation 1% for TC of FO and 3 3% for DFQ - giving QL e 11 5 442 e 49 0 mH (12) L1 e 2q c 125 000 c 11 5 Knowing the core inductance per turn L and L1 the number of turns is found T1 e


While the addition of a carrier detection circuit (for a mute or squelch function) will only decrease receiver ultimate sensitivity there is sometimes good reason to employ it to free the controller from watching for RX signal when no carrier is incoming or to employ it to reduce the probability of line collisions (when multiple transmitters operate simultaneously to cause one or more transmissions to fail) Unless the detector is heavily filtered or uses a high carrier amplitude threshold there will be false outputs that force the controller to have Data Out data checking capability just as is required when using no carrier detector If false triggering is minimized the probability of line collisions is increased due to the inability to sense low carrier amplitudes and because of sense delay The property of the LM1893 to change output state infrequently (although the polarity is undefined) when in the RX mode with no incoming carrier reduces the desire to implement carrier detection and preserves the full ultimate sensitivity Also many impulse-noise insensitive transmission schemes like handshaking are easily modified to recover from line collisions Regarding this it should be stated that for very complicated industrial systems with long signal runs and high line noise levels it is probably wise to use a protocol which is inherently collision free so that no carrier detect hardware or software is needed A token passing protocol is an example of such a system

Figure 30 shows a low cost carrier amplitude detection circuit

Audio Transmission
The LM1893 is designed to allow analog data transmission and reception Base-band audio-bandwidth signals FM modulate the carrier passing through the tuned transformer (placing a limit on the usable percent modulation) onto the power line to be linearly demodulated by the receiver PLL Because the receiver data path beyond the phase detector will pass only digital signal external audio filtering and amplification is required Figure 31 shows a simple audio transmitter and receiver circuit utilizing a carrier detection mute circuit A single LM339 quad comparator may be used to build the carrier detect and mute Filter bandwidth is held to a minimum to minimize noise especially line-related correlated noise

T is normally an integer but these transformers require so few turns that half-turns are specified remembering that the remaining turn is completed on the P C board and is loosely coupled The secondary turns are calculated T1 49 5 e e 7 00 e 7 turns T2 e (15) N 7 07 giving an L2 of 0 98 mH Note that the recommended 125 kHz transformer mirrors these specifications The resonating capacitor is CQ e 1 e 33 1 c 10 b 9 e 33 nF (2qFQ)2 L1 (16)

0 L 020 nH T

49 0 mH

e 49



Communication and System Protocols
The development of communication and system protocols has historically been the single most time consuming element in design of carrier current systems The protocols are defined as the following 1 Communication protocol a software method of encoding and decoding data that remains constant for every transmis-


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FIGURE 30 A simple carrier amplitude detector with output low when carrier is detected

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FIGURE 31 A simple linear analog audio transmitter and receiver are shown The carrier and 1 6V inputs are derived from the carrier detector of Figure 30 The remaining 2 LM339 comparators may be used to build the carrier detector circuit

Communication and System Protocols (Continued)
sion in a system Its first purpose is to put data in a baseband digital form that is more easily recognized as a real message at the receive end Secondly it incorporates encoding techniques to ensure that noise induced errors do not easily occur and when they do they can always be detected Lastly the software algorithms that are used on the receive end to decode incoming data prevent the reception of noise induced ``phantom'' messages and insure the recovery of real messages from an incoming bit stream that has been altered by noise 2 System protocol the manner in which messages are coordinated between nodes in a system Its first purpose is to ensure message retransmission to correct errors (handshake) Secondly it coordinates messages for maximum utilization and efficiency on the network Lastly it ensures that messages do not collide on the network Common system protocols include master-slave carrier detect multiple access and token passing Token passing and master slave have been found to be the most useful since they are inherently collision free Both protocols usually reside as software in a single microcontroller that is connected to the LM1893 2893 I O In any case some sort of intelligence is needed to process incoming and outgoing messages UARTs have no usefulness in


Communication and System Protocols (Continued)
carrier current applications since they do not have the intelligence needed to distinguish between real messages and noise induced phantoms The difficulty in designing special protocols arises out of the special nature of the AC line an environment laden with the worst imaginable noise conditions The relatively low data rates possible over the AC line (typically less than 9600 baud) make it even more imperative that systems utilize the most sophisticated means available to ensure network efficiency With these facts in mind the designer is referred to a publication intended to aid in the development of carrier current systems This is literature 570075 The Bi-Line Carrier Current Networking System a 200 pp book that functions as the ``bible'' of Bi-Line system design It has sections on LM1893 circuit optimization protocol design evaluation kit usage critical component selection and the Datachecker DTS case study

transmission using a random number of bits delay or a delay based on each transmitter's address since each transceiver has a unique address An example of a simple transmission data packet is shown in Figure 32 The 8 bit 50% duty-cycle preamble is long enough to allow receiver biasing with enough bits left over to allow the receiver controller to detect the square-wave that signals the start of a transmission If there had been no transmission for some time the receiver would simply need to note that a data transition had occurred and begin its watch for a square-wave If the receive controller detected the alternating-polarity data square-wave it would then use the sync bit to signal that the address and data were immediately following The address data would then be loaded assuming the fixed format and tested against its own If the address was correct the receiver would then load and store the data If the address was not correct either the transmission was not meant for this receiver or noise has fooled the receiver In the former case when the transmission was not meant for the receiver the controller should immediately return to watching the incoming data for its address If the later case were true then the receive controller would continue to detect edges tieing itself up by loading false data and being forced to handshake The square-wave detection and address load and check routines should be fast to minimize the time spent in loops after being false-triggered by noise If the controller detects an error (a received data bit that does not conform to the pre-defined encoding format) it should immediately resume watching the LM1893's Data Out for transmissions the next bit would be shifted in and the process repeated A line-synchronous CCT system passing 3 bits per half-cycle may replace the long 8 bit preamble and sync pulse with a 2 bit start-of-transmission bias preamble The receive controller might then assume that preamble always starts after bit 1 (the first bit after zero-crossing) so that any data transition at a zero crossing must be the start of the address bits and is tested as such The line synchronous receiver operates with a simpler controller than an asynchronous system Discussion has assumed that the controller has always known when the Data Out is high or low The controller must sample at the proper time to check the Data Out state Since noise shows itself as pulse width jitter symmetrically placed about the no-noise switch-points optimum Data Out sampling is done in the center of the received data pulse The receive data path has a time delay that at low data rates is dominated by the impulse noise filter integrator and is nominally bit At a 2 kHz data rate an additional delay of approximately bit is added because of the cumulative delay of the remainder of the receiver Figure 33 shows that Data Out sampling occurs conveniently at the transmitted

Basic Data Encoding (please refer to the previously mentioned publications for advanced techniques) At the beginning of a received transmission the first 0 to 2 bits may be lost while the chip's receiver settles to the DC bias point required for the given transmitter receiver pair carrier frequency offset With proper data encoding dropped start bits can be tolerated and correct communication can take place One simple data encoding scheme is now discussed Generally a CCT system consists of many transceivers that normally listen to the line at all times (or during predetermined time windows) waiting for a transmission that directs one or more of the receivers to operate If any receiver finds its address in the transmitted data packet further action such as handshaking with the transmitter is initiated The receiver might tell the transmitter via retransmission that it received this data waiting for acknowledgement before acting on the received command Error detecting and correcting codes may be employed throughout The transmitter must have the capability to retransmit after a time if no response from the receiver is heard - under the assumption that the receiver didn't detect its address because of noise or that the response was missed because of noise or a line collision (A line collision happens when more than 1 transmitter operates at one time - causing one or more of the communications to fail) After many re-transmissions the transmitter might choose to give up Collision recovery is achieved by waiting some variable amount of time before re-

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FIGURE 32 A simple encoded data packet generated by the transmit controller is shown The horizontal axis is time where 1 bit time is 1 (2fDATA)


Basic Data Encoding (Continued)

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FIGURE 33 Operating waveforms of a linesynchronized transceiver pair are shown The diagram shows how the transmitted data transitions may be used as received data sampling points data edges for the line synchronous data transmission scheme mentioned in the previous paragraph With the asynchronous system