Text preview for : dtaTechLibrary115971.pdf part of BenQ 6100/6200 Service manual for BenQ DLP Projectors Models 6100 and 6200.
Back to : dtaTechLibrary115971.part | Home
DLP PROJECTOR
SERVICE MANUAL
MODEL¡G PB6100 / PB6200
CAUTION
BEFORE SERVICING THE PROJECTOR,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
1
Index
1. Safety Precautions -------------------------------- 3
2. Engineering Specification---------------------- 4
3. Spare Parts List ---------------------------------- 32
4. Block Diagram ------------------------------------ 36
5. Packing Description ---------------------------- 44
6. Factory OSD Operation ------------------------ 50
7. Firmware upgrade procedure --------------- 57
8. RS232 Communication Protocol ----------- 61
9. Trouble Shooting Guide ----------------------- 73
10.CUSTOMER ACCEPTANCE CRITERIA ---- 78
11. Schematics ---------------------------------------- 96
2
1. Safety Precautions
3
2. Engineering Specification
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
3. Spare Parts List
Model : PB6100
Item Component Description Type
1 42.J8618.001 U/C PC+ABS PB6100 R
2 55.J7612.001 PCBA KEYPAD BD PB7200 BENQ850 2
3 54.J8612.001 BALLAST PHG201G16 PB6100 R
4 60.J8605.001 ASSY Lower Case PB6100 R
5 23.10102.001 BLOWER 12V 50*50*20MM ADDA R
6 60.J8617.001 ASSY LAMPBOX PB6100 R
7 23.10103.001 FAN 12V 70*70*25AXIAL ADDA R
8 60.J8604.001 ASSY R/C PB6100 R
9 55.J8608.001 PCBA REAR IR BD PB6100 2
10 65.J8602.001 ASSY AC INLET+THERM SW PB6100 R
11 55.J5019.001 PCBA THERMAL BD DX850 2
12 55.J5020.001 PCBA EMI BD DX850 2
13 55.J8601.001 PCBA MAIN BD PB6100 2
14 60.J8607.001 ASSY DOOR PB6100 R
15 55.J1313.001 PCB 1L SENSOR-B BD SL700 X MI 2
16 65.J8603.001 CW DIA44DEG110 PB6100 PRODISC R
17 55.J5019.001 PCBA THERMAL BD DX850 2
18 55.J8623.001 PCBA CHIP BD PB6100 2
19 65.J7602.001 PL ZOOM PB7200 ASIA R
20 71.08060.000 IC DMD 0.6SVGA 8060-624C 12DDR R
32
Model : PB6100
Item Component Description Type
21 31.J8601.001 BADGE AL PLATE PB6100 R
22 60.J1334.001 ASSY CAP LENS SL700X R
23 60.J8603.001 ASSY F/C PB6100 R
24 55.J8611.001 PCBA PFC BD PB6100 2
25 55.J8613.001 PCBA FAN BD PB6100 2
26 65.J5003.001 FOOT ADJ DX850 R
27 44.J0502.005 CTN 415*325*255 PB6100/BENQ VI R
28 47.J8605.001 CUSHION FRONT EPE PB6100 R
29 47.J8606.001 CUSHION REAR EPE PB6100 PB6100 R
30 50.72920.011 C.A MIN-DIN 4P S-VIDEO W/S 150 R
31 50.J0508.503 SIGNAL/C 15/15P 20276 1800MM R
32 50.J1303.501 CABLE RCA Y/Y 1600MM BLK R
33 56.26J86.001 REMOTE CR14AI PB6100 R
34 42.20019.002 BAG PE 250*350 LD FP741/NEC R
35 46.00003.012 CARD WARRANTY 7254E R
36 49.J8601.001 MANUAL USER PB6100/ PB6200 R
37 53.J8601.001 CD MANUAL USER PB6100/ PB6200 R
38 60.J8618.CG1 ASSY Service LAMP 200W/U PB6100 0
39 60.J8621.001 ASSY S2+ EGN 12D PB6100 0
33
Model : PB6200
Item Component Description Type
1 55.J8501.001 PCBA MAIN BD PB6200 2
2 42.J8618.001 U/C PC+ABS PB6100 R
3 55.J7612.001 PCBA KEYPAD BD PB7200 BENQ850 2
4 54.J8612.001 BALLAST PHG201G16 PB6100 R
5 55.J5020.001 PCBA EMI BD DX850 2
6 60.J8605.001 ASSY L/C PB6100 R
7 55.J8608.001 PCBA REAR IR BD PB6100 2
8 23.10103.001 FAN 12V 70*70*25AXIAL ADDA R
9 60.J8607.001 ASSY DOOR PB6100 R
10 23.10102.001 BLOWER 12V 50*50*20MM ADDA R
11 60.J8617.001 ASSY LAMPBOX PB6100 R
12 55.J1313.001 PCB 1L SENSOR-B BD SL700 X MI 2
13 65.J8603.001 CW DIA44DEG110 PB6100 PRODISC R
14 60.J8621.001 ASSY S2+ EGN 12D PB6100 0
15 55.J8623.001 PCBA CHIP BD PB6100 2
16 71.08060.000 IC DMD 0.6SVGA 8060-624C 12DDR R
17 31.J7601.061 NAME PLATE AL PB6200 R
18 55.J5019.001 PCBA THERMAL BD DX850 2
19 60.J1334.001 ASSY CAP LENS SL700X R
20 60.J8603.001 ASSY F/C PB6100 R
34
Model : PB6200
Item Component Description Type
21 55.J8611.001 PCBA PFC BD PB6100 2
22 55.J8613.001 PCBA FAN BD PB6100 2
23 65.J5003.001 FOOT ADJ DX850 R
24 44.J7601.051 CTN AB PB6100/BENQ(VI) R
25 45.L2701.011 LBL CTN 120*100 BLUE FP559 R
26 47.J8605.001 CUSHION FRONT EPE PB6100 R
27 22.91007.001 SKT PLUG 2/3P W/G R
28 27.01818.000 CORD SVT#18*3C 10A125V 1830US R
29 44.J0501.011 CTN ASSY 350*240*48 7765P R
30 50.72920.011 C.A MIN-DIN 4P S-VIDEO W/S 150 R
31 50.J0508.503 SIGNAL/C 15/15P 20276 1800MM R
32 50.J1303.501 CABLE RCA Y/Y 1600MM BLK R
33 56.26J86.001 REMOTE CR14AI PB6100 R
34 46.00003.012 CARD WARRANTY 7254E R
35 49.J8601.001 MANUAL USER PB6100/ PB6200 R
36 53.J8601.001 CD MANUAL USER PB6100/ PB6200 R
37 60.J8618.CG1 ASSY Service LAMP 200W/U PB6200 0
35
4. Block Diagram
PB6100 DMD projector being using the SGA DMD Engine made by BENQ, it included
front end circuitry that digitizes and scaling processes for the input analog VGA and TV signals. As
shown, in figure below the front end circuitry consists of :
1. Frond end Circuitry
1.1 Power supply module include PFC and DC/DC portion. DC/DC portion provide 12V, 5V and
3,3V for whole system.
12V Lamp Fan1
PFC
Lamp Power
IGNITOR
POWER SUPPLY
Module
AC IN
Lamp Fan Power Fan
DC to DC
EMI Filter
12V,5V,2.5V For System
1.2 Pixelworks scaler(PW166) with x86 CPU, OSD and SDRAM is used for system control. It control
whole system operation and with crucial role of this system.(Include fan speed, inter-lock SW,....)
1.3 A/D-decoder(AD9883) is used for decoding VGA analog signal to digital signal(RGB 888) which
provide 24 bit true color resolution. It can accept SOG(sync on green) and composite signal for PC
input. It also support YPbPr signal.
1.4 The video decoder that process TV video signal input. The TV video signal support both of
composite and S-video input and output YUV format to scaler processor. The basic block as
following.
36
From Power Supply
Regulator(3.3v)
12V,5V,2.5V
EEPROM
(16K bit)
ThERMAL IC
SENSOR
Scaler (memory +cpu+osd)
RGB888 Signal To DMD Driver
Power(12V,5V,2.5V) To DMD Driver
D-Sub Input
AD Converter
Control Signal To DMD Driver
S-Video& RCA input
Video Decoder
2. DMD driver board that transfer PW166 scaler output RGB888 signal to DMD chip acceptable
signal for driving DMD mirror operation. The relate diagram as below:
RAMBUS CLOCK RAMBUS RDRAM
400mHz
GEN
Address
Data &
60MHz
CLK
100MHz
DATA , CONTROL,60MHz
DATA-GY(7:0),RV(7:0),BU(7:0)
DMD Chip
VSync,HSync,ACTDATA
Front End (0.6 SVGA
PIXEL CLOCK(CLKIN) DDP 1000 VBIAS SR16C DDR)
Circuit VRST DMD
MBRST
Resetz,Poweron (15:0)
Voltage VCC2 RESET DRIVER
LampLitz GEN
VCC2
CWY(1:3)
SENSOR BOARD CWindex Control Signal MOTOR DRIVER COLOR Drum
Color Wheel
CWCTR
37
3. Whole system block diagram is show as below:
Lamp Module Optical Device
PFC EMI Filter
Optical Engine Lamp On Power Board and Ballast
DMD Color Wheel DC/DC
Fan/BD Ballast
Control Signal
Data &
2.5V, 5V, 12V
Fan
Power & DMD Driver
DMD CHIP Board
Control Data
Control Signal
Sensor Signal RGB 888
Main
Color Wheel
Sensor Board Board
Color Wheel
Sensor
PW166 Scaler
Keypad
A/D Converter Video Decoder
IR Rear Board
Video Input
D-Sub Input
S-video Input
Overview
The Main Board of PB6100 is mainly composed of an ADC converter(AD9883) , a
ImageProcessor(PW166) , a EEPROM(24C16) and a flash memory (MBM29LV800B) .
The input signal is analog RGB format , which comes from the standard VGA D_SUB connector ,
the analog signal input to ADC converter , which output RGB digital data stream to Image Processor .
The Image Processor also known as "Scaler" , which indicate its main function , expand or
downsize the digital picture from ADC to a fixed size digital image output .
The CPU which control the whole system is embedded inside the Image Processor , there is also
a Real Time Operating System which incorporates with the CPU as hardware layer interface .
The EEPROM stores the system information such as brightness , contrast ...which ensure the
system operates under the most user friendly circumstance .
The Flash memory stored the Software Program which control the system , the CPU will read the
Flash as its execution command .
38
Block Diagram
Below is the simple block diagram of PB6100 Main Board .
I2C
D_SUB
I2C EEPROM
Analg Flat Panel
Interface RGB888 signals
AD9883
Address
Control Signals Image Processor Flash
PW166
Data
I2C
S-Video
YUV 422
RCA
Video Decoder
SAA7118
Control Signals
Clock Clock
GEN signal
Control Signals
RGB 888
Signals
I2C
DMD Driver
As the diagram shown above , here is the function of every discrete blocks .
- D_SUB input
Analog RGB data input , the standard maximum analog input resolution is SXGA .There also
some interface signals from the VGA cable , they are
ADHSYNC Providing the Horizontal Synchronization signal to AD9883.
ADVSYNC - Providing the Vertical Synchronization signal AD9883.
DDC interface Providing Digital Display Channel , which include VCC(Pin9) ,
SCL(Pin15) , SDA(Pin12) .
- Analog Flat Panel Interface (ADC Converter) , AD9883
The ADC converter digitizes the input analog RGB data signal from D_SUB and output the
digital data streams to Image Processor .
The normal voltage level of analog RGB input signals is about 0.7V , while the ADC digital
signal output to Image Processor is LVTTL level , about 3.3V.
The ADC , AD9883 could supports up to pixel rate at about 140MHZ , which is about SXGA
75HZ analog input signal .
39
There are some other interface signals related to AD9883
SOGIN Sync On Green input from Image Processor , the signal enable the PB6100 support
the very special VGA input signal .
GCOAST Input signal from Image Processor , the signal enable the PB6100 support the
Machintosh analog input format .
GCLK Output to Image Processor as Pixel Clock , providing the reference clock for Image
Processor .
GHS Providing the Horizontal Synchronization signal to Image Processor .
GVS - Providing the Vertical Synchronization signal to Image Processor .
GRE,GGE,GBE Digital data stream to Image Processor which is higher than SXGA
75HZ .
. Image Processor (PW166)
The most important IC is the image Processor , here below list its main function
- Supporting input digital data stream up to UVGA and output digital data up to SXGA
- Two input port , which are Graphic port ( VGA format ) and Video port ( video decoder format ) .
- Frame rate conversion , the output frame rate is independent from the input frame rate and
the most important feature of the Image Processor is memory inside , there is no need
of external memory for frame rate convertion .
- Up and Down scaling of different input resolution , ensure the same output image size .
- Providing Bitmap OSD picture , which if more fancy than normal OSD chip .
- On chip Microprocessor
The Image Processor is a highly integrated circuit , it include MCU , Scaler , Memory , OSD . This
will increase the stability of the system .
There is some control signals list below
DCLK pixel clock output to DMD driver BD , provided as a reference clock for DMD driver
DVS Vertical synchronization signal output to DMD BD , provided as Vertical reference signal
for DMD driver .
DHS Horizontal synchronization signal output to DMD BD , provided as Horizontal reference
signal for DMD driver .
DEN Data enable signal output to DMD BD , provided as a valid data indicator signal for
DMD driver .
VCLK V-port pixel clock .
VPEN V-port data enable .
VVS V-port Vertical Synchronization .
VHS V-port Horizontal Synchronization .
VFILED V-port Even/Odd frame indicator .
RESETZ Output to DMD driver BD as RESETZ signal for DMD normal operation .
ABNORMAL Input to CPU for indicating abnormal condition , if the CPU detects an
40
abnormal status , it will disable lamp ignition .
POWERON Output to power to enable the other power source into normal working situation .
LAMPLIT Input signal as an indicator that the Lamp is ON or OFF
LED1, LED2 Output to enable the LED ON or OFF .
IRRCVR0 System IR input to CPU as remote control signals .
MCKEXT Memory clock to CPU .
DCKEXT Data clock to for Scaling .
I2C_SDA , I2C_SCL I2C format data transfer line .
. EEPROM
Store the system information for user friendly .
. Flash Memory
System software was stored in this chip , the memory size is 8M bits
. DDP1000
The DDP1000 transfer signal from PW166 to DMD for driving DMD mirror operation.
. Direct Rambus Memory
The DDP1000 utilizes a high speed Direct Rambus Memory. To support the RDRAM a
Direct Rambus clock generator CDCR83 is utilized. It can transfer input clock from 50MHz
to 400MHz.
IR Receiver schematic:
The IS1U621 is miniaturized receivers for infrared remote control systems. PIN diode and
pre-amplifier are assembled on lead frame, the epoxy package is designed as IR filter. The
demodulated output signal can directly be decoded by a microprocessor. The main benefit is the
reliable function even in disturbed ambient and the protection against uncontrolled output pulses.
Electronic System Protection for abnormal state:
The circuit of electronic system protection for abnormal state is used for the hardware light off and
power off in abnormal state of thermal and safety issues. If the protection function is active then the
software system will detect the abnormal signal.
41
Sensor BD:
The Sensor BD provides the color wheel index signal to DMD BD. The CWINDEX shall indicate the
beginning of the red light on the DMD device. The phase of the display data on the DMD based on the
CWINDEX signal. It can be configured to delay the CWINDEX for electronic alignment of the color
wheel. The timing of CWINDEX and the delayed CWINDEX is shown in Figure 1.
CWINDEX
DELAYED
CWINDEX
DMD COLOR Red
FIGURE 1
42
PB6100 Lamp on Sequence
Signal Voltage Change Description
POWERON Low High 1. This signal should go from low to high after all
the DC supplies are within spec. Then RESETZ
can go high.
2. After the power key pressed 3 second
continuously, the POWERON signal will
activate.
RESETZ Low High DMD is working, when the DMD reset.
LAMPEN Low High Lamp lights up.
LAMPLIT Low High Indicate "Lamp on".
PB6100 Normal Lamp off Sequence
Signal Voltage Change Description
RESETZ High Low DMD is off.
LAMPEN High Low Lamp is off.
LAMPLIT High Low Indicate "lamp off".
POWERON High Low Power down the system, but the peripherals of the
CPU still power on.
43
5. Packing Description
44
45
46
47
48
49
6. Factory Menu
1. How to enter factory menu:
I. Hold press "UP" button until the "Lamp hours info." OSD display on
bottom-right of screen (Fig-1)
(Fig-1) Lamp Hours Info
II. Press keypad and key simultaneously again, then enter
Factory menu.
50
2. Factory layer:
I. DMD layer (Fig-3):
(Fig-3) DMD layer
1. CW delay: Adjust color wheel delay.(Note this value before upgrade software)
2. White peak: Adjust DMD white peak.
In PC mode default value set 10, in Video mode is 0.
Software auto set this value as source find.
3. DLP Brightness: Adjust DLP Brightness.
Default setting is 36.Do not change this value.
4. DLP Contrast: Adjust DLP Contrast.
Default setting is 30.Do not change this value.
5. Burn-In Hour: set how many hours to burn-in.
Projector will enter burn-in mode on next selection.
6. Burn-In: After you set burn-in hours, set this selection to "On" and system will
enter going to burn-in immediately.
Projector will run color change (Red, Green, Blue, Black, White) on screen.
System will auto turn off after burn-in hour count down to 0 and burn-in
complete.
(You can also cancel burn-in sequence by set this selection to "Off").
51
II. ADC layer (Fig-4): (only available when input source is analog RGB)
(Fig-4) ADC layer
1. ADC Brightness: ADC brightness auto calibration black.
2. ADC Contrast: ADC contrast auto calibration white.
3. ADC Offset RGB: value to tell you calibrate result.
4. ADC Gain RGB: value to tell you calibrate result.
5. Fac Brightness: adjust default brightness value in source PC.
6. Fac Contrast: adjust default contrast value in source PC.
III. Color layer (Fig-5):
(Fig-5) Color layer
52
1. PbPr: enter PbPr color control Layer.
When Source is YPbPr (Never Change these setting)
(Note these values Before Upgrade Software)
PbPr G Offset : combine with user OSD brightness in YPbPr
PbPr G Gain: combine with user OSD contrast in YPbPr
PbPr R Offset: offset of color red
PbPr G Offset: offset of color green
PbPr R Gain: saturation R
PbPr B Gain: saturation B
2. 6500,11500 R,G,B: 6500K/11500k submenu
(Never Change these setting)
6500 R :gain of color red while color temp is 6500
6500 G :gain of color green while color temp is 6500
6500 B :gain of color blue while color temp is 6500
6500 R :gain of color red while color temp is 11500
11500 G :gain of color green while color temp is 11500
53
11500 B :gain of color blue while color temp is 11500
3. PC 9300 and Video 9300: 9300K submenu.
(Never Change these setting)
PC 9300 R :gain of color red while PC color temp is 9300
PC 9300 G :gain of color green while PC color temp is 9300
PC9300 B :gain of color blue while PC color temp is 9300
Video 9300 R :gain of color red while Video color temp is 9300
Video 9300 G :gain of color green while Video color temp is 9300
Video 9300 B :gain of color blue while Video color temp is 9300
IV. Optic layer (Fig-5):
(Fig-5) Optic layer
1. Test Pattern: system auto produce pattern for engineer test.
2. Spoke light: unit display full white.
3. Curtain Red: unit display full color red.
4. Curtain Green: unit display full color green.
54
5. Curtain Blue: unit display full color blue.
V. Lamp layer (Fig-6):
(Fig-6) Lamp layer
1. Interpolation: De-interlace Mode
2. Filter: system auto select Filter.
3. Lamp Hour: value to tell you lamp usage hours.
4. Usage Hour: value to tell you unit usage hours.
5. Fac Lamp Hours: Record all of the amp usage hours
6. Data Reset: Reset all data to default include factory assign value.
Never try to reset all data.
VI. Others layer (Fig-7):
(Fig-7) YPbPr layer
1. Gamma index: system auto select DLP gamma index
2. Gray value: adjust here to check DMD fail pixel.
55
3. Blue value: adjust here to check DMD fail pixel.
4. Scaling: tell you what scaling mode is using now.
5. Pc/PbPr Mode: index of input timing
6. RS232: Enable / Disable RS232 control
VII. FAN Layer.
T1-DMD: DMD sensor temperature
T2-Lamp: Lamp sensor temperature
T3-Blwr: Blower sensor temperature
F1-Lamp:Lamp fan speed in RPM
F2-Blst: Blaster fan speed in RPM
F3-Blwr : Blower fan speed in RPM
Manual Fan Speed: Change fan speed by manual.
SOG Threshold : Change SOG threshold level of AD
More Options: Change to Fac7 submenu
(Fac7 Submenu)
( This menu only for control testing)
56
7. Firmware upgrade procedure
PB6100/PB6100 Download Procedure
Hardware required
1. D-sub download cable (full ping D-SUB P/N : 50.J2402.201)
2. Download board ( P/N : 55.J1316.001 )
3. PS2 Download cable from download BD to PC ( P/N : 50.J0510.5D1 )
4. (Cable/RS232D MD8PM/DS9PF 1800MM)
5. Adaptor for Download BD ( DC12 V)
6. DVD player with YPbPr (Progressive) output
7. PC timing/pattern generator
8. Personal computer or laptop computer
Software required
1. FlashUpgrader.exe (or FlashUpgraderNT.exe if you're using Windows NT®)
2. pwSDK.inf
3. romcode.hex
4. configdata.hex
5. gui.hex
6. flasher.hex
Download procedure
1. Record CW delay value in factory page 1 on the unit to be upgraded.
Fig. 1
57
2. Record all Color Temperature values in factory page 3.
Fig. 2
3. Power down the projector and turn the power switch off after cooling.
4. Setup the download board as Fig. 3
PS2 Download cable to PC
P/N : 50.J0510.5D1
Download BD
P/N : 55.J1316.001
D-Sub connector to Projector
P/N : 50.J2402.201
Power supply DC 12 V
Fig. 3
5. Connect the D-Sub to PC input of Projector.
58
6. Run FlashUpgrader.exe and open the file pwSDK.inf. You can browse to locate it. Select the
correct COM port and use 115200 as the BAUD rate.(as Fig. 4)
Fig. 4
7. Press the "Flash" button , and then turn on the power switch. (as Fig. 5)
Fig. 5
8. Now the progress bar in the FlashUpgrader should be running.
9. Download is complete ,Pls turn off power switch , and turn ON power switch.
10. Power on projector and the factory settings should be restored.
59
Calibration procedure
1. Use any video pattern generator to output XGA 60Hz PC timing with 32 grayscale pattern.
Enter the factory OSD page 2 and execute ADC Brightness and ADC Contrast.(as Fig. 6)
Fig. 6
2. Restore CW delay value and color temperature values.
Verification
Check the version number in the factory OSD page 1.(as Fig. 1)
60
8. RS232 Communication Protocol / Codes
External Communication Protocol
External communication protocol include two parts¡G A. setup connecting, B. send command.
BenQ default Serial Port :
Baud Rate: 19200
Parity: none
Data bits: 8
Stop bits: 1
Flow Control:none
A. Setup Connecting
A typical Packet transaction session is shown in Figure 1
PC BenQ Projector
Host System Target
System
a
Packet to Target =>
<= ACK b
<= Packet to Host
c
Packet to Target =>
<= ACK d
<= Packet to Host
e Packet to Target =>
Figure 1
61
a. 1st Packet to Target (BenQ PB6XXX) structure like as below (Table 1)
Byte0 0xBE Magic
Byte1 0xEF Number
Byte2 0x01 Packet Type
Packet
Byte3 0x05 Packet size (Low)
Header
Byte4 0x00 Packet size (High)
Byte5 0xD1 CRC (Low)
Byte6 0xFA CRC (High)
Byte7 0x01 System Info Type
Byte8 0x02
Packet Version Number
Byte9 0x00
Payload
Byte10 0x00 Object ID
Byte11 0x00 Level
Table 1
b. The Ack of Packet to Host (PC) (Table 2)
Ack Byte0 0x1E PAK
Byte1 0xBE Magic
Byte2 0xEF Number
Byte3 0x01 Packet Type
Packet
Byte4 0x05 Packet size (Low)
Header
Byte5 0x00 Packet size (High)
Byte6 0xD1 CRC (Low)
Byte7 0xFA CRC (High)
Byte8 0x01 System Info Type
Byte9 0x02
Packet Version Number
Byte10 0x00
Payload
Byte11 0x00 Object ID
Byte12 0x00 Level
Table 2
PAK means that PC will follow the received Packet data
c. Packet same as 1st Packet (Table 1)
d. Same as Ack (Table 2)
62
e. Packet to Target (BenQ PB6XXX) structure (Table 3)
Byte0 0xBE Magic
Byte1 0xEF Number
Byte2 0x01 Packet Type
Packet
Byte3 0x05 Packet size (Low)
Header
Byte4 0x00 Packet size (High)
Byte5 0xA9 CRC (Low)
Byte6 0xC6 CRC (High)
Byte7 0x00 System Info Type
Byte8 0x00
Packet Version Number
Byte9 0x00
Payload
Byte10 0x00 Object ID
Byte11 0x00 Level
Table 3
B. Send Command
1. Introduction
Command packets consist of "Header" and "Payload". The Packet Header is consistent for all packets. The Packet
Payload type and content varies based on the type of packet sent. The entire packet size is variable, being the sum of the
fixed-size Packet Header and variable-sized Packet Payload.
Packet Header (fixed size) Packet Payload (variable size)
Figure 2 Packet Format
Packet Header Format
All Packets use the same Packet Header format illustrated Figure 3.
Byte 0 1 2 3 4 5 6
Magic Number Type Packet Payload Size CRC
0xBE 0xEF type size_lo size_hi crc_lo crc_hi
Figure 3 Packet Format
63
The Packet Header size is fixed at seven bytes (Intel byte ordering is used). The following code fragments are taken
from these source files
The Packet Header definition is shown below:
typedef struct
{
BYTE ePacketType; // type of the payload
WORD nPacketSize; // size of the payload
WORD nCRCPacket; // CRC for the entire packet
} PACKET_HEADER;
Magic Number
The Magic Number is a fixed value that is used to insure packet alignment if there are partial packets received or
bytes lost. The Magic Number is a WORD in length (2 bytes). The Magic Number value is 0xEFBE. Because Intel
byte ordering is used, the ls-byte of the word is sent first (byte0 = 0xBE), then the ms-byte (byte1 = 0xEF).
Packet Type
The Packet Type (ePacketType) is a BYTE in length number that defines the type of data in the packet. The following
entries are valid packet typess:
Table 4 Packet Type Name Packet Type Description
Packet Number
Types pt_INVALID 0 Invalid Packet Type
RESERVED 1 RESERVED
pt_EVENT 2 Host can send any event defined in BenQ PB6XXX
software.
pt_OPERATION 3 Host can send any operation defined in BenQ PB6XXX
software.
Packet Payload Size
The Packet Payload Size (nPacketSize) is a BYTE that defines the size of the Payload portion of the packet. If the
packet contains only header information, this is zero. Therefore, the total byte count of any packet = nPacketSize plus
7 (since the Packet Header is seven bytes long).
Packet Checksum (CRC)
Each packet is CRC'ed using the tables later in this document. This number is the CRC value for the complete packet
including the Packet Header and Packet Payload. The CRC is calculated with the nCRCPacket value initialized to
zero.
64
2. Packet Payload Definition
Event Packet Type
The Event packet is used by the host system to send virtual events (such as Zoom, Source, Auto Adjust, etc.) to the
target system. Packet payload size is 6 bytes.
Byte Field Name Field Value Description
0-1 Virtual Event Virtual Event ID as defined through
Configurator
2-5 Parameter Parameter that can be associated with the
event.
. Table 5 Event Packet Type Format
The source code definition of the Message packet data structure is:
typedef struct
{
WORD eEvent;
DWORD dwParam;
} EVENT_MESSAGE;
This lets you send any event defined in Configurator to the system including all remote, IR, or special events
Operation Packet Type
The Operation packet is used by the host system to execute operations (such as Brightness, Contrast, Image
Position, etc) in the target system. The Operation packet payload size is 25 bytes.
Byte Field Name Field Description
Value
0 Operation Type 1 OPERATION_SET
2 OPERATION_GET
3 OPERATION_INCREMENT
4 OPERATION_DECREMENT
5 OPERATION_EXECUTE
1-2 Operation Operation ID as defined in Configurator
3-4 Is Avail Operation is available
5-8 Operation Target Used for Operation with Targets. These Targets are
defined in configurator. For instance,
op_BRIGHTNESS has a Target of either MAIN or
PIP window..
9-12 Operation Value Value of the Set on a set or the Value of the
Get on a Return.
65
13-16 Operation Value of The Minimum Value of the set for operation
minimum. command.
17-20 Operation Value of The Maximum Value of the set for operation
maximum command.
21-24 Operation Value of The Increment Value of the set for operation
Increment command.
Table 6 Operation Packet Payload Format
The source code definition of the Operation packet data structure is:
typedef struct
{
eOPERATION_TYPE eOpType;
WORD eOperation;
WORD bisAvail;
DWORD dwTarget;
DWORD dwValue;
DWORD lmMin;
DWORD lmMax;
DWORD lmInc;
} OPERATION_MESSAGE;
This lets the user directly perform logical operations such as "Set Contrast = 80".
66
3. Send Command
PC BenQ PB6XXX
Host System Target System
a
Packet to Target =>
<= ACK b
Figure 4
a. The structure of Command (EX. input select) send to Target (BenQ PB6XXX) like as below
(Table 7)
Byte0 0xBE Magic
Byte1 0xEF Number
Byte2 0x02 Packet Type
Packet
Byte3 0x06 Packet size (Low)
Header
Byte4 0x00 Packet size (High)
Byte5 0x80 CRC (Low)
Byte6 0xC7 CRC (High)
Byte7 0xC9
Virtual Event ID
Byte8 0x00
Packet Byte9 0x00
Payload Byte10 0x00
Parameter
Byte11 0x00
Byte12 0x00
Table 7
b. Target return to Host (PC) Ack like as below Table 8
Ack Byte0 0x06 ACK
Table 8
67
C. Serial Communication Cable and Parameters
For external serial communication from a computer to BenQ projector, BenQ recommends
manfactures use RS-232 communations over a straight through serial cable a 9 pin female D-sub9
connector.
The standard D-sub9 connector on the computer is a male connector, and BenQ projector, too. The
wiring between the computer and BenQ projector is a straight through cable. A 9 pin female to 9 pin
female stright through cable is a very standard part and readily available in many lengths.
Female D-sub9 pinout numbering and definitions on both terminal :
Pin number Name
2 Transmit
3 Receive
5 Ground
PW Serial uses the following default serial port settings:
. Baud Rate: 19200
. Parity: none
. Data bits: 8
. Stop bits: 1
. Flow Control: none
68
D. Software Flow Chart
Build serial communication port
Baud rate: 19200
Parity: none
Data bits: 8
Stop bits: 1
Transmit 1st Packet (see Table 1)
Delay 100ms
Transmit 2nd Packet (see Table1)
Delay 100ms
Transmit 3rd Packet (see Table3)
Transmit Command (see Table7)
69
Command List
Event Packet Type command:
Command Packet Header (7 bytes) Packet Payload (6 bytes)
Power BE EF 02 06 00 13 CE AA 00 00 00 00 00
Auto BE EF 02 06 00 F7 C8 8E 00 00 00 00 00
Input select BE EF 02 06 00 C4 C8 8D 00 00 00 00 00
Menu BE EF 02 06 00 26 C9 8F 00 00 00 00 00
Exit BE EF 02 06 00 FE CA 97 00 00 00 00 00
Zoom + BE EF 02 06 00 AD CD B4 00 00 00 00 00
Zoom - BE EF 02 06 00 7C CC B5 00 00 00 00 00
PIP Source BE EF 02 06 00 37 C6 CE 00 00 00 00 00
Freeze BE EF 02 06 00 46 CE AF 00 00 00 00 00
Ratio BE EF 02 06 00 04 C6 CD 00 00 00 00 00
Force PC BE EF 02 06 00 AE C6 C7 00 00 00 00 00
Force Video BE EF 02 06 00 51 C6 C8 00 00 00 00 00
Force S-Video BE EF 02 06 00 80 C7 C9 00 00 00 00 00
Force YPbPr BE EF 02 06 00 B3 C7 CA 00 00 00 00 00
RS232 Power ON BE EF 02 06 00 3E C4 D7 00 00 00 00 00
RS232 Power OFF BE EF 02 06 00 C1 C4 D8 00 00 00 00 00
Blank BE EF 02 06 00 1A CC B3 00 00 00 00 00
Operation Packet Type command
PC Picture Controls
Command Packet Header (7 bytes) Packet Payload (25 bytes)
Brightness + BE EF 03 19 00 44 A0 03 C7 02 CC CC 00 00 00 00 CC×16
Brightness - BE EF 03 19 00 2A 0A 04 C7 02 CC CC 00 00 00 00 CC×16
Contrast + BE EF 03 19 00 2E 19 03 C5 02 CC CC 00 00 00 00 CC×16
Contrast - BE EF 03 19 00 40 B3 04 C5 02 CC CC 00 00 00 00 CC×16
YPbPr Picture Controls
Command Packet Header (7 bytes) Packet Payload (25 bytes)
Brightness + BE EF 03 19 00 7B 14 03 D9 02 CC CC FF FF FF FF CC×16
Brightness - BE EF 03 19 00 15 BE 04 D9 02 CC CC FF FF FF FF CC×16
Contrast + BE EF 03 19 00 FA 6A 03 F1 02 CC CC FF FF FF FF CC×16
Contrast - BE EF 03 19 00 94 C0 04 F1 02 CC CC FF FF FF FF CC×16
70
S-Video / Composite Video Picture Controls
Command Packet Header (7 bytes) Packet Payload (25 bytes)
Brightness + BE EF 03 19 00 E9 18 03 35 02 CC CC 00 00 00 00 CC x16
Brightness - BE EF 03 19 00 87 B2 04 35 02 CC CC 00 00 00 00 CC x16
Contrast + BE EF 03 19 00 16 FC 03 36 02 CC CC 00 00 00 00 CC x16
Contrast - BE EF 03 19 00 78 56 04 36 02 CC CC 00 00 00 00 CC x16
Color + BE EF 03 19 00 83 A1 03 37 02 CC CC 00 00 00 00 CC X16
Color - BE EF 03 19 00 ED 0B 04 37 02 CC CC 00 00 00 00 CC x16
Tint + BE EF 03 19 00 00 0F 03 4A 02 CC CC 00 00 00 00 CC x16
Tint - BE EF 03 19 00 6E A5 04 4A 02 CC CC 00 00 00 00 CC x16
Sharpness + BE EF 03 19 00 43 D0 03 38 02 CC CC 00 00 00 00 CC x16
Sharpness - BE EF 03 19 00 2D 74 04 38 02 CC CC 00 00 00 00 CC x16
Misc Controls
Command Packet Header (7 bytes) Packet Payload (25 bytes)
Color Temp 50 (0) BE EF 03 19 00 69 49 01 ED 02 CC CC 00 00 00 00 CE FF FF FF
CC CC CC CC CC CC CC CC CC CC CC CC
0 (10) BE EF 03 19 00 1C 89 01 ED 02 CC CC 00 00 00 00 00 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
50 (20) BE EF 03 19 00 69 1C 01 ED 02 CC CC 00 00 00 00 32 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
PIP Controls
PIP Size
Off BE EF 03 19 00 15 02 01 8C 02 CC CC 01 00 00 00 03 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
Small BE EF 03 19 00 E4 42 01 8C 02 CC CC 01 00 00 00 00 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
Medium BE EF 03 19 00 74 83 01 8C 02 CC CC 01 00 00 00 01 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
Large BE EF 03 19 00 85 C3 01 8C 02 CC CC 01 00 00 00 02 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
PIP Position
Upper-Left BE EF 03 19 00 1D 66 01 43 02 CC CC 01 00 00 00 00 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
Upper-Center BE EF 03 19 00 8D A7 01 43 02 CC CC 01 00 00 00 01 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
Upper-right BE EF 03 19 00 7C E7 01 43 02 CC CC 01 00 00 00 02 00 00 00
71
CC CC CC CC CC CC CC CC CC CC CC CC
Mid-Left BE EF 03 19 00 EC 26 01 43 02 CC CC 01 00 00 00 03 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
Mid-Center BE EF 03 19 00 DE 64 01 43 02 CC CC 01 00 00 00 04 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
Mid-Right BE EF 03 19 00 4E A5 01 43 02 CC CC 01 00 00 00 05 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
Lower-Left BE EF 03 19 00 BF E5 01 43 02 CC CC 01 00 00 00 06 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
Lower-Center BE EF 03 19 00 2F 24 01 43 02 CC CC 01 00 00 00 07 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
Lower-Right BE EF 03 19 00 DB 61 01 43 02 CC CC 01 00 00 00 08 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
PIP Source
S-Video BE EF 03 19 00 E8 36 01 DA 02 CC CC 01 00 00 00 03 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
Video BE EF 03 19 00 DA 74 01 DA 02 CC CC 01 00 00 00 04 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
PIP Brightness BE EF 03 19 00 FE 0B 01 35 02 CC CC 01 00 00 00 CE FF FF FF
-50 (48) CC CC CC CC CC CC CC CC CC CC CC CC
0 (126) BE EF 03 19 00 8B CB 01 35 02 CC CC 01 00 00 00 00 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
50 (204) BE EF 03 19 00 FE 5E 01 35 02 CC CC 01 00 00 00 32 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
PIP Contrast BE EF 03 19 00 01 EF 01 36 02 CC CC 01 00 00 00 CE FF FF FF
-50 (58) CC CC CC CC CC CC CC CC CC CC CC CC
0 (131) BE EF 03 19 00 74 2F 01 36 02 CC CC 01 00 00 00 00 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
50 (204) BE EF 03 19 00 01 BA 01 36 02 CC CC 01 00 00 00 32 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
PIP Color BE EF 03 19 00 94 B2 01 37 02 CC CC 01 00 00 00 CE FF FF FF
50 (129) CC CC CC CC CC CC CC CC CC CC CC CC
0 (157) BE EF 03 19 00 E1 72 01 37 02 CC CC 01 00 00 00 00 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
-50 (185) BE EF 03 19 00 94 E7 01 37 02 CC CC 01 00 00 00 32 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
PIP Tint -50 (0) BE EF 03 19 00 17 1C 01 4A 02 CC CC 01 00 00 00 CE FF FF FF
CC CC CC CC CC CC CC CC CC CC CC CC
0 (128) BE EF 03 19 00 62 DC 01 4A 02 CC CC 01 00 00 00 00 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
50 (255) BE EF 03 19 00 17 49 01 4A 02 CC CC 01 00 00 00 32 00 00 00
CC CC CC CC CC CC CC CC CC CC CC CC
72
9. Trouble Shooting Guide
Optical Engine
No. Item Trouble Shooting Guide
1. Change lamp
1 Brightness 2. Check overfill size: If overfill too large, re-install SL and AL to
ensure correct position
1. If Uniformity is within 3% of spec: Change lamp
2. Check FM installation
2 Uniformity
3. Check overfill size: If overfill too small, re-install SL and AL
to ensure correct position
1. Clean DMD
3 FOFO Contrast
2. Clean PL
1. Clean PL
4 ANSI Contrast 2. Clean DMD
3. Change PL
5 Color Check CW 50% point. Replace CW if necessary
6 Color Uniformity Change CM
1. Readjust LP: Make sure the LP end is touching with
7 Blue Edge DMD_HSG Datum
2. Check LP: If LP is crushed, replace with new LP
1. re-install SL and AL to ensure correct position
8 Blue/Purple Border
2. Check FM installation
1. Change Projection Lens
9 Focus
2. Put shim metal between upper side of DMD and DMD datum
10 Dust Clean DMD
1. Check connector between FPC and M/B
2. Re-install DMD with FPC
Horizontal/Vertical
11 3. Check if any pin of C-Spring is missing or damaged
Strips
4. Change new FPC/C-Spring
5. Change new DMD
12 Pixel Fail Change new DMD
73
Main board
1.chk voltage input from F/B : 2.5V,5V,12V
2.chk oscillator Y2,Y3 output frequency (16.257MHz,10MHz)
3.chk MCLK(U24-5,130MHz) and DCLK(U25-5,40MHz)
System no work 4.chk U17 whether S/W inside or bad soldering
5.change U22(bad soldering)
Yes 6.chk Reset IC (U14)
No 7.chk Abnorm al signal
8.chk Resetz(RN25-5),Poweron(RN25-6) ,DVS(RN18-3),DEN(RN18-
1),DHS(RN18-2),DCLK(RN18-4)
No data
1.chk output from U15(RN6,RN7,RN8,RN9,RN10,RN11) [graphics input]
Yes 2.chk output from U13 (Via VUV[0:7}&VY{0:7]) [video input]
No 3.chk U22 and its peripherals (as above block)
No im age when graphics
is the current input 1.chk D_SUB cable and L9
2.chk GHS(UH2-4),GVS(UH702-4)
3.chk U15 voltage source U12(3.3V),UB16(3.3V)
Yes 4.chk U15 GHS(64),GVS(63),GFBK(65),G CLK(66)
No 5.chk U15 soldering
6.change U15
No im age when video
is the current input 1.chk U13 voltage source U12,UA6
4.chk Y1 output frequency(24.576MHz)
Yes 5.chk U13 output signals to U22
6.chk U13 soldering
No 7.chagne U13
Unable to download 1.change U17
Yes
2.chk U711 enable pins(1,4)
No
Yes 1.change U21
Unable to save
O SD setting
1.chk RN725-RN728 soldering
No 2.chk U27,U28
Yes
Keypad
m alfunction
No
74
DMD Driver
Start
Yes
1.chk J702,2.5V(4,,5,6),5V(3),12V(1)
Power Voltage No
2.chk bead L710-L714,L44
Yes
DDP 1000
function 1.chk clock frequency (unit:MHz)
No a.Y901(30)b.Y5(20) C.UY1(100)
C.Motor Controller(8.33)
Yes 2.chk ACTDATA,POWERON,RESETZ,CLKIN,HSYNC,
VSYNC,SYNCVALID from Front End
3.chk CW spinning frequency 120Hz , if wrong, chk
1.LAMPEN Signal to Ballast. MTRDATA , MTRCLK , MTRSELZ
2. 3.5s after LAMPLIT,DMD Become Active and Peripheral
Display an Image . No
Hardware
.
Yes
Image Color
No 1.chk CW spinning in cloclwise
2.chk CW tape position and width
3.chk cutrain displayed 220us after CW index
Yes 4.sequence color transition during CW spoke interval
Image Quality 1.Output from DAD1000 : VBIAS(22-25V),VRST(-26V),