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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14530B Dual 5-Input Majority Logic Gate
The MC14530B dual fiveinput majority logic gate is constructed with Pchannel and Nchannel enhancement mode devices in a single monolithic structure. Combinational and sequential logic expressions are easily implemented with the majority logic gate, often resulting in fewer components than obtainable with the more basic gates. This device can also provide numerous logic functions by using the W and some of the logic (A thru E) inputs as control inputs. · Diode Protection on All Inputs · Supply Voltage Range = 3.0 Vdc to 18 Vdc · Capable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load Over the Rated Temperature Range MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage L SUFFIX CERAMIC CASE 620
P SUFFIX PLASTIC CASE 648
D SUFFIX SOIC CASE 751B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Value Unit V V 0.5 to + 18.0 ± 10 500 Vin, Vout Iin, Iout PD TL Input or Output Voltage (DC or Transient) 0.5 to VDD + 0.5 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature mA mW Tstg 65 to + 150 260
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC
TA = 55° to 125°C for all packages.
_C _C
W 6 1 2 3 4 5 * Z = M5 Z = M5 Z = M5 9 10 11 12 13 14
BLOCK DIAGRAM
Lead Temperature (8Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: 12 mW/_C From 100_C To 125_C
A B C D E
7 M5 Z
LOGIC TABLE
INPUTS A B C D E For all combinations of inputs where three or more inputs are logical "0". For all combinations of inputs where three or more inputs are logical "1". W 0 1 0 1 Z 1 0 0 1
W = (ABC+ABD+ABE+ACD+ W = (ACE+ADE+BCD+BCE+ W = (BDE+CDE) W
A B C D E M5 15 Z
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
W * M5 is a logical "1" if any three or more inputs are logical "1".
Exclusive NOR Exclusive OR
TRUTH TABLE
M5 0 0 1 1 W 0 1 0 1 Z 1 0 0 1
VDD = PIN 16 VSS = PIN 8
REV 3 1/94
©MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14530B 1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 3.0 0.64 1.6 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- ± 0.1 -- 0.25 0.5 1.0 2.4 0.51 1.3 3.4 0.51 1.3 3.4 -- -- -- -- -- 4.2 0.88 2.25 8.8 0.88 2.25 8.8 ± 0.00001 5.0 0.0005 0.0010 0.0015 -- -- -- -- -- -- -- ± 0.1 7.5 0.25 0.5 1.0 1.7 0.36 0.9 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- ± 1.0 -- 7.5 15 30 mAdc 3.85 7.6 12.1 -- -- -- 3.75 7.5 12 2.75 5.50 8.25 -- -- -- 3.75 7.5 12 -- -- mAdc Min -- -- -- 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.2 2.5 3.0 0.05 0.05 0.05 -- -- -- 1.25 2.5 3.0 0.05 0.05 0.05 -- -- -- 1.15 2.4 2.9 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD µAdc pF µAdc IT IT = (0.75 µA/kHz) f + IDD IT = (1.50 µA/kHz) f + IDD IT = (2.25 µA/kHz) f + IDD µAdc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. * To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.002.
PIN ASSIGNMENT
AA BA CA DA EA WA ZA VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD ZB WB EB DB CB BB AB
MC14530B 2
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Symbol tTLH, tTHL VDD 5.0 10 15 Min -- -- -- Typ # 100 50 40 Max 200 100 80 Unit ns Propagation Delay Time A, C, W = VDD; B, E = Gnd; D = Pulse Generator tPLH = (1.7 ns/pF) CL + 290 ns tPLH = (0.66 ns/pF) CL + 127 ns tPLH = (0.5 ns/pF) CL + 85 ns tPHL = (1.7 ns/pF) CL + 345 ns tPHL = (0.66 ns/pF) CL + 162 ns tPHL = (0.5 ns/pF) CL + 95 ns A, B, C, D, E = Pulse Generator; W = VDD tPLH = (1.7 ns/pF) CL + 170 ns tPLH = (0.66 ns/pF) CL + 87 ns tPLH = (0.5 ns/pF) CL + 60 ns tPHL = (1.7 ns/pF) CL + 195 ns tPHL = (0.66 ns/pF) CL + 92 ns tPHL = (0.5 ns/pF) CL + 75 ns A, B, C, D, E = Gnd; W = Pulse Generator tPHL, tPLH = (1.7 ns/pF) CL + 145 ns tPHL, tPLH = (0.66 ns/pF) CL + 72 ns tPHL, tPLH = (0.5 ns/pF) CL + 50 ns tPLH 5.0 10 15 tPHL 5.0 10 15 5.0 10 15 tPHL 5.0 10 15 5.0 10 15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 375 160 110 430 195 120 255 120 86 280 125 100 230 105 75 960 400 300 1200 540 410 640 300 210 750 330 250 575 265 190 ns ns ns tPLH ns tPLH, tPHL ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD 16 A B C D PULSE GENERATOR E W A B C D E W 8 VDD VSS VSS CL Z CL Z 20 ns 50% DUTY CYCLE 20 ns Vin
Figure 1. Power Dissipation Test Circuit and Waveform
MOTOROLA CMOS LOGIC DATA
MC14530B 3
SEQUENTIAL LOGIC APPLICATIONS
W A B C D E
COINCIDENT FLIPFLOP
1 0 1 x y
Z
x 0 0 0 1
y 0 1 0 1
Qn+1 0 Q Q 1 A flipflop that will change only when both inputs agree.
ASTABLE MULTIVIBRATOR
0 0 1 x y W A B C D E
t
Z
x 0 0 1 1
y 0 1 0 1
Qn+1 1 2 2 1 A flipflop with three output conditions, where the third state is in oscillation between "1" and "0". The period of oscillation is twice the delay of the gate and the feedback element.
COINCIDENT FLIPFLOP
1 x y z W A B C D E tx Z 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 Qn+1 0 Qn Qn Qn Qn Qn Qn 1 The flipflop changes state only when all "1's" or all "0's" are entered. This configuration may be extended by cascading M5 gates to cover ninputs where all inputs must be "1's" or "0's" before the output will change. As an example, this configuration is useful for controlling an nstage up/down counter that is to cycle from a minimum to maximum count and back again without flipping over (from all "1's" to all "0's".)
MC14530B 4
MOTOROLA CMOS LOGIC DATA
BASIC COMBINATIONAL FUNCTIONS
1 W A B C D E Z M5 5INPUT MAJORITY GATES 1 1 0 W Z A B C W Z A B C 3INPUT OR GATE 1 0 0 W Z A B C 3INPUT AND GATE AND3 OR3 M3 3INPUT MAJORITY GATES 1 1 1 0 1 1 W Z A B C NOR3 0 1 0 W Z A B C M3 0 W A B C D E Z M5
5INPUT MAJORITY LOGIC GATE APPLICATIONS
Each package labeled M5 is a single majority logic gate using five inputs, A thru E, and one output Z. 1. Majority Logic Gate Array yielding the symmetric function of 1 thru 7 variables true, out of 7 input variables (X1... X7) (e.g., if any twoinput variables are true (logical "1"), Z1 and Z2 are true (logical "1")
0 0
A B C M5 D E
Z7
0
A B C M5 D E
Z6
3INPUT NOR GATE 0 0 0 W Z A B C 3INPUT NAND GATE NAND3 0 0 A B C M5 D E
M5
Z5
DOUBLING THE WEIGHT OF INPUT VARIABLE A BY TYING IT TO ANY TWO INPUTS
W W A A B C D Z
0 M5
(AB + AC + AD + BCD)
W
0 0 M5 M5
A B C M5 D E
Z4
To S0 S1 S2 S3 S4
W A B C D E
CORRELATION OF MULTIPLE SAMPLES WITH A TEST BIT
Z CORRELATION OF 60%, 80%, 100% The gate will have a "1" output if the test bit To matches or correlates with 3, 4 or 5 of the sample bits S0S4. Z
A B C M5 D E
Z3
0 1
1 M5 M5
1
To To S0 S1 S2 S3
W A B C D E
A B C M5 D E
Z2
CORRELATION OF 75%, 100% 1 1 M5 1 1 M5 1 1 A B C M5 D E
Z1
To To To S0 S1 S2
W A B C D E Z X1 X2 X3 X4 X5 X6 X7
CORRELATION OF 100%
MOTOROLA CMOS LOGIC DATA
MC14530B 5
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 62010 ISSUE V
A
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
B
1 8
C
L
T
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
T B
S
0.25 (0.010)
T A
S
P SUFFIX PLASTIC DIP PACKAGE CASE 64808 ISSUE R
A
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
T H G D
16 PL
SEATING PLANE
K
J T A
M
M
0.25 (0.010)
M
MC14530B 6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B05 ISSUE J
A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
B
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C T
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
T B
S
A
S
DIM A B C D F G J K M P R
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MOTOROLA CMOS LOGIC DATA
*MC14530B/D*
MC14530B MC14530B/D 7