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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MC14534B 5 Cascaded BCD Counters
The MC14534B is composed of five BCD ripple counters that have their respective outputs multiplexed using an internal scanner. Outputs of each counter are selected by the scanner and appear on four (BCD) pins. Selection is indicated by a logic high on the appropriate digit select pin. Both BCD and digit select outputs have three­state controls providing an "open­circuit" when these controls are high and allowing multiplexing. Cascading may be accomplished by using the carry­out pin. The counters and scanner can be independently reset by applying a high to the counter master reset (MR) and the scanner reset (SR). The MC14534B was specifically designed for application in real time or event counters where continual updating and multiplexed displays are used. · · · · · · Four Operating Modes (See truth table) Input Error Detection Circuit Clock Conditioning Circuits for Slow Transition Inputs Counter Sequences on Positive Transition of Clock A Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low­power TTL Loads or One Low­power Schottky TTL Load Over the Rated Temperature Range
L SUFFIX CERAMIC CASE 623 P SUFFIX PLASTIC CASE 709

DW SUFFIX SOIC CASE 751E

ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC

TA = ­ 55° to 125°C for all packages.

BLOCK DIAGRAM
TO CAPACITORS 22 23 CLOCK B CLOCK A 4 MASTER 2 RESET C ÷ 10 Q0 5 MODE A MODE B 6 MUX 18 Q2 BCD OUT Q1 R SCANNER 10 CLOCK 20 SCANNER Q0 OUTPUT CONTROL MUX MUX MUX MUX 17 Q3 PULSE SHAPER PULSE ERROR DETECTOR 3 ERROR OUT TEST CONTROL 1 VDD = PIN 24 VSS = PIN 12

UNITS Cn+4 Q3 CARRY CONTROL C ÷ 10 Q0

TENS Cn+4 Q3

HUNDREDS C ÷ 10 Q0 Cn+4 Q3

THOUSANDS C ÷ 10 Q0 Cn+4 Q3

TEN THOUSANDS C ÷ 10 Cn+4 Q0 Q3

13 CARRY OUT

SCANNER RESET 9

19

21 15 3­STATE DIGIT CONTROL

3­STATE BCD CONTROL

7 NOTE: = 3­STATE OUTPUT BUFFER DS1

8 DS2

14 DS3

16 DS4

11 DS5

3­State Control 0 1

Out Q or DS High Impedance

DIGIT SELECT

REV 3 1/94

©MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995

MC14534B 1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS (Voltages referenced to VSS)
Symbol VDD Parameter DC Supply Voltage Value Unit V V ­ 0.5 to + 18.0 Vin, Vout Iin, Iout PD Tstg TL Input or Output Voltage (DC or Transient) ­ 0.5 to VDD + 0.5 ± 10 500 ­ 65 to + 150 260 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Lead Temperature (8­Second Soldering) mA mW

_C _C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

v

v

* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: ­ 12 mW/_C From 100_C To 125_C

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 5.0 10 15 IOL 5.0 10 15 15 -- ­ 3.0 ­ 0.64 ­ 1.6 ­ 4.2 0.64 1.6 4.2 ­ 0.31 ­ 0.31 ­ 0.9 0.024 0.06 1.3 -- -- VIH 5.0 10 15 4.0 8.0 12 Min -- -- -- 4.95 9.95 14.95 -- -- --

­ 55_C

25_C

125_C

Max

Min -- -- --

Typ # 0 0 0 5.0 10 15 1.5 3.0 4.5 3.5 7.0 11

Max

Min -- -- --

Max

Unit Vdc

Output Voltage Vin = VDD or 0

"0" Level

0.05 0.05 0.05 -- -- -- 1.0 2.0 3.0 -- -- -- -- -- -- -- -- -- --

0.05 0.05 0.05 -- -- -- 1.0 2.0 3.0 -- -- -- -- -- -- -- -- -- --

0.05 0.05 0.05 -- -- -- 1.0 2.0 3.0

"1" Level Vin = 0 or VDD Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "0" Level

VOH

4.95 9.95 14.95 -- -- -- 4.0 8.0 12 ­ 2.4 ­ 0.51 ­ 1.3 ­ 3.4 0.51 1.3 3.4 ­ 0.25 ­ 0.25 ­ 0.75 0.02 0.05 0.25 -- --

4.95 9.95 14.95 -- -- -- 4.0 8.0 12 ­ 1.7 ­ 0.36 ­ 0.9 ­ 2.4 0.36 0.9 2.4 ­ 0.17 ­ 0.17 ­ 0.51 0.014 0.035 0.175 -- --

Vdc

VIL

Vdc

Vdc -- -- -- mAdc ­ 4.2 ­ 0.88 ­ 2.25 ­ 8.8 0.88 2.25 8.8 ­ 0.8 ­ 0.4 ­ 1.6 0.03 0.09 1.63 ± 0.00001 5.0 -- -- -- -- -- -- -- mAdc

Sink

Output Drive Current -- Pins 1 and 22 (VOH = 2.5 Vdc) (VOH = 9.5 Vdc) Source (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Sink

IOH -- -- -- -- -- ± 0.1 -- -- -- -- -- -- ± 0.1 7.5 -- -- -- -- -- ± 1.0 --

mAdc

mAdc

Iin Cin

µAdc pF (continued)

#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.

MC14534B 2

MOTOROLA CMOS LOGIC DATA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) (continued)
Characteristic Symbol IDD VDD Vdc 5.0 10 15 5.0 10 15 ­ 55_C Min -- -- -- Max 5.0 10 20 25_C 125_C Min -- -- -- Typ # 0.010 0.020 0.030 Max 5.0 10 20 Min -- -- -- Max 150 300 600 Unit Quiescent Current (Per Package) µAdc Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Three­State Leakage Current IT IT = (0.5 µA/kHz) f + IDD IT = (1.0 µA/kHz) f + IDD IT = (1.5 µA/kHz) f + IDD -- ± 0.1 -- ± 0.0001 µAdc Scan Oscillator Frequency = 1.0 kHz ITL 15 ± 0.1 -- ± 3.0 µAdc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL ­ 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD ­ VSS) in volts, f in kHz is input frequency, and k = 0.001.

MOTOROLA CMOS LOGIC DATA

MC14534B 3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C, see Figure 1)
Characteristic Symbol tTLH, tTHL VDD Vdc 5.0 10 15 Min -- -- -- Typ # 100 50 40 Max 200 100 80 Unit ns Output Rise and Fall Time Propagation Delay Time, Clock to Q tPLH, tPHL = (1.8 ns/pF) CL + 4.0 µs tPLH, tPHL = (0.8 ns/pF) CL + 1.5 µs tPLH, tPHL = (0.6 ns/pF) CL + 1.0 µs Clock to Carry Out tPLH = (1.8 ns/pF) CL + 3.3 µs tPLH = (0.8 ns/pF) CL + 1.1 µs tPLH = (0.6 ns/pF) CL + 0.8 µs Master Reset to Q tPHL = (1.8 ns/pF) CL + 1.8 µs tPHL = (0.8 ns/pF) CL + 0.6 µs tPHL = (0.6 ns/pF) CL + 0.5 µs Master Reset to Error Out tPHL = (1.8 ns/pF) CL + 0.57 µs tPHL = (0.8 ns/pF) CL + 0.19 µs tPHL = (0.6 ns/pF) CL + 0.11 µs Scanner Clock to Q tPLH, tPHL = (1.8 ns/pF) CL + 1.8 µs tPLH, tPHL = (0.8 ns/pF) CL + 0.6 µs tPLH, tPHL = (0.6 ns/pF) CL + 0.5 µs Scanner Clock to Digit Select tPHL, tPLH = (1.8 ns/pF) CL + 1.5 µs tPHL, tPLH = (0.8 ns/pF) CL + 0.5 µs tPHL, tPLH = (0.6 ns/pF) CL + 0.4 µs Propagation Delay Time 3­State Control to Q tPLH, tPHL 5.0 10 15 tPLH 5.0 10 15 tPHL 5.0 10 15 tPHL 5.0 10 15 tPLH, tPHL 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1000 500 375 320 130 80 900 150 100 2000 600 450 1060 350 250 0.6 0.2 0.12 1.8 0.6 0.5 1.5 0.5 0.4 75 45 40 120 55 40 120 55 45 160 70 45 1.0 3.0 5.0 500 190 125 160 65 40 270 80 50 900 300 250 550 205 140 1.5 .5 0.38 µs 3.6 1.2 0.9 µs 3.0 1.0 0.75 150 90 80 240 110 80 240 110 90 320 140 90 0.5 1.0 1.2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns -- -- -- 1.8 0.6 0.5 3.6 1.2 0.9 µs -- -- -- 3.3 1.1 0.8 6.6 2.2 1.7 µs -- -- -- 4.0 1.5 1.0 8.0 3.0 2.25 µs µs tPLH, tPLH tPHZ tPZH ns tPLZ ns tPZL ns Clock Pulse Frequency fcl MHz Clock or Scanner Clock Pulse Width tWH ns Scanner Reset Pulse Width tw ns Scanner Reset Removal Time trem ns Master Reset Pulse Width tWH(R) ns Master Reset Removal Time trem ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.

MC14534B 4

MOTOROLA CMOS LOGIC DATA

COUNTER TIMING DIAGRAM
1 2 CLOCK A UNITS Q0 UNITS Q1 UNITS Q2 UNITS Q3 UNITS Cn + 4 TENS Q0 TENS Q3 TENS Cn + 4 HUNDREDS Q0 HUNDREDS Q3 HUNDREDS Cn + 4 THOUSANDS Q0 THOUSANDS Q3 THOUSANDS Cn + 4 TEN THOUSANDS Q0 TEN THOUSANDS Q3 CARRY OUT MASTER RESET 3 4 5 6 7 8 9 10 102 103 104 105 106

MODE CONTROL TRUTH TABLE
Mode A 0 0 1 1 Mode B 0 1 1 0 First Stage Output Normal Count and Display Inhibited Inhibited Counts 3, 4, 5, 6, 7 = 5 Counts 8, 9, 0, 1, 2 = 0 Carry to Second Stage At 9 to 0 transition of first stage Input Clock At 4 to 5 transition of first stage At 7 to 8 transition of first stage Application 5­digit Counter Test Mode: Clock directly into stages 1, 2, and 4. 4­digit counter with ÷ 10 and roundoff at front end. 4­digit counter with 1/2 pence capability.

MOTOROLA CMOS LOGIC DATA

MC14534B 5

SCANNER TIMING DIAGRAM
SCANNER CLOCK SCANNER RESET DS1 DS2 DS3 DS4 DS5 TEN THOUSANDS THOUSANDS HUNDREDS TENS UNITS

NOTE: If Mode B = 1, the first decade is inhibited and S1 will not go high, and the cycle will be shortened to four stages. DS5 is selected automatically when Scanner Reset goes high.

ERROR DETECTION TIMING DIAGRAM
RESET

CLOCK A CLOCK B ERROR OUT GOOD PULSE ERROR 1 ERROR 2 GOOD PULSE

ERROR 3

ERROR 4

NOTE: Error detector looks for inverted pulse on Clock B. Whenever a positive edge at Clock A is not accompanied by a negative pulse at Clock B (or vice­versa) within a time period of the one­shots an error is counted. Three errors result in Error Out to go to a "1". If error detection is not needed, tie Clock B high or low and leave Pins 1 and 22 unconnected.

CLOCK SKEW RANGE
1000 ALLOWABLE CLOCK SKEW (ns/pF) 500 300 100 50 30 10 5.0 3.0 1.0 3.0
SKEW IN THIS RANGE RESULTS IN NO ERROR COUNTED. SKEW IN THIS RANGE RESULTS IN COUNTED ERROR. MAX SKEW IN THIS RANGE MAY OR MAY NOT RESULT IN COUNTED ERROR.

TYP MIN

NOTES: 1. The skew is the time difference between the low­to­high transition of CA to the high­to­ low transition of CB or vice­versa. Capacitors C1 = C22 tied from pins 1 and 22 to VSS. 2. This graph is accurate for C1 = C22 100 pF. 3. When the error detection circuitry in not used, pins 1 and 22 are left open.

5.0

7.0

9.0 11 VDD (Vdc)

13

15

17

MC14534B 6

MOTOROLA CMOS LOGIC DATA

APPLICATIONS INFORMATION
VDD En CLOCK C MC14534B 1/2 MC14518B Q4 CLOCK A Cout* MC14534B CLOCK A

* Carry Out is high for a single clock period when all five BCD stages go to zero. (Carry Out also goes high when MR is applied.)

Figure 1. Cascade Operation

CLOCK

CLOCK A MC14534B SC DS1 DS2 DS3 DS4 DS5

Q0 Q1 Q2 Q3 BCD FOR SELECTED STAGE

When the Q outputs of a given stage are required, this configuration will lock up the selected stage within four clock cycles. The select line feedback may be hardwired or switched.

Figure 2. Forcing a BCD Stage to the Q Outputs

PIN ASSIGNMENT
Cext MR Eout CLOCK A MODE A MODE B DS1 DS2 SR SC DS5 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD CLOCK B Cext 3­ST BCD Q0 Q1 Q2 Q3 DS4 3­ST DIG DS3 Cout

MOTOROLA CMOS LOGIC DATA

MC14534B 7

OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 623­05 ISSUE M
24 13 NOTES: 1. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION (WHEN FORMED PARALLEL). DIM A B C D F G J K L M N MILLIMETERS MIN MAX 31.24 32.77 12.70 15.49 4.06 5.59 0.41 0.51 1.27 1.52 2.54 BSC 0.20 0.30 3.18 4.06 15.24 BSC 0_ 15 _ 0.51 1.27 INCHES MIN MAX 1.230 1.290 0.500 0.610 0.160 0.220 0.016 0.020 0.050 0.060 0.100 BSC 0.008 0.012 0.125 0.160 0.600 BSC 0_ 15_ 0.020 0.050

B
1 12

A
SEATING PLANE

F

C

L G D N K M J

P SUFFIX PLASTIC DIP PACKAGE CASE 709­02 ISSUE C
24 13 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 31.37 32.13 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.03 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 1.235 1.265 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.080 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040

B
1 12

A N K H G F D
SEATING PLANE

C

L

M

J

MC14534B 8

MOTOROLA CMOS LOGIC DATA

OUTLINE DIMENSIONS
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E­04 ISSUE E
­A­
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029

­B­

12X

P 0.010 (0.25)
M

B

M

1

12

24X

D 0.010 (0.25)
M

J T A
S

B

S

F R C ­T­
SEATING PLANE X 45 _

M
22X

G

K

DIM A B C D F G J K M P R

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MOTOROLA CMOS LOGIC DATA

*MC14534B/D*

MC14534B MC14534B/D 9