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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA
MC14561B 9's Complementer
The MC14561B 9's complementer is a companion to the MC14560B NBCD adder to allow BCD subtraction. A BCD number (8񪣂1 code) is applied to the inputs (A1 = 20, A2 = 21, A3 = 22, A4 = 23). If the complement control (Comp) is low, the BCD number appears at the outputs unmodified. The complement disable (Comp) allows the complement control to be gated, or an inverted control signal to be used. If the complement input is high and the disable input low, the 9's complement of the number is displayed at the outputs. The zero control (Z), when high, forces the outputs low regardless of the state of the other inputs. When the MC14561B is used to perform BCD subtraction in conjunction with the MC14560B NBCD adder, the complement control becomes an add/subtract control. All Inputs Buffered Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low璓ower TTL Loads or One Low璓ower Schottky TTL Load Over the Rated Temperature Range MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage MC14XXXBCP MC14XXXBCL MC14XXXBD L SUFFIX CERAMIC CASE 632

P SUFFIX PLASTIC CASE 646

D SUFFIX SOIC CASE 751A

ORDERING INFORMATION
Plastic Ceramic SOIC

挝挝挝挝挝挝挝挝挝挝 挝挝挝挝挝挝挝挝挝挝 挝挝挝挝挝挝挝挝挝挝 挝挝挝挝挝挝挝挝挝挝
Value Unit V V 0.5 to + 18.0 Vin, Vout Iin, Iout PD Tstg TL Input or Output Voltage (DC or Transient) 0.5 to VDD + 0.5 10 500 65 to + 150 260 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Lead Temperature (8璖econd Soldering) mA mW

TA = 55 to 125癈 for all packages.

PIN ASSIGNMENT
A1 A2 A3 A4 COMP COMP VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD F1 F2 F3 F4 Z NC

_C _C

* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: 12 mW/_C From 100_C To 125_C

NC = NO CONNECTION

TRUTH TABLE
Z 0 0 0 0 1 Comp 0 0 1 1 X Comp 0 1 1 0 X A1 0 A2 0 A2A3 + A2A3 0 A2A3A4 0 Complement Zero A1 A2 A3 A4 Straight璽hrough F1 F2 F3 F4 Mode

X = Don't Care.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high璱mpedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

v

v

REV 3 1/94

㎝OTOROLA CMOS LOGIC DATA Motorola, Inc. 1995

MC14561B 1

挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝 挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝 挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝 挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 3.0 0.64 1.6 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 2.4 0.51 1.3 3.4 0.51 1.3 3.4 -- -- -- -- -- 4.2 0.88 2.25 8.8 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 1.7 0.36 0.9 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD 礎dc pF 礎dc IT IT = (1.5 礎/kHz) f + IDD IT = (3.0 礎/kHz) f + IDD IT = (4.5 礎/kHz) f + IDD 礎dc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL 50) Vfk where: IT is in 礎 (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.004.

MC14561B 2

MOTOROLA CMOS LOGIC DATA

挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝 挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝 挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝 挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝挝
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time tPLH, tPHL = (1.7 ns/pF) CL + 315 ns tPLH, tPHL = (0.66 ns/pF) CL + 127 ns tPLH, tPHL = (0.5 ns/pF) CL + 95 ns Symbol tTLH, tTHL VDD 5.0 10 15 5.0 10 15 Min -- -- -- -- -- -- Typ # 100 50 40 400 160 120 Max 200 100 80 Unit ns tPLH, tPHL ns 1000 400 300 * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 20 ns ANY INPUT 90% 50% 10% tPLH 90% ANY OUTPUT 10% tPHL VOH 50% VOL tTLH tTHL 20 ns VDD VSS

Figure 1. Switching Time Waveforms

MOTOROLA CMOS LOGIC DATA

MC14561B 3

LOGIC DIAGRAM
A1 1

F1 13

A2 2

F2 12

F3 11 A3 3 F4 10 A4 4 COMP 5 COMP 6 Z 9 VDD = PIN 14 VSS = PIN 7

TRUTH TABLE COMPLEMENT MODE (Z = 0, Comp = 1, Comp = 0)
Decimal Equivalent Input 0 1 2 3 4 5 6 7 8 9 Illegal BCD Input Codes 10 11 12 13 14 15 Inputs A4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Decimal Equivalent Output 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 Outputs F4 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F3 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 F2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 F1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

MC14561B 4

MOTOROLA CMOS LOGIC DATA

TYPICAL APPLICATIONS
One MC14560B and one MC14561B permit a BCD digit to be added to or subtracted from a second digit, such as in the typical configurations in Figures 2 and 3. A second MC14561B permits either digit to be added to or subtracted from the other, or either word to appear unmodified at the output.

ADD/SUBTRACT MC14561B A1 A1 A2 A3 A4 COMP COMP ZERO Z F4 F3 F2 Cin A1 A2 A3 A4 B1 B2 B1 B3 Cout MC14561B A1 A10 A2 A3 A4 COMP COMP Z F4 F3 F2 Cin A1 A2 A3 A4 B1 B2 B10 B3 B4 Cout S3 S4 S1 S2 TENS F1 MC14560B S3 S4 S1 S2 UNITS F1 MC14560B

TRUTH TABLE
Zero 0 0 1 X = Don't Care Add/Subtract 0 1 X Result B plus A B minus A B

Figure 2. Parallel Add/Subtract Circuit (10's Complement)

MOTOROLA CMOS LOGIC DATA

MC14561B 5

TYPE D FLIP璅LOP D C ADD/SUBTRACT A REGISTER MC14561B A1 A2 A3 A4 COMP COMP Z F1 F2 F3 F4 MC14560B Cin A1 A2 A3 A4 B1 B2 B3 B4 S1 S2 RESULT S3 S4 Cout Q

100's

10's

1's

CLOCK 100's 10's 1's

B REGISTER

Figure 3. Serial Add/Subtract Circuit

MC14561B 6

MOTOROLA CMOS LOGIC DATA

OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 63208 ISSUE Y
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 6.23 7.11 3.94 5.08 0.39 0.50 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15_ 0.51 1.01


14 9


1 7

C

L


SEATING PLANE

K F D
14 PL

G 0.25 (0.010)
M

N J T A
S 14 PL

M 0.25 (0.010)
M

T B

S

DIM A B C D F G J K L M N

P SUFFIX PLASTIC DIP PACKAGE CASE 64606 ISSUE L
14 8

B
1 7

NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01

A F C N H G D
SEATING PLANE

L

J K M

MOTOROLA CMOS LOGIC DATA

MC14561B 7

OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A03 ISSUE F

14 8


1 7

P 7 PL 0.25 (0.010)
M

B

M

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

G C

R X 45 _

F


SEATING PLANE

D 14 PL 0.25 (0.010)
M

K T B
S

M A
S

J

DIM A B C D F G J K M P R

MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50

INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019

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MC14561B 8



*MC14561B/D*

MOTOROLA CMOS LOGIC DATA MC14561B/D