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Dual 4-Bit Binary/BCD
Down Counter
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MC14569B Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter
The MC14569B is a programmable dividebyN dual 4bit binary or BCD down counter constructed with MOS Pchannel and Nchannel enhancement mode devices (complementary MOS) in a monolithic structure. This device has been designed for use with the MC14568B phase comparator/counter in frequency synthesizers, phaselocked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity.
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MARKING DIAGRAMS
16 PDIP16 P SUFFIX CASE 648 MC14569BCP AWLYYWW 1 16 TSSOP16 DT SUFFIX CASE 948F 1 16 14 569B ALYW
· Speedup Circuitry for Zero Detection · Each 4Bit Counter Can Divide Independently in BCD or Binary · · ·
Mode Can be Cascaded With MC14526B for Frequency Synthesizer Applications All Outputs are Buffered Schmitt Triggered Clock Conditioning
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8Second Soldering) Value 0.5 to +18.0 0.5 to VDD + 0.5 ±10 500 55 to +125 65 to +150 260 Unit V V
SOIC16 DW SUFFIX CASE 751G 1
14569B
AWLYYWW
mA mW °C °C °C
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device MC14569BCP MC14569BDT MC14569BDW MC14569BDWR2 Package PDIP16 TSSOP16 SOIC16 SOIC16 Shipping 2000/Box 96/Rail 47/Rail 1000/Tape & Reel
1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2000
1
August, 2000 Rev. 4
Publication Order Number: MC14569B/D
MC14569B
PIN ASSIGNMENT
ZERO DETECT CTL1 P0 P1 P2 P3 CASCADE FEEDBACK VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q P7 P6 P5 P4 CTL2 CLOCK
BLOCK DIAGRAM
P0 P1 P2 P3 CTL = Low for Binary Count CTL = High for BCD Count 3 4 5 6 CTL1 CTL2 2 10 P4 P5 P6 P7 11 12 13 14 VDD = PIN 16 VSS = PIN 8 15 Q
CLOCK
9
BINARY/BCD COUNTER #1
CLOCK LOAD
BINARY/BCD COUNTER #2
CASCADE 7 FEEDBACK
ZERO DETECT ENCODER
1 ZERO DETECT
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MC14569B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 Min -- -- -- 55_C 25_C 125_C Max Min -- -- -- Typ (3.) 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 Vin = 0 or VDD "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- ±0.1 -- 5.0 10 20 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- ±0.1 7.5 5.0 10 20 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- ±1.0 -- 150 300 600 mAdc Vdc "1" Level VOH 4.95 9.95 14.95 -- -- -- 3.5 7.0 11 3.0 0.64 1.6 4.2 0.64 1.6 4.2 -- -- -- -- -- 4.95 9.95 14.95 -- -- -- 3.5 7.0 11 2.4 0.51 1.3 3.4 0.51 1.3 3.4 -- -- -- -- -- 5.0 10 15 2.25 4.50 6.75 2.75 5.50 8.25 4.2 0.88 2.25 8.8 0.88 2.25 8.8 ±0.00001 5.0 0.005 0.010 0.015 4.95 9.95 14.95 -- -- -- 3.5 7.0 11 1.7 0.36 0.9 2.4 0.36 0.9 2.4 -- -- -- -- -- Vdc Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) "1" Level (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current (4.) (5.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Source VIL Vdc IOH mAdc Sink Iin Cin IDD µAdc pF µAdc IT IT = (0.58 µA/kHz) f + IDD IT = (1.20 µA/kHz) f + IDD IT = (1.95 µA/kHz) f + IDD µAdc 3. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 4. The formulas given are for the typical characteristics only at 25_C. 5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001.
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MC14569B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol tTLH VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 tPHL 5.0 10 15 5.0 10 15 tWH 5.0 10 15 5.0 10 15 5.0 10 15 -- -- -- -- -- -- 300 150 115 -- -- -- 380 150 100 530 225 155 100 45 30 3.5 9.5 13.0 NO LIMIT 600 300 200 1000 400 300 -- -- -- 2.1 5.1 7.8 ns All Types Typ (6.) 100 50 40 100 50 40 420 175 125 675 285 200 Min -- -- -- -- -- -- -- -- -- -- -- -- Max 200 100 80 200 100 80 700 300 250 1200 500 400 ns Unit ns Output Rise Time Output Fall Time tTHL ns TurnOn Delay Time Zero Detect Output tPLH ns Q Output TurnOff Delay Time Zero Detect Output ns Q Output Clock Pulse Width ns Clock Pulse Frequency fcl MHz Clock Pulse Rise and Fall Time tTLH, tTHL µs 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
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MC14569B
SWITCHING WAVEFORMS
20 ns 20 ns CLOCK 10% 90% 50% tWH tPLH tPHL fin = fmax
Q
10%
90% 50% tTLH tTHL
Figure 1.
20 ns 20 ns CLOCK 10% 90% 50% tWH tPLH 90% ZERO DETECT tTLH 10% tTHL tPHL
Figure 2.
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MC14569B
PIN DESCRIPTIONS
INPUTS CONTROLS
P0, P1, P2, P3 (Pins 3, 4, 5, 6) -- Preset Inputs. Programmable inputs for the least significant counter. May be binary or BCD depending on the control input. P4, P5, P6, P7 (Pins 11, 12, 13, 14) -- Preset Inputs. Programmable inputs for the most significant counter. May be binary or BCD depending on the control input. Clock (Pin 9) -- Preset data is decremented by one on each positive transition of this signal.
OUTPUTS
Cascade Feedback (Pin 7) -- This pin is normally set high. When low, loading of the preset inputs (P0 through P7) is inhibited, i.e., P0 through P7 are "don't cares." Refer to Table 1 for output characteristics. CTL1 (Pin 2) -- This pin controls the counting mode of the least significant counter. When set high, counting mode is BCD. When set low, counting mode is binary. CTL2 (Pin 10) -- This pin controls the counting mode of the most significant counter. When set high, counting mode is BCD. When set low, counting mode is binary.
SUPPLY PINS
Zero Detect (Pin 1) -- This output is normally low and goes high for one clock cycle when the counter has decremented to zero. Q (Pin 15) -- Output of the last stage of the most significant counter. This output will be inactive unless the preset input P7 has been set high.
VSS (Pin 18) -- Negative Supply Voltage. This pin is usually connected to ground. VDD (Pin 16) -- Positive Supply Voltage. This pin is connected to a positive supply voltage ranging from 3.0 volts to 18.0 volts.
OPERATING CHARACTERISTICS The MC14569B is a programmable dividebyN dual 4bit down counter. This counter may be programmed (i.e., preset) in BCD or binary code through inputs P0 to P7. For each counter, the counting sequence may be chosen independently by applying a high (for BCD count) or a low (for binary count) to the control inputs CTL1 and CTL2. The divide ratio N (N being the value programmed on the preset inputs P0 to P7) is automatically loaded into the counter as soon as the count 1 is detected. Therefore, a division ratio of one is not possible. After N clock cycles, one pulse appears on the Zero Detect output. (See Timing Diagram.) The Q output is the output of the last stage of the most significant counter (See Tables 1 through 5, Mode Controls.) When cascading the MC14569B to the MC14526B, the Cascade Feedback input, Q, and Zero Detect outputs must be respectively connected to "0", Clock, and Load of the following counter. If the MC14569B is used alone, Cascade Feedback must be connected to VDD.
18 16 f, FREQUENCY (MHz), TYPICAL 14 12 10 8.0 6.0 4.0 2.0 0 -40 -20 0 +20 +40 +60 TA, AMBIENT TEMPERATURE (°C)
CL = 50 pF
VDD = 15 V
10 V
5.0 V
+80
+100
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MC14569B
Table 1. Mode Controls (Cascade Feedback = Low)
Counter Control Values CTL1 0 0 1 1 CTL2 0 1 0 1 Divide Ratio Zero Detect 256 160 160 100 Q 256 160 160 100
NOTE: Data Preset Inputs (P0P7) are "Don't Cares" while Cascade Feedback is Low.
Table 2. Mode Controls (CTL1 = Low, CTL2 = Low, Cascade Feedback = High)
Preset Inputs P7 0 0 0 0
Divide Ratio P2 0 0 0 0
P6 0 0 0 0
P5 0 0 0 0
P4 0 0 0 0
P3 0 0 0 0
P1 0 0 1 1
P0 0 1 0 1
Zero Detect 256 X 2 3
Q 256 X X X X X X X X X X X X X X X X X X X X 128
Comments Max Count Illegal State Min Count
0 0
0 0
0 0
0 1
1 0
1 0
1 0
1 0
15 16
0
0
1
0
0
0
0
0
32
0
1
0
0
0
0
0
0
64
0 1
1 0
1 0
1 0
1 0
1 0
1 0
1 0
127 128
Q Output Active
1
0
0
0
1
0
0
0
136
136
1 27 128
1 26 64
1 25 32
1 24 16
1 23 8
1 22 4
1 21 2
1 20 1
255
255 Bit Value Counting Sequence
Counter #2 Binary X = No Output (Always Low)
Counter #1 Binary
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MC14569B
Table 3. Mode Controls (CTL1 = High, CTL2 = Low, Cascade Feedback = High)
Preset Inputs P7 0 0 0 0
Divide Ratio P2 0 0 0 0
P6 0 0 0 0
P5 0 0 0 0
P4 0 0 0 0
P3 0 0 0 0
P1 0 0 1 1
P0 0 1 0 1
Zero Detect 160 X 2 3
Q 160 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 80
Comments Max Count Illegal State Min Count
0 0
0 0
0 0
0 1
1 0
0 0
0 0
1 0
9 10
0 0
0 0
0 1
1 0
1 0
0 0
0 0
1 0
19 20
0
0
1
1
0
0
0
0
30
0
1
0
0
0
0
0
0
40
0
1
0
1
0
0
0
0
50
0
1
1
0
0
0
0
0
60
0
1
1
1
0
0
0
0
70
1
0
0
0
0
0
0
0
80
Q Output Active
1
0
0
1
0
0
0
0
90
90
1
1
1
1
0
0
0
0
150
150
1 80
1 40
1 20
1 10
1 8
0 4
0 2
1 1
159
159 Bit Value Counting Sequence
Counter #2 Binary X = No Output (Always Low)
Counter #1 BCD
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MC14569B
Table 4. Mode Controls (CTL1 = Low, CTL2 = High, Cascade Feedback = High)
Preset Values P7 0 0 0 0
Divide Ratio P2 0 0 0 0
P6 0 0 0 0
P5 0 0 0 0
P4 0 0 0 0
P3 0 0 0 0
P1 0 0 1 1
P0 0 1 0 1
Zero Detect 160 X 2 3
Q 160 X X X X X X X X X X X X X X X X X
Comments Max Count Illegal State Min Count
0 0
0 0
0 0
0 1
1 0
1 0
1 0
1 0
15 16
0 0
0 0
0 1
1 0
1 0
1 0
1 0
1 0
31 32
0
0
1
1
0
0
0
0
48
0
1
0
0
0
0
0
0
64
X
0
1
0
1
0
0
0
0
80
X
0
1
1
1
0
0
0
0
112
X
1
0
0
0
0
0
0
0
128
128
Q Output Active
1
0
0
1
0
0
0
0
144
144
1 27 128
0 26 64
0 25 32
1 24 16
1 23 8
1 22 4
1 21 2
1 20 1
159
159 Bit Value Counting Sequence
Counter #2 BCD X = No Output (Always Low)
Counter #1 Binary
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MC14569B
Table 5. Mode Controls (CTL1 = High, CTL2 = High, Cascade Feedback = High)
Preset Values P7 0 0 0 0
Divide Ratio P2 0 0 0 0
P6 0 0 0 0
P5 0 0 0 0
P4 0 0 0 0
P3 0 0 0 0
P1 0 0 1 1
P0 0 1 0 1
Zero Detect 100 X 2 3
Q 100 X X X X X X X X X X X X X X X X X X X X X X X X X X X 80
Comments Max Count illegal state Min Count
0 0
0 0
0 0
0 1
1 0
0 0
0 0
1 0
9 10
0
0
1
1
0
0
0
0
30
0
1
0
0
0
0
0
0
40
0
1
0
1
0
0
0
0
50
0
1
1
1
0
0
0
0
70
1
0
0
0
0
0
0
0
80
Q Output Active
1
0
0
1
0
0
0
0
90
90
1 80
0 40
0 20
1 10
1 8
0 4
0 2
1 1
99
99 Bit Value Counting Sequence
Counter #2 BCD X = No Output (Always Low)
Counter #1 BCD
TIMING DIAGRAM MC14569B
CLOCK DIVIDE BY 2 ZERO DETECT OUTPUT DIVIDE BY 3 DIVIDE BY 4 DIVIDE BY 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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MC14569B
2
LOGIC DIAGRAM
DP Q D DP Q D DP Q D PE C
CTL1
P0
3
PE C
P1
4
PE C
DP Q P2 5 D DP Q P3 6 D DP Q D DP Q D DP Q D IU VDD CASCADE 7 FEEDBACK VDD
PE C PE C PE C PE C
PE C
CLOCK
9 1 ZERO DETECT
P4
11
DP D Q
C PE
P5
12
DP D Q
C PE
P6
13
DP D Q
C PE
P7 CTL2
14 10
DP D Q
C PE 15
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MC14569B
TYPICAL APPLICATIONS
fin
C
CF MC14569B
Q
C PE
ZERO DETECT
CF MC14522B OR MC14526B
Q4 0"
C PE
CF MC14522B OR MC14526B
Q4 0"
Q1/C2 MC14568B PE 0"
DP0 - - - - - - DP3 LSD
DP0 - - - - - - DP3
DP0 - - - - - - DP3 MSD fout
Figure 3. Cascading MC14568B and MC14522B or MC14526B with MC14569B
(40 kHz) VSS
PCin C1 CT1 0" PE
PCout G F Q1/C2
VCO VSS VSS
fout (144 - 146 MHz)
DP0 - - - - DP3 CF MC14569B ZERO DETECT C
VDD MC14011 Q
MIXER 2k 2M Frequencies shown in parenthesis are given as an example
CRYSTAL OSCILLATOR (143.5 MHz)
Figure 4. Frequency Synthesizer with MC14568B and MC14569B Using a Mixer (Channel Spacing 10 kHz)
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MC14569B
PACKAGE DIMENSIONS
A
16 9
PDIP16 P SUFFIX PLASTIC DIP PACKAGE CASE 64808 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
T H G D
16 PL
SEATING PLANE
K
J T A
M
M
0.25 (0.010)
M
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MC14569B
PACKAGE DIMENSIONS
TSSOP16 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
T U
S
V
S
K K1
16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
2X
L/2
J1 B U
L
PIN 1 IDENT. 1 8
SECTION NN J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A V N F DETAIL E
C 0.10 (0.004) T SEATING
PLANE
H D G
DETAIL E
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ÇÇÇ ÉÉ ÇÇÇ ÉÉ
9
W
MC14569B
PACKAGE DIMENSIONS
SOIC16 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G03 ISSUE B
D
16 M 9
A
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
B
1 16X
8
B T A
S
B B
S
0.25
M
A
h X 45 _
SEATING PLANE
M
8X
0.25
E
A1
14X
e
T
C
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L
MC14569B
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MC14569B/D