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IC INFORMATION TC90A64AF
J
Function Two pictures control 1/1 E
Type CMOS Model AVH-P6400CD/UC
Nagative ACK Out
Digital VDD(2.5V)
Buffer VDD(3.3V)
Digital Vss
Buffer Vss
Test 30
Test 29
Test 28
Test 27
Test 26
Test 25
Test 24
Test 23
Test 22
Test 21
Test 20
Test 19
Test 18
Test 17
Test 16
Test 15
Test 14
Test 13
Test 12
Test 11
Test 10
Test 9
Test 8
Test 7
Test 6
Test 5
Test 4
Test 3
Test 2
Test 1
Test 0
144 143 1 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 1 109
42 10
Vss VDD VDD Vss
DRAM Vss 1 Vss Vss 108 DRAM Vss
Gate Scan Start 1 2 NGOE 107 Test mode3
Gate Scan Start 2 3 STV1 106 Test mode2
Gate Clock Out 4 STV2 105 Dispaly Mute
Gate Enable Out 5 CPV 104 Reset IN
DRAM VDD (DR.2.5V) 6 VDD Control ACK VDD 103 DRAM VDD(DR.2.5V)
Signal Polality Out 7 POLS NDSV 102 OSD H.Sync Out
H.Sampling Clock 8 CPH SCKE 101 OSD Clock Out
Output Signal Clamp Pulse 9 CLMPO NDSH 100 OSD V.Sync Out
Digtal Vss 10 Vss 99 Bus Data I/O
VCO Monitor Bus
VCO Moniter 11 VCOM VDD 98 Digital VDD(2.5V)
Inter
Digital VDD(2.5V) 12 VDD STH1 Face 97 Test mode1
H.Sampling Latch Select 13 STH2 96 Bus Serial Clock IN
2M
H.Sampling Start1 14 CX Memory 95 Test mode0
FNAVI
H.Sampling Start2 15 Vss 94 Digital Vss
R
Digital VSS 16 Vss OSD
Side
93 RGB Over lay Cont.IN
Output RGB PIP
D.RAM Test 17 G 92 OSD Blank IN
HD1
OSD OSD
H.Sync IN 18 Switch Matrix Process 91 OSD B IN
VD1 B Color
V.Sync IN 19 Inter 90 OSD G IN
C.Sync1 Palette Face
RGB 2 C.V.Sync IN 20 C.Video 89 OSD R IN
Cont./Bright
Ext.PLL Clock 21 CKP 88 C.Video Sync IN
C.Sync2
HREF
Ext.PLL H.ref. 22 Y U V 87 C.Video Signal IN1 Cl amp Out1
Ext.PLL Select 23 CKPSEL Cont./Bright 86 C.Video Signal IN2 Cl amp Out1
Process Color
Buffer VDD(3.3V) 24 VDD Decode VDD 85 Digital VDD(2.5V)
Buffer Vss 25 Vss Signal C.Video C VDD 84 Buffer VDD(3.5V)
Polarity Side
Sub Timing XO
Analog Vss 26 Vss
NTSC:2line Pulse Gene 42 M 83 X'tal IN
POLC Y/C Sep
D/A Bias 1 27 RGB 82 X'tal OUT
Side PAL:LPF/BPF
Common Polality Out 28 D/A HD2 8bit
HD2
Digtal Vss 81 Buffer Vss
Analog VDD(2.5V) 29 VDD VD2 Main Timing A/D A/D A/D
VD2 PLL Vss 80 Sub PLL Digital Vss
Pulse Gene H/V Sep
Ext.Clamp Bias Out 30 D/A A/D 8bit Vss 79 Sub PLL Analog Vss
Ped.Clamp(63.5LSB) 1/ 2 D/A
D/A Bias Out 31 REFO 1 / 3050 R G B AGS 78 A.G.S.2
Mute 13. 5 M
H/V Sep 1 / 3048 VCO
Analog Vss 32 Vss 1/ 2 77 Sub PLL Filter
27M 54M
10bit 1/ 2 4. 8 M
Analog VDD(2.5V) 33 VDD VDD 76 Sub PLL Analog VDD(2.5V)
D/A 1/ 4 PC1,CP1
Red PD1/PD2 1/ 5 9. 6 M Ped.Clamp(8LSB)
R Signal Out 34 CP1/CP2
VDD 75 Sub PLL Digital VDD(2.5V)
Green 1/ 6 8. 0 M Ped.Clamp(8LSB)
D/A Bias 3 35 D/A x 4 Li m 74 Sub PLL IN
Analog Analog
G Signal Out 36 PLL VCO PLL VDD 73 CK D/A Analog VDD(2.5V)
D/A 48M
Blue
VDD Vss VDD VDD AGS1 Vss VDD Vss VDD VDD Vss Vss
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Clock D/A Vref.
PLL Digital VDD(2.5V)
PLL Analog VDD(2.5V)
R IN1
GIN1
B IN1
R IN2
GIN2
B IN2
D/A Bias.4
Analog VDD(2.5V)
Analog Vss
Analog Vss
Analog VDD(2.5V)
Analog Vss
Analog VDD(2.5V)
Analog VDD(2.5V)
A/D Bais.6
Clock D/A Bias
Analog Vss
C.Video Signal IN2
C.Video Signal IN1
PLL Analog Vss
PLL Digital Vss
B.Signal Out
Vref.IN
Main A/D Verf.High
A/D Bais.5
A/D Vref.High
CK D/A Analog Vss
H.PLL Filter Out
H.PLL Filter IN
A.G.S.1
Main A/D Verf.Low
A/D Verf.Low
Clock D/A Out
2002.4