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SCHEMATIC DIAGRAM-5
: +B SIGNAL LINE : PLAYBACK SIGNAL LINE : FM/AM SIGNAL LINE
MAIN CIRCUIT : RECORD SIGNAL LINE : CD SIGNAL LINE
IC800
C1BB00000757
ASP IC
(1A) TUN_RCH
A C207 C302
R201 16V10 50V2.2
CE C202
B TNR_RCH 6.8K 50V2.2 1 VIN1 DS2 24
C407 C210
TUN_LCH 16V10
C R202 C201 1000P
2 VIN2 INF1 23
18K 220P
PLLDA C410
D 1000P
3 SEL2OUT INF2 22
TO DO/ST R401 R402 C401
MAIN (TUNER) E
6.8K 18K 220P C402
TNR_LCH 50V2.2 4 SEL1OUT BNF2 21
CIRCUIT F
PLLCLK
(1B) ON C204
TNR_GND CD_LCH 50V2.2 5 A1IN BOUT2 20
SCHEMATIC G
DIAGRAM-4 TNR_15V
R203 R204 C203
H 2.7K 6.8K 220P 6 A2IN BNF1 19
DO/ST IC800
I 7 B1IN BOUT1 18
R403 R404 C403
SD 2.7K 6.8K 220P C404
J CD_RCH 50V2.2 C213 50V0.47
8 B2IN OUT1 17
K TNR_7.5V C206
PB_LCH 50V2.2 C413 50V0.47
DET 9 C1IN OUT2 16
L
R206 C205
10K 220P 10 C2IN VCC 15
C301
REC_RIN REC_RCH 25V47 11 FILTER S1 14
1 R406 C405
10K 220P C406
REC_LIN REC_LCH PB_RCH 50V2.2
2 12 GND SC 13
AFGND
3
TO 4
PB_ROUT PB_RCH
R409 R209 C304 R303
DECK CIRCUIT PB_LOUT PB_LCH 18K 18K C209 47P 6.8K
(CN1304) ON 5 1000P
SCHEMATIC 6
9VGND C305
R302
DIAGRAM-10 47P 6.8K
R210
9V(D9V) A9V
7 REC_LCH 1K
MOTOR_9V
8
C409
MOTOR_GND 1000P D301 D302
9 REC_RCH
B0AACK000004 B0AACK000004
WH800
SP_DATA
R410
SP_CLK
CD_7.5V
1K
D5V
CD_RCH
CD_LCH
L802
J0JKB0000020
IC802
S81333HG-Z
CD_L C831 REGULATOR
19
1000P
A_GND
18 2 1 3
CD_R C830
17 1000P D5V
CD_3.3V L803 J0JKB0000020
16
LD_SW/CLDCK C816 C815
C828 16V22 50V1
15 1000P
D_GND
14
100K
100K
CD_7.5V
220P
220P
10K
10K
10K
13
LOADING
MDATA
SUBQ
BLKCK
MCLK
MLD
SQCK
D5V
CD_OPEN_SW
REST_SW
CD_RST
STAT
12 TX
TO PWR_GND
R830
R829
R827
R824
R822
C821
C820
11 D802 R821 Q805
CD SERVO MA2C700A0F 100
CIRCUIT 10 MCLK KRC101MTA
BLKCLK INTERFACE
(CN702) ON 9
MDATA R820 100
SCHEMATIC R813 4.7K
MLD D801 R823 4.7K Q805
DIAGRAM-2 8
MA2C700A0F
R812 4.7K
BLKCK R816 10K R811 4.7K
7
SQCK R814 10K
6 R815 4.7K C819
100P R810 10K
SUBQ R819 10K
5
STATUS R818 10K
4
RST R817 4.7K
Q804
3
REST_SW
2 Q804
1
LOADING C818
100P
KRC101MTA
SUBQ INTERFACE
5.6K
CN801
100P
100P
R826
18K Q803
C832 C822
R825
0.01 100P
C824
C823
Q803
C817
KRC101MTA
100P STATUS INTERFACE
L=OPEN CP800
H=CLOSE
1 1
CD
OPEN 2 2
SW
SCHEMATIC DIAGRAM-6
: +B SIGNAL LINE : MAIN SIGNAL LINE
MAIN CIRCUIT
TNR_7.5V
C411 R412 1
0.22 3.9K
TNR_15V
2
R411 TNR_GND
390K C412 R214 3
0.22 8.2K
R212 LCH
3.9K 4 TO
C211 0.22 R213 5 SPEAKER TERMINAL
C214
R211 12K 1800P RCH
CIRCUIT (CN802B)
390K R414 8.2K
C212 0.22
6 ON SCHEMATIC
R413
A9V
7
DIAGRAM-11
C414
12K 1800P
R216 R416 Q802 8
6.8K 6.8K MOTOR_GND
R415 9
R215
3.9K 3.9K MOTOR_9V
10
C215 C415 CN802A
0.027 0.027
______
/MUTEA
R301 Q802
33 KRC102MTA
MUTING CONTROL A9V
C303
25V47
RDS_CLK
C814 R807 L801
100P 1K 100