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Semiconductor

ICL7129
41/2 Digit LCD, Single-Chip A/D Converter
Description
The Harris ICL7129 is a very high performance 41/2-digit, analog-to-digital converter that directly drives a multiplexed liquid crystal display. This single chip CMOS integrated circuit requires only a few passive components and a reference to operate. It is ideal for high resolution hand-held digital multimeter applications. The performance of the ICL7129 has not been equaled before in a single chip A/D converter. The successive integration technique used in the ICL7129 results in accuracy better than 0.005% of full scale and resolution down to 10V/count. The ICL7129, drawing only 1mA from a 9V battery, is well suited for battery powered instruments. Provision has been made for the detection and indication of a "LOW/BATTERY" condition. Autoranging instruments can be made with the ICL7129 which provides overrange and underrange outputs and 10:1 range changing input. The ICL7129 instantly checks for continuity, giving both a visual indication and a logic level output which can enable an external audible transducer. These features and the high performance of the ICL7129 make it an extremely versatile and accurate instrument-on-a-chip.

August 1997

Features
19,999 Count A/D Converter Accurate to 4 Count 10V Resolution on 200mV Scale 110dB CMRR Direct LCD Display Drive True Differential Input and Reference Low Power Consumption Decimal Point Drive Outputs Overrange and Underrange Outputs Low Battery Detection and Indication 10:1 Range Change Input

Ordering Information
PART NUMBER ICL7129CPL ICL7129RCPL ICL7129CM44 TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 PACKAGE 40 Ld PDIP 40 Ld PDIP 44 Ld MQFP PKG. NO. E40.6 E40.6 Q44.10x10

NOTE: "R" indicates device with reversed leads.

Pinouts
ICL7129 (PDIP) TOP VIEW
OSC1 1 OSC3 2 ANNUNCIATOR 3 DRIVE B1 , C1 , CONT 4 A1 , G1 , D1 5 F1 , E1 , DP1 6 DISPLAY OUTPUT LINES B2 , C2 , LO BAT 7 A2 , G2 , D2 8 F2 , E2 , DP2 9 B3 , C3 , MINUS 10 A3 , G3 , D3 11 F3 , E3 , DP3 12 B4 , C4 , BC5 13 A4 , D4 , G4 14 F4 , E4 , DP4 15 BP3 16 BP2 17 BP1 18 VDISP 19 DP4 /OR 20 40 OSC2 39 DP1 38 DP2 37 RANGE 36 DGND 35 REF LO 34 REF HI 33 IN HI 32 IN LO 31 BUFF 30 CREF29 CREF+ 28 COMMON 27 CONTINUITY 26 INT OUT 25 INT IN 24 V+ 23 V22 LATCH/HOLD B2 , C2 , LO BAT B3 , C3 , MINUS A1 , G1 , D1 F1 , E1 , DP1 A2 , G2 , D2 F2 , E2 , DP2 A3 , G3 , D3 F3 , E3 , DP3 B4 , C4 , BC5 A4 , D4 , G4 21 DP3 /UR F4 , E4 , DP4 DGND RANGE DP2 DP1 OSC 2 OSC 1 OSC 3 NC NC ANNUNCE DRIVE B1 , C1 , CONT 1 44 43 42 41 40 39 38 37 36 35 34 33 2 32 3 4 5 6 7 8 9 31 30 29 28 27 26 25 V+ VNC NC LATCH/ HOLD DP3 /UR DP4 /OR VDISP BP1 BP2 BP3

ICL7129 (MQFP) TOP VIEW
CONTINUITY COMMON INT OUT

REF LO

REF HI

CREF+

CREF-

24 10 11 23 12 13 14 15 16 17 18 19 20 21 22

INT IN

BUFF

IN LO

IN HI

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

Harris Corporation 1997

File Number

3085.1

3-31

ICL7129 Functional Block Diagram
LOW BATTERY CONTINUITY

SEGMENT DRIVES

BACKPLANE DRIVES

ANNUNCIATOR DRIVE

LATCH, DECODE DISPLAY MULTIPLEXER OSC1 VDISP

OSC2

UP/DOWN RESULTS COUNTER

OSC3

SEQUENCE COUNTER/DECODER

CONTROL LOGIC

ANALOG SECTION

RANGE L/H

CONT

V+

V-

DGND

OR DP3

UR DP3

DP2

DP1

Typical Application Schematic
LOW BATTERY CONTINUITY

V+ 5pF (MICA)
20 21 19 22 18 23 17 24 + 16 15 26 14 13 12 11 10 9 8 7 6 5 4 3 2 1

ICL7129

120kHz

9V

25

560pF 10pF (MICA) 1.2k 0.1F 150k 10k 1.0F 0.1F ICL8069
+

27

28

29

30

31

32

33 +

100k

34

35

20K

36

37

38

39

40

270K

V+ 6.8F

-

-

VIN

3-32

ICL7129
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Reference Voltage (REF HI or REF LO). . . . . . . . . . . . . . . . V+ to VInput Voltage (Note 1), IN HI or IN LO . . . . . . . . . . . . . . . . . V+ to VVDISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND -0.3V to V+ Digital Input Pins 1, 2, 19, 20, 21, 22, 27, 37, 38, 39, 40 . . . . . . . . . . . . . DGND to V+

Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES: 1. Input voltages may exceed the supply voltages provided that input current is limited to 1400mA. Currents above this value may result in valid display readings but will not destroy the device if limited to 1mA. 2. JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications
PARAMETER Zero Input Reading Zero Reading Drift Ratiometric Reading Range Change Accuracy Rollover Error Linearity Error

V- to V+ = 9V, VREF = 1.00V, TA = 25oC, fCLK = 120kHz, Unless Otherwise Specified TEST CONDITIONS VIN = 0V, 200mV Scale VIN = 0V, 0oC To 70oC VIN = VREF = 1000mV, RANGE = 2V VIN = 0.10000V on Low, Range VIN = 1.0000V on High Range -VIN = +VIN = 199mV 200mV Scale VCM = 1V,VIN = 0V, 200mV Scale VIN = 0V, 200mV Scale MIN -0000 9996 0.9999 2.8 4.5 6 6.3 100 TYP 0000 0.5 9999 1.0000 1.5 1.0 110 (V-) +1.5 (V+) -1.0 14 1 2 3.2 0.6 10 5.3 1.2 9 1.0 120 50 7.2 200 200 2 3/3 3/9 40 3 MAX +0000 10000 1.0001 3.0 10 7 3.5 5.8 12 1.5 360 7.7 400 10 UNITS Counts V/oC Counts Ratio Counts Counts dB V V pA ppm/oC V mA A V mA V mA kHz k V mV mV A A A A A

Input Common-Mode Rejection Ratio Input Common-Mode Voltage Range

Noise (Peak-To-Peak Value not Exceeded 95% of Time) VIN = 0V 200mV Scale Input Leakage Current Scale Factor Tempco COMMON Voltage COMMON Sink Current COMMON Source Current DGND VoItage DGND Sink Current Supply Voltage Range Supply Current Excluding COMMON Current Clock Frequency VDISP Resistance Low Battery Flag Activation Voltage CONTINUITY Comparator Threshold Voltages VIN = 0V, Pin 32, 33 VIN = 199mV 0oC To 70oC External VREF = 0ppm/oC V+ to Pin 28 Common = + 0.1V Common = -0.1V V+ to Pin 36, V+ to V- = 9V DGND = +0.5V V+ to V- (Note 3) V+ to V- = 9V (Note 3) VDISP to V+ V+ to VVOUT Pin 27 = HI VOUT Pin 27 = LO Pull-Down Current "Weak Output" Current Sink/Source Pins 37, 38, 39 Pins 20, 21 Sink/Source Pin 27 Sink/Source Pin 22 Source Current Pin 22 Sink Current NOTE:

3. Device functionality is guaranteed at the stated Min/Max limits. However, accuracy can degrade under these conditions.

3-33

ICL7129 Pin Descriptions
PIN 1 2 3 SYMBOL OSC1 OSC3 ANNUNCIATOR DRIVE B1 , C1 , CONT A1 , G1 , D1 F1 , E1 , DP1 DESCRIPTION Input to first clock inverter. Output of second clock inverter. Backplane squarewave output for driving annunciators. Output to display segments. Output to display segments. Output to display segments. PIN 23 24 SYMBOL VV+ DESCRIPTION Negative power supply terminal. Positive power supply terminal, and positive rail for display drivers. Input to integrator amplifier. Output of integrator amplifier. INPUT: When LO, continuity flag on the display is off. When HI, continuity flag is on. OUTPUT: HI when voltage between inputs is less than +200mV. LO when voltage between inputs is more than +200mV. 28 COMMON Sets common-mode voltage of 3.2V below V+ for DE, 10X, etc., Can be used as pre-regulator for external reference. Positive side of external reference capacitor. Negative side of external reference capacitor. Output of buffer amplifier. Negative input voltage terminal. Positive input voltage terminal. Positive reference voltage input terminal. Negative reference voltage input terminal. Ground reference for digital section. 3A pull-down for 200mV scale. Pulled HIGH externally for 2V scale. Internal 3A pull-down. When HI, decimal point 2 will be on. Internal 3A pull-down. When HI, decimal point 1 will be on. Output of first clock inverter. Input of second clock inverter.

25 26 27

INT IN INT OUT CONTINUITY

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

B2 , C2 , LO BATT Output to display segments. A2 , G2 , D2 F2 , E2 , DP2 B3 , C3 , MINUS A3 , G3 , D3 F3 , E3 , DP3 B4 , C4 , BC5 A4 , D4 , G4 F4 , E4 , DP4 BP3 BP2 BP1 VDlSP DP4 /OR Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Backplane #3 output to display. Backplane #2 output to display. Backplane #1 output to display. Negative rail for display drivers. INPUT: When HI, turns on most significant decimal point. OUTPUT: Pulled HI when result count exceeds 19,999. 31 32 33 34 BUFFER IN LO IN HI REF HI 29 CREF+

30

CREF-

35

REF LO

36 37

DGND RANGE

21

DP3 /UR

INPUT: Second most significant decimal point on when HI. OUTPUT: Pulled HI when result count is less than 1,000.

38

DP2

39

DP1

22

LATCH/HOLD

INPUT: When floating, A/D converter operates in the free-run mode. When pulled HI, the last displayed reading is held. When pulled LO, the result counter contents are shown incrementing during the de-integrate phase of cycle. OUTPUT: Negative going edge occurs when the data latches are updated. Can be used for converter status signal.

40

OSC2

3-34

ICL7129 Detailed Description
The ICL7129 is a uniquely designed single chip A/D converter. It features a new "successive integration" technique to achieve 10V resolution on a 200mV full-scale range. To achieve this resolution a 10:1 improvement in noise performance over previous monolithic CMOS A/D converters was accomplished. Previous integrating converters used an external capacitor to store an offset correction voltage. This technique worked well but greatly increased the equivalent noise bandwidth of the converter. The ICL7129 removes this source of error (noise) by not using an auto-zero capacitor. Offsets are cancelled using digital techniques instead. Savings in external parts cost are realized as well as improved noise performance and elimination of a source of electromagnetic and electrostatic pick-up. In the overall Functional Block Diagram of the ICL7129 the heart of this A/D converter is the sequence counter/decoder which drives the control logic and keeps track of the many separate phases required for each conversion cycle. The sequence counter is constantly running and is a separate counter from the up/down results counter which is activated only when the integrator is de-integrating. At the end of a conversion the data remaining in the results counter is latched, decoded and multiplexed to the liquid crystal display. The analog section block diagram shown in Figure 1 includes all of the analog switches used to configure the voltage sources and amplifiers in the different phases of the cycle. The input and reference switching schemes are very
CREF REF HI DE REF LO DE X10 INT1 IN HI DEDE+ COMMON INT1 , INT2 IN LO INT REST, INT2 DE+ DE10 COMPARATOR 1 + 100 RINT BUFFER

similar to those in other less accurate integrating A/D converters. There are 5 basic configurations used in the full conversion cycle. Figure 2 illustrates a typical waveform on the integrator output. INT, INT1 , and INT2 all refer to the signal integrate phase where the input voltage is applied to the integrator amplifier via the buffer amplifier. In this phase, the integrator ramps over a fixed period of time in a direction opposite to the polarity of the input voltage. DE1 , DE2 , and DE3 are the de-integrate phases where the reference capacitor is switched in series with the buffer amplifier and the integrator ramps back down to the level it started from before integrating. However, since the de-integrate phase can terminate only at a clock pulse transition, there is always a small overshoot of the integrator past the starting point. The ICL7129 amplifies this overshoot by 10 and DE2 begins. Similarly DE2's overshoot is amplified by 10 and DE3 begins. At the end of DE3 the results counter holds a number with 51/2 digits of resolution. This was obtained by feeding counts into the results counter at the 31/2 digit level during DE1 , into the 41/2 digit level during DE2 and the 51/2 digit level for DE3 . The effects of offset in the buffer, integrator, and comparator can now be cancelled by repeating this entire sequence with the inputs shorted and subtracting the results from the original reading. For this phase INT2 switch is closed to give the same common-mode voltage as the measurement cycle. This assures excellent CMRR. At the end of the cycle the data in the up/down results counter is accurate to 0.02% of full scale and is sent to the display driver for decoding and multiplexing.
CINT INT, IN INT OUT

+ BUFFER Z1, X10

-

+ INTEGRATOR

-

-

+

-

TO DIGITAL SECTION

COMPARATOR 2

FIGURE 1. ANALOG BLOCK DIAGRAM
ZERO-INTEGRATE AND LATCH INT1 INTEGRATE DE1 DE-INTEGRATE REST X10

DE2 REST

X10

DE3 ZERO-INTEGRATE

NOTE: Shaded area greatly expanded in time and amplitude.
1000 CLOCKS 10,000 CLOCKS 2000 CLOCKS

INTEGRATOR RESIDUE VOLTAGE 1000 CLOCKS

FIGURE 2. INTEGRATOR WAVEFORM FOR NEGATIVE INPUT VOLTAGE SHOWING SUCCESSIVE INTEGRATION PHASES AND RESIDUE VOLTAGE

3-35

ICL7129
COMMON, DGND, and "Low Battery" The COMMON and DGND (Digital GrouND) outputs of the ICL7129 are generated from internal zener diodes (Figure 3). COMMON is included primarily to set the common-mode voltage for battery operation or for any system where the input signals float with respect to the power supplies. It also functions as a pre-regulator for an external precision reference voltage source. The voltage between DGND and V+ is the supply voltage for the logic section of the ICL7129 including the display multiplexer and drivers. Both COMMON and DGND are capable of sinking current from external loads, but caution should be taken to ensure that these outputs are not overloaded. Figure 4 shows the connection of external logic circuitry to the ICL7129. This connection will work providing that the supply current requirements of the logic do not exceed the current sink capability of the DGND pin. If more supply current is required, the buffer in Figure 5 can be used to keep the loading on DGND to a minimum. COMMON can source approximately 12mA while DGND has no source capability.
V+ 24 EXTERNAL LOGIC ICL7129 EXTERNAL LOGIC CURRENT

+

36

DGND 23 V-

FIGURE 5. BUFFERED DGND

The "LOW BATTERY" annunciator of the display is turned on when the voltage between V+ and V- drops below 7.2V typically. The exact point at which this occurs is determined by the 6.3V zener diode and the threshold voltage of the N-Channel transistor connected to the V- rail in Figure 3. As the supply voltage decreases, the N-Channel transistor connected to the V-rail eventually turns off and the "LOW BATTERY" input to the logic section is pulled HIGH, turning on the "LOW BATTERY" annunciator. I/O Ports Four pins of the ICL7129 can be used as either inputs or outputs. The specific pin numbers and functions are described in the Pin Description table. If the output function of the pin is not desired in an application it can easily be overridden by connecting the pin to V+ (HI) or DGND (LO). This connection will not damage the device because the output impedance of these pins is quite high. A simplified schematic of these input/output pins is shown in Figure 6. Since there is approximately 500k in series with the output driver, the pin (when used as an output) can only drive very light loads such as 4000 series, 74CXX type CMOS logic, or other high input impedance devices. The output drive capability of these four pins is limited to 3A, nominally, and the input switching threshold is typically DGND + 2V.

24 V+ 3.2V 28 COMMON

-

+

N

5V LOGIC SECTION "LOW BATTERY" P

36 DGND

N

23 V-

FIGURE 3. BIASING STRUCTURE FOR COMMON AND DGND

V+ 24 EXTERNAL LOGIC 36 ILOGIC 23 VICL7129 DGND 500k DP4/OR PIN 20 DP3/UR PIN 21 LATCH/HOLD PIN 22 CONTINUITY PIN 27 ICL7129

FIGURE 6. "WEAK OUTPUT"

FIGURE 4. DGND SINK CURRENT

LATCH/HOLD, Overrange, and Underrange Timing The LATCH/HOLD output (pin 22) will be pulled low during the last 100 clock cycles of each full conversion cycle. During this time the final data from the ICL7129 counter is latched and transferred to the display decoder and multiplexer. The conversion cycle and LATCH/HOLD timing are directly related to the clock frequency. A full conversion cycle takes 30,000 clock cycles which is equivalent to 60,000 oscillator cycles. OverRange (OR pin 20) and UnderRange

3-36

ICL7129
(UR pin 21) outputs are latched on the falling edge of LATCH/HOLD and remain in that state until the end of the next conversion cycle. In addition, digits 1 through 4 are blanked during overrange. All three of these pins are "weak outputs" and can be overridden with external drivers or pullup resistors to enable their input functions as described in the Pin Description table. Instant Continuity A comparator with a built-in 200mV offset is connected directly between INPUT HI and INPUT LO of the ICL7129 (Figure 7). The CONTINUITY output (pin 27) will be pulled high whenever the voltage between the analog inputs is less than 200mV. This will also turn on the "CONTINUITY" annunciator on the display. The CONTINUITY output may be used to enable an external alarm or buzzer, thereby giving the ICL7129 an audible continuity checking capability. Since the CONTINUITY output is one of the four "weak outputs" of the ICL7129, the "continuity" annunciator on the display can be driven by an external source if desired. The continuity function can be overridden with a pull-down resistor connected between CONTINUITY pin and DGND (pin 36). Display Configuration The ICL7129 is designed to drive a triplexed liquid crystal display. This type of display has three backplanes and is driven in a multiplexed format similar to the ICM7231 display driver family. The specific display format is shown in Figure 8. Notice that the polarity sign, decimal points, "LOW BATTERY", and "CONTINUITY" annunciators are directly driven by the ICL7129. The individual segments and annunciators are addressed in a manner similar to row-column addressing. Each backplane (row) is connected to one-third of the total number of segments. BP1 has all F, A, and B segments of the four least significant digits. BP2 has all of the C, E, and G segments. BP3 has all D segments, decimal points, and annunciators. The segment lines (columns) are connected in groups of three bringing all segments of the display out on just 12 lines. Annunciator Drive
BUFFER

IN HI

+

-

COMMON IN LO 200mV - V + CONTINUITY

+ TO DISPLAY DRIVER (NOT LATCHED)

-

500k

A special display driver output is provided on the ICL7129 which is intended to drive various kinds of annunciators on custom multiplexed liquid crystal displays. The ANNUNClATOR DRIVE output (pin 3) is a squarewave signal running at the backplane frequency, approximately 100Hz. This signal swings from VDISP to V+ and is in sync with the three backplane outputs BP1, BP2, and BP3. Figure 9 shows these four outputs on the same time and voltage scales. Any annunciator associated with any of the three backplanes can be turned on simply by connecting it to the ANNUNClATOR DRIVE pin. To turn an annunciator off connect if to its backplane. An example of a display and annunciator drive scheme is shown in Figure 10.

FIGURE 7. "INSTANT CONTINUITY" COMPARATOR AND OUTPUT STRUCTURE

LOW BATTERY CONTINUITY
a f c e e d f g c e d b f g c e d a b f g c e d
BP3

a b f

a b g c
BP2 BP1 BACKPLANE CONNECTIONS

LOW BATTERY CONTINUITY
a f c e
F4, E4, DP4 A4, G4, D4 B4, C4, BC5 F3, E3, DP3 A3, G3, D3 B3, C3, MINUS

a b f g c e d c e b f

a b g c d e f

a b g c d
B1, C1, CONTINUITY A1, G1, D1 F1, E1, DP1 B2, C2, LOW BATTERY A2, G2, D2 F2, E2, DP2

f g e d

FIGURE 8. TRIPLEXED LIQUID CRYSTAL DISPLAY LAYOUT FOR ICL7129

3-37

ICL7129
compensation will depend upon the type of liquid crystal used. Display manufacturers can supply the temperature compensation requirements for their displays. Figure 11 shows two circuits that can be adjusted to give a temperature compensation of +10mV/ oC between V+ and VDISP . The diode between DGND and VDISP should have a low turn-on voltage to assure that no forward current is injected into the chip if VDISP is more negative than DGND. Component Selection
BP3

BP1

BP2

ON SEG.

There are only three passive components around the ICL7129 that need special consideration in selection. They are the reference capacitor, integrator resistor, and integrator capacitor. There is no auto-zero capacitor like that found in earlier integrating A/D converter designs. The integrating resistor is selected to be high enough to assure good current Iinearity from the buffer amplifier and integrator and low enough that PC board leakage is not a problem. A value of 150k should be optimum for most applications. The integrator capacitor is selected to give an optimum integrator swing at full-scale. A large integrator swing will reduce the effect of noise sources in the comparator but will affect rollover error if the swing gets too close to the positive rail (0.7V). This gives an optimum swing of 2.5V at fullscale. For a 150k integrating resistor and 2 conversions per second the value is 0.1F. For different conversion rates, the value will change in inverse proportion. A second requirement for good linearity is that the capacitor have low dielectric absorption. Polypropylene caps give good performance at a reasonable price. Finally the foil side of the cap should be connected to the integrator output to shield against pickup. The only requirement for the reference cap is that it be low leakage. In order to reduce the effects of stray capacitance, a 1F value is recommended. Clock Oscillator The ICL7129 achieves its digital range changing by integrating the input signal for 1000 clock pulses (2,000 oscillator cycles) on the 2V scale and 10,000 clock pulses on the 200mV scale. To achieve complete rejection of 60Hz on both scales, an oscillator frequency of 120kHz is required, giving two conversions per second.
V+

FIGURE 9. TYPICAL BACKPLANE AND ANNUNCIATOR DRIVE WAVEFORM
ANNUNCIATOR

m
LOW BATTERY CONTINUITY K M BACKPLANE ANNUNCIATOR AMPS VOLTS


BACKPLANE

FIGURE 10. MULTIMETER EXAMPLE SHOWING USE OF ANNUNCIATOR DRIVE OUTPUT

Display Temperature Compensation For most applications an adequate display can be obtained by connecting VDlSP (pin 19) to DGND (pin 36). In applications where a wide temperature range is encountered, the voltage drive levels for some triplexed liquid crystal displays may need to vary with temperature in order to maintain good display contrast and viewing angle. The amount of temperature
V+

1N4148

39K 200K 24 20K 19 VDISP ICL7129 36 DGND

39K 24 2N2222 19 VDISP ICL7129 36 18K 23 V23 VDGND

5K +

ICL7611

75K

FIGURE 11. TWO METHODS FOR TEMPERATURE COMPENSATING THE LIQUID CRYSTAL DISPLAY

3-38

ICL7129
In low resolution applications, where the converter uses only 31/2 digits and 100V resolution, an R-C type oscillator is adequate. In this application a C of 51pF is recommended and the resistor value selected from fOSC = 0.45/RC. However, when the converter is used to its full potential (41/2 digits and 10V resolution) a crystal oscillator is recommended to prevent the noise from increasing as the input signal is increased due to frequency jitter of the R-C oscillator. Both R-C and crystal oscillator circuits are shown in Figure 12. It is important to notice that in Figure 13, digital ground of the ICL7129 (DGND pin 36) is not directly connected to power supply ground. DGND is set internally to approximately 5V less than the V+ terminal and is not intended to be used as a power input pin. It may be used as the ground reference for external logic, as shown in Figure 4 and 5. In Figure 4, DGND is used as the negative supply rail for external logic provided that the supply current for the external logic does not cause excessive loading on DGND. The DGND output can be buffered as shown in Figure 5. Here, the logic supply current is shunted away from the ICL7129 keeping the load on DGND low. This treatment of the DGND output is necessary to insure compatibility when the external logic is used to interface directly with the logic inputs and outputs of the ICL7129. When a battery voltage between 3.8V and 6V is desired for operation, a voltage doubling circuit should be used to bring the voltage on the ICL7129 up to a level within the power supply voltage range. This operating mode is shown in Figure 14.
ICL7129 1 27k 5pF V+ 120kHz 10pF V40 2 CRYSTAL MODE: PARALLEL RS < 50k CL < 12pF CO < 5pF V+ REF HI + 3.8V TO 6V 36 8 2 + 3 ICL7660 4 5 + 10F 10F IN LO V23 REF LO ICL7129 DGND COM IN HI 24 34 35 28 33 32 VIN

ICL7129 1 75k 40 51pF 2

FIGURE 12. RC AND CRYSTAL OSCILLATOR CIRCUITS

Powering the ICL7129 The ICL7129 may be operated as a battery powered hand-held instrument or integrated into larger systems that have more sophisticated power supplies. Figures 13, 14, and 15 show various powering modes that may be used with the ICL7129. The standard supply connection using a 9V battery is shown in the Typical Application Schematic. The power connection for systems with +5V and -5V supplies available is shown in Figure 13. Notice that measurements are with respect to ground. COMMON is also tied to INLO to remove any common-mode voltage swing on the integrator amplifier inputs.
+5V 24 V+ 0.1F REF HI REF LO ICL7129 36 DGND COM IN HI IN LO V23 34 ICL8089 35 28 33 32 VIN

-

+

-

FIGURE 14. POWERING THE ICL7129 FROM A 3.8V TO 6V BATTERY

Again measurements are made with respect to COMMON since the entire system is floating. Voltage doubling is accomplished by using an ICL7660 CMOS voltage converter and two inexpensive electrolytic capacitors. The same principle applies in Figure 15 where the ICL7129 is being used in a system with only a single +5V power supply. Here measurements are made with respect to power supply ground.
+5V 24 V+ 34 0.1F 35 0.1F 8 2 + 3 ICL7660 4 5 + 10F 10F V23 32 36 ICL7129 28 33 VIN + ICL8089

0.1F

0.1F

-

-5V

FIGURE 13. POWERING THE ICL7129 FROM +5V AND -5V

FIGURE 15. POWERING THE ICL7129 FROM A SINGLE POLARITY POWER SUPPLY

3-39

ICL7129
A single polarity power supply can be used to power the ICL7129 in applications where battery operation is not appropriate or convenient only if the power supply is isolated from system ground. Measurements must be made with respect to COMMON or some other voltage within its input common-mode range. Voltage References The COMMON output of the ICL7129 has a temperature coefficient of 80ppm/ oC typically. This voltage is only suitable as a reference voltage for applications where ambient temperature variations are expected to be minimal. When the ICL7129 is used in most environments, other voltage references should be considered. The diagram in the Typical Application Schematic and Figure 15 show the ICL8069 1.2V band-gap voltage source used as the reference for the ICL7129, and the COMMON output as its pre-regulator. The reference voltage for the ICL7129 is set to 1.000V for both 2V and 200mV full-scale operation. Integrate Resistor RINT = VINFS/IINT RINT (Typ) = 150k Integrate Capacitor
( t INT ) ( I INT ) C INT = ---------------------------------V INT

Integrator Output Voltage Swing
( t INT ) ( I INT ) V INT = ---------------------------------C INT

VINT Maximum Swing: Display Count

(V- + 0.5V) < VINT < (V+ - 0.7V)

V IN COUNT = 10, 000 ---------------- ( Range = 1 ) V REF (2V Range) V IN 10 COUNT = 10, 000 ---------------------- ( Range = 0 ) V REF (200mV Range)

Multiple Integration A/D Converter Equations
Oscillator Frequency fOSC = 0.45/RC COSC > 50pF; ROSC > 50k fOSC (Typ) = 120kHz or fOSC = 120kHz Crystal (Recommended) Oscillator Period tOSC = 1/fOSC Integration Clock Period tCLOCK = 2*tOSC Integration Period tINT(2V) = 1000*tCLOCK tINT(200mV) = 10,000*tCLOCK 60/50Hz Rejection Criterion tINT /t60Hz or tINT /t50Hz = Integer Optimum Integration Current IINT = 13A Full Scale Analog Input Voltage VINFS (Typ) = 200mV or 2V
ZERO-INTEGRATE AND LATCH INT1 INTEGRATE

Minimum VREF: 500mV Common Mode Input Voltage (V- + 1V) < VIN < (V+ - 0.5V) Auto Zero Capacitor: CAZ not used Reference Capacitor: 0.1F < CREF < 1F VCOM Biased Between V+ and V-. VCOM V+ -2.9V Regulation lost when V+ to V- < 6.4V. If VCOM is externally pulled down to (V+ to V-)/2, the VCOM circuit will turn off. Power Supply: Single 9V V+ - V- = 9V Digital supply is generated internally VGND V+ - 4.5V Display: Triplexed LCD Continuity Output On if VINHI to VINLO < 200mV Conversion Cycle (In Both Ranges) tCYC = tCLOCK x 30,000

(Range = 1) (Range = 0)

DE1 DE-INTEGRATE REST X10

DE2 REST

X10

DE3 ZERO-INTEGRATE

NOTE: Shaded area greatly expanded in time and amplitude.
1000 CLOCKS 10,000 CLOCKS 2000 CLOCKS

INTEGRATOR RESIDUE VOLTAGE 1000 CLOCKS

3-40