Text preview for : dc0501.pdf part of panasonic dc0501 panasonic Video NV-HV65 NV-HV65EC_NV-HV60EB_NV-HV60EBL_NV-HV60EC_NV-HV60EP_NV-HV55EC_NV-HV50EC SVC dc0501.pdf
Back to : dc0501.pdf | Home
Pin No. Signal Name I/O Describe P-OFF P-SAVE P-FAIL Reset
1 A.DEF(H) O Output signal for audio defea and decoder IC reset. Low Low Low Low
Detection of COLOR KILLER active.
2 CKILLER DET(L) I In In In In
3 AFC S I S curve input from tuner. In In In In
Output signal depens on tape speed.
4 SLP(H) O (During N10H or P9H: High) Low Low Low Low
(Except N10H and P9H: Low)
PB input from AV2.
*3.21v ~ :High
5 CPB I In In In In
*1.23v ~ 3.21v :Middle
* ~ 1.23v : Low
Normal/Service/Test2/Test3 select.
* 4.0v ~ :NORMAL mode
6 N/S/T2 I * 2.5v ~ 4.0v :SERVICE mode In In In In
* 1.0v ~ 2.5v :TEST2 mode
* 0v ~ 1.0v :No define (spare)
Photo sensor input from supply side.
7 S-PHOTO I In In In In
(more than 2.6V: black / less than 2.4V: white)
Photo sensor input from take up side.
8 T-PHOTO I In In In In
(more than 2.6V: black / less than 2.4V: white)
9 TRACKING_ENVE I Video envelope input for auto tracking and CVC. In In In In
PB input from IC3001.
* 3.21v ~ : High
10 AV1_8IN I In In In In
* 1.23v ~ 3.21v: Middle
* ~ 1.23v: Low
11 CURRENT_LIMIT O Current limit for capstan driver. Low Low Low Low
12 F ADJUST O Analogue voltage output for HEAD frequency response adjustment. Low Low Low Low
13 ART.V/H/N O Artificial V synchronization signal. Low Low Low Low
14 IR I Interrupt input from IR sensor. In In In In
Output signal for AV2-PB "H". (2 Scart Model)
Output signal for AV1-PB "H". (1 Scart Model)
15 AVPB-H(L) O High High Low High
* H/M/L is output to 21pin-(8) when both terminals are set as follows.
Setting
Pin 8 AVPB-H(L) AVPBM-(H)
High L Hi-z
16 AVPB-M(H) O Middle H Hi-z
Low Low Low Low
Low H L
Write enable for EEPROM.
17 EEP_WR O High High Low High
*H:READ only L:Write
18 VIDEO.H.SW O Output signal for video HEAD switch. Low Low Low Low
19 A.H.SW O Output signal for FM audio HEAD switch. Low Low Low Low
I/O control to switch IIC bus for LW-programmer.
20 PROG ON(H) O H:IIC bus is connected to AV2. Low Low Low Low
L:IIC bus is not connected to AV2.
21 B/W(H) O Output signal for B/W mode. Low Low Low Low
22 NC O Non connect. (Low Fix) Low Low Low Low
Input signal for FM audio enverope level detection.
23 ABS_NORM(H) I In In In In
(Also serves that the Automatic Adjustment is completed)
24 V EE(L) O Output signal for switch between EE and VV. Low Low Low Low
25 D.FM.REC(H) O Control signal for FM audio recording current) Low Low Low Low
26 D.A.REC(H) O Control signal for normal audio recording current. Low Low Low Low
Control signal for FM audio recording current.
27 BIAS(H) O D.A.REC(H) Low Low Low Low
BIAS(H)
140ms 140ms
28 FM.MUTE(H) O Output signal for audio mute control. High High Low High
29 PAL-I/BG/DK(SYS4) O Output terminal for broad cast system to control the video circuit. Not fix Low Low Low
30 S-VHS DET(H) I Detection between SVHS and VHS. In In In In
Pin No. Signal Name I/O Describe P-OFF P-SAVE P-FAIL Reset
Input terminal for mechanism position.
31 POS.SW3 I In In In In
D.A.REC(H)
32 POS.SW2 I In In In In
BIAS(L)
140mS 140mS
33 POS.SW1 I In In In In
34 RESET(L) I MICOM reset input terminal. In In In In
35 32KHz IN I Sub oscillator input. --- --- --- ---
36 32KHz OUT O Sub oscillator output. --- --- --- ---
37 +5V(D) - Power. --- --- --- ---
38 12MHz.IN I Main oscillator input. --- --- --- ---
39 12MHz.OUT O Main oscillator output. --- --- --- ---
40 GND(D) - --- --- --- ---
Control signal for power circuit.
*Low is existed when turning off the power supply for concerned circuit.
41 POWER OFF(L) O *High is existed while power is supplied to mechanism and/or concerned circuit, Low Low Low Low
although it
seems to be power off.
Control signal for FIP on/off.
P-OFF in power save mode: "H" is output.
42 FIP ON(L) O Other than above: "L" is output. Low High Low Low
(Output switching timing of FIP"L" is same with the switching timing of POWER OFF
"L".)
43 12M.START(H) I Starting clock select terminal at releasing RESET. --- --- --- ---
44 LC.OSC IN I OSC terminal for OSD dot clock. --- --- --- ---
45 LC.OSC OUT O OSC terminal for OSD dot clock. --- --- --- ---
46 GND I GND --- --- --- ---
47 4FC.LPF I NC --- --- --- ---
48 OSD.FSC IN I NC --- --- --- ---
49 GND(OSD) - GND --- --- --- ---
50 CVIN I Composite video signal input terminal. --- --- --- ---
51 LECHA I Composite video signal white level input terminal. --- --- --- ---
52 CVOUT O CG video output teminal. --- --- --- ---
53 5V(OSD) - --- --- --- ---
54 HLF I LPF connection terminal for SLICER (Used for OSD dot clock.) --- --- --- ---
55 AMUTE(H) O Audio mute signal only for RF convertor. High High Low High
56 CVIN(EDS) I Composite video signal input terminal for SLICER. In In In In
57 GND I --- --- --- ---
58 SECAM/PAL(SYS2) O Output terminal for the unit recognition result of broad cast system. Low Low Low Low
59 SECAM.V.IN I Chroma input terminal for SECAM SUPERIMPOSE. --- --- --- ---
60 OSD PULSE O Abstraction signal for BOX from the video signal at SUPERIMPOSE. Low Low Low Low
Power circuit control signal for super power save mode.
*P-OFF in power save mode: "L" is output.
61 SLEEP(L) O Other than above: "H" is output. High Low Low High
*Output switching timing of FIP "L" is same with the switching timing of POWER OFF
"L".)
Control signal for Loading motor forward.
62 UNLOADING(H) O Low Low Low Low
*High is existed when the loading motor rotates reverse direction and/or breaking.
Control signal for Loading motor reverse.
63 LOADING(H) O Low Low Low Low
*High is existed when the loading motor rotates forward direction and/or breaking.
64 FLD CS O FLD chip select terminal. Not fix Not fix Low Low
65 MESECAM DET(H) I Detection between MESECAM and NORMAL in playback mode. In In In In
Output signal depens on tape speed in both EE and VV modes.
66 LP(H) O * During N4H,N6H,P6H or P9H: High. Low Low Low Low
* Other than above speed: Low.
Non connect.
67 NC O Low Low Low Low
* Low fixed.
68 FLD DATA OUT O Serial data output signal for FIP driver. Not fix Not fix Low Low
69 FLD DATA IN I Serial data input signal for FIP driver. Not fix Not fix In In
70 FLD CLK O Serial clock signal for FIP driver. Not fix Not fix Low Low
71 IIC CLK O IIC clock for all IIC devices Not fix Not fix Low Low
72 IIC DATA O IIC data for all IIC devices Not fix Not fix Low Low
125Hz output for adjustment of clock accuracy .
73 125Hz O Low Low Low Low
(Output in only TEST MODE 2.)
74 CAP.R/F O Control signal for capstan motor diriction. Low Low Low Low
Pin No. Signal Name I/O Describe P-OFF P-SAVE P-FAIL Reset
75 HALF_WAVE(H) O Control signal for switching capstan motor mode FAST and SLOW. In In In In
76 CAP.ET O Torque control signal for capstan motor. 0V 0V Low 0V
77 CYL.ET O Torque control signal for cylinder motor. 4.213V 4.213V Low 4.213V
78 P FAIL I Interrupt input signal for power fail detection. In In In In
79 S.REEL.PULSE I Input signal from supply reel sensor. In In In In
80 T.REEL.PULSE I Input signal from take up reel sensor. In In In In
Input signal from Safety-tab SW.
81 S TAB(L) I In In In In
* Safety-tab exists: Low, * Safety-tab does not exist: High)
Input terminal for signal from power button on the Front Panel.
82 POWER_KEY I In In In In
* Switch between ON and off, when down edge is detected.
83 CNR OFF(H) O CNR control for IC3001. Low Low Low Low
84 SECAM_ID(L) I Detection of SECAM mode. In In In In
85 DAVN I DAVN signal from Slicer In In In In
86 FG.AMP.OUT I Output from internal FG Amplifier --- --- --- ---
87 FG.AMP.IN I Input for internal FG Amplifier --- --- --- ---
88 GND(A) - --- --- --- ---
89 AV3_S_IN(L) I Detection of conposite or conponent for AV3 VIDEO INPUT. In In In In
90 PFG I FPG input terminal. --- --- --- ---
91 OREF O Output from internal reference voltage (2.5V) --- --- --- ---
92 IREF I Input for internal reference voltage --- --- --- ---
93 SCAS_IN(L) I Detection between VHS tape or S-VHS tape. In In In In
94 CTL.HEAD(-) I/O Input signal from CTL HEAD(+) --- --- --- ---
95 CTL.HEAD(+) I/O Input signal from CTL HEAD(-) --- --- --- ---
96 CTL.AMP.REF I Input for internal CTL amplifier reference voltage --- --- --- ---
97 PB.CTL.OUT O Output from internal CLT amplifier --- --- --- ---
98 +5V(A) - --- --- --- ---
99 +5V(AD) - --- --- --- ---
100 EX.FF/REW(L) O Control terminal for the filter of the PB-CTL signal during FF/REW. Low Low Low Low