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June1996
NDC632P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
These P-Channel logic level enhancement mode -2.7A, -20V. RDS(ON) = 0.14 @ VGS = -4.5V
power field effect transistors are produced using RDS(ON) = 0.2 @ VGS = -2.7V.
Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is Proprietary SuperSOTTM-6 package design using copper
especially tailored to minimize on-state resistance. lead frame for superior thermal and electrical capabilities.
These devices are particularly suited for low voltage
applications such as notebook computer power High density cell design for extremely low RDS(ON).
management and other battery powered circuits Exceptional on-resistance and maximum DC current
where fast high-side switching, and low in-line power capability.
loss are needed in a very small outline surface
mount package.
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4 3
5 2
6 1
TM
SuperSOT -6
Absolute Maximum Ratings T A = 25