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Text preview for : Service Manual Chassis 2114 Series EB5-C.pdf part of Sanyo Chassis 2114 EB5-C Series Service manual for the 2114 EB5-C Series chassis, not model specific. Complimentary to model-specific EB5-C service manuals.

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Service Manual
Chassis Description

4:3 Colour Television

CHASSIS 2114
EB5-C Series

Note This TV receiver will not work properly in foreign countries where the television transmission system and power source differ from the design specifications. Refer to the specifications for the design specifications.

Date of Edition: 07 May 2002, Version 1.1

Reference: MS CHASIS2114-I

Service Manual CHASIS 2114 (EB5-C Series)

Index
1. BEFORE STARTING.................................................................................................................................... 3 1.1. WARNINGS................................................................................................................................................. 3 1.2. X-RAY RADIATION PRECAUTIONS. ............................................................................................................. 3 1.3. ENVIRONMENTAL RECOMMENDATIONS ..................................................................................................... 3 1.4. SECURITY REGULATIONS AND EMC (ELECTROMAGNETIC COMPATIBILITY). ............................................ 3 TABLE OF CHARACTERISTICS OF CHASSIS 2114 (EB5-C SERIES).............................................. 4 BLOCK DIAGRAM. ..................................................................................................................................... 5 3.1. INTEGRATED CIRCUITS ............................................................................................................................... 6 3.1.1. General PCB ..................................................................................................................................... 6 3.1.2. PCB Audio. ........................................................................................................................................ 6 3.1.3. PCB Socket. ...................................................................................................................................... 6 DETAILED BLOCK DESCRIPTION . ....................................................................................................... 7 4.1. POWER SUPPLY. ......................................................................................................................................... 7 4.1.1. Switched mode power supply (SMPS)................................................................................................ 7 4.1.2. Voltage regulation in STANDBY........................................................................................................ 7 4.1.3. Outputs post-regulation and STANDBY/ON control. ........................................................................ 8 4.1.4. Mains switch-off detection. ................................................................................................................ 8 4.2. MICROPROCESSOR AND TELETEXT. ........................................................................................................... 9 4.2.1. Ports description ................................................................................................................................ 9 4.2.2. Voltage supplies ................................................................................................................................. 9 4.2.3. Working modes................................................................................................................................... 9 4.2.4. Oscillator ......................................................................................................................................... 10 4.2.5. Reset................................................................................................................................................. 10 4.2.6. I2C Bus and peripherals................................................................................................................... 10 4.2.7. RGB outputs, character generator................................................................................................... 10 4.2.8. Teletext............................................................................................................................................. 10 4.2.9. User commands reception................................................................................................................ 10 4.2.10. LED control signals...................................................................................................................... 11 4.2.11. Tuning control signals.................................................................................................................. 11 4.2.12. CTL1 and CTL2 Signals ............................................................................................................... 11 4.2.13. -PD&FAIL Signal......................................................................................................................... 11 4.2.14. SCA and SCB signals ................................................................................................................... 11 4.2.15. KEY Signal ................................................................................................................................... 11 4.2.16. LP Signal ...................................................................................................................................... 11 4.2.17. SOUND_EN Signal ...................................................................................................................... 11 4.2.18. HP_SW Signal .............................................................................................................................. 11 4.2.19. FRONT_SW Signal....................................................................................................................... 11 4.2.20. PBL Signal.................................................................................................................................... 12 4.2.21. ON Signal ..................................................................................................................................... 12 4.2.22. Rotation Signal............................................................................................................................. 12 4.2.23. IR Signal....................................................................................................................................... 12 4.2.24. SUP_FAIL signal ....................................................................................................................... 12 4.2.25. DEGAUSS Signal ......................................................................................................................... 12 4.2.26. 16_9 Signal................................................................................................................................... 12 4.2.27. Microprocessor block diagram .................................................................................................... 12 4.3. HORIZONTAL DEFLECTION ....................................................................................................................... 12 4.3.1. Driver stage ..................................................................................................................................... 12 4.3.2. Lines-stage. ...................................................................................................................................... 13 4.3.3. EHV flyback transformer (FBT)....................................................................................................... 13 4.3.4. E/W Phase........................................................................................................................................ 14 4.3.5. H_FLY signal Generation................................................................................................................ 14 4.3.6. Anti-"mouse-teeth" effect circuit...................................................................................................... 14 4.3.7. Protections. ...................................................................................................................................... 14 4.3.8. New deflection adjustments.............................................................................................................. 15 4.4. BEAM CURRENT LIMITER AND GEOMETRY COMPENSATIONS. ................................................................... 15 4.4.1. BCI and HVI signals generation...................................................................................................... 15 4.4.2. Geometry compensation................................................................................................................... 15 4.4.3. ACL Descriptión .............................................................................................................................. 16 4.4.4. PBL description. .............................................................................................................................. 16
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2. 3.

4.

Service Manual CHASIS 2114 (EB5-C Series)

4.5. VERTICAL DEFLECTION ............................................................................................................................ 16 4.5.1................................................................................................................................................................ 17 4.5.1. Vertical deflection supply................................................................................................................. 17 4.5.2. Vertical deflection protection........................................................................................................... 17 4.6. TUNER AND TUNING CIRCUIT.................................................................................................................... 17 4.7. VIDEO SIGNAL PROCESSING...................................................................................................................... 17 4.7.1. Video Processor ............................................................................................................................... 17 4.7.2. Pack I3 .............................................................................................................................................. 21 4.7.3. VIDEO PROCESSOR BLOCK DIAGRAM ...................................................................................... 22 4.7.4. Comb-Filter...................................................................................................................................... 22 4.7.5. Video switching diagrams................................................................................................................ 23 4.7.6. Television peripherals connection ................................................................................................... 24 4.8. RGB AMPLIFIER ...................................................................................................................................... 25 4.8.1. Socket Connector ............................................................................................................................. 25 4.9. AUDIO SIGNAL PROCESSING...................................................................................................................... 25 4.9.1. Audio Processor............................................................................................................................... 25 4.9.2. FM and NICAM Sound I.F............................................................................................................... 26 4.9.3. AM Sound......................................................................................................................................... 26 4.9.4. BBE .................................................................................................................................................. 26 4.9.5. Speakers amplifier ........................................................................................................................... 27 4.9.6. Headphones Amplifier ..................................................................................................................... 27 5. CONFIGURATION AND ADJUSTMENTS. ............................................................................................ 28 5.1. SERVICE MENU ........................................................................................................................................ 28 5.1.1. Service menu navigation .................................................................................................................. 28 5.1.2. Table of service menu values ........................................................................................................... 29 5.2. MEANING OF GEOMETRIC ADJUSTMENTS.................................................................................................. 32 5.3. ADJUSTMENTS. ........................................................................................................................................ 33 SPECIAL MODES AND ACTIONS. ......................................................................................................... 34 6.1. SECAM B/G - L ADAPTATION. ................................................................................................................. 34 6.2. INITIAL AUTO-TUNING ACTIVATION.......................................................................................................... 34 6.3. NON-VOLATILE MEMORY REPLACEMENT PROCEDURE. ............................................................................ 34 6.4. "FACTORY" MODE DESCRIPTION .............................................................................................................. 34 6.5. "HOTEL" AND "RENTAL" MODE DESCRIPTION.......................................................................................... 34 FAILURE DETECTION. ............................................................................................................................ 35 7.1. INTRODUCTION. ....................................................................................................................................... 35 7.2. ERROR INDICATION TABLES...................................................................................................................... 35 7.3. START-UP PROCESS .................................................................................................................................. 35 7.4. PD&FAIL SIGNAL ACTIVATION MOTIVE DETECTION PROCESS............................................. 36 7.5. PROTECTIONS' INHIBITION. ...................................................................................................................... 36 7.6. POWER SUPPLY START UP OSCILLOGRAMS. .............................................................................................. 37 DEFLECTION START UP OSCILOGRAMS ................................................................................................................ 38 7.8. FAILURE DETECTION DIAGRAMS ............................................................................................................... 39 GLOSSARY OF TERMS. ........................................................................................................................... 44

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Service Manual CHASIS 2114 (EB5-C Series)

1. BEFORE STARTING.
For a correct interpretation of this service instruction manual, it is recommended to read it together with the corresponding model's schematic diagram.

1.1.

Warnings.

Always consider that the primary side of the power supply is at the mains voltage. Therefore, an isolation transformer of adequate power handling capability should be connected in the power line between the television set and the AC line whenever any instrument without floating potential is connected to the primary side of the power supply. Also take into account that the deflection heatsink is connected to the vertical amplifier's negative voltage supply (B4-V).

1.2.

X-ray Radiation Precautions.

In television sets the picture tube (CRT) is a potential source of X-ray radiations. Its design and construction is conceived to limit this radiation according to the prevailing regulations provided that the specified polarization conditions are kept. In case of repairs take special care that the Extremely High Voltage (EHV) and Beam Current are kept within the specified limits in the Table of Characteristics. In horizontal deflection repairs, check carefully that only those components associated to the picture tube being used are assembled and that the horizontal deflection supply voltage is adjusted according to the table of adjustments.

1.3.

Environmental Recommendations

WORN OUT BATTERIES: Batteries included in the remote control of these models do not contain mercury . Even so, SANYO recommends NOT to dispose of worn out batteries in your household rubbish. Please contact your local authorities for information regarding the disposal of worn out batteries. END OF LIFE CYCLE INSTRUCTIONS: These SANYO television sets have been designed with recyclable and reusable materials. At the end of their life cycle, specialised companies can disassemble them to recuperate reusable materials and reduce disposable materials to the minimum. Please contact your local authorities for information regarding the disposal of your set when the time arrives. Please help us preserve the environment.

1.4.

Security Regulations and EMC (Electromagnetic Compatibility).

It fulfils the safety requirements established in the regulations: EN 60065:1998. It fulfils the EMC requirements established in the regulations. EN 55013:1990/A12:1993 / A13:1996 / A14: 1999 EN 55020:1994/A11:1996 / A13: 1999 / A14: 1999 EN 61000-3-2:1995 +A1:1998 +A2:1998 / A14:2000 EN 61000-3-3:1995

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Service Manual CHASIS 2114 (EB5-C Series)

2. TABLE OF CHARACTERISTICS OF CHASSIS 2114 (EB5-C SERIES).
21" True Flat A51ERF135X70: maximum EHV : 28,5Kv, maximum I.Beam: 1,2mA. 21" Super Flat A51EAL155X10: maximum EHV : 27,5Kv, maximum I.Beam: 1,2mA. 25" Super Flat A59EAK071X11: maximum EHV : 29,5Kv, maximum I.Beam: 1,4mA. Cathode ray tubes 28" Super Flat A66EAK075X11/A66EAK071X11: maximum EHV : 29,5Kv, maximum and its working limits I.Beam: 1,4mA. 25" Super Flat A59EAK071X11: maximum EHV : 29,5Kv, maximum I.Beam: 1,4mA. 28" Super Flat A59EAK071X11: maximum EHV : 29,5Kv, maximum I.Beam: 1,4mA. 29" True Flat A68EJZ011X101: Not available at the time of edition. Voltage Synthesis, 100 programmes in non-volatile memory, AFT, Finetuning (first 10 programmes), automatic search, semi-automatic and manual. Band I: channels 2-4 (VHF)=E2-E4 Tuning System Cable channels: S1-S20 Hyper-band Channels: S21-S41 III Band: Channels 5-12 (VHF)=E5-E12 IV-V Band: channels 21-69 (UHF)=E21-E69 B/G, D/K, I, L (all models) Reception System B/G, D/K, I, L, L' (models for France) PAL, SECAM, NTSC 3.58, NTSC 4.43, N.A.P. (NTSC Amusement by PAL) in all Colour System models Model CE21FFV1: 2 x 6,5W rms Speakers Power Models CE21FA4, CE28FV4: 2 x 5,5W rms (10% distortion, 2 x 8 Models CE25FA4, CE25FV4, CE25GN3, CE28FA4, CE28FV4, CE28GN3: 2 x 8,5W ohms load) rms Aerial External aerial socket 75 ohms IEC Headphones Jack Timer Functions Jack stereo 3,5mm. CTV switch-on and off programmable in real time. Clock and alarm function. Scart connector A: Inputs are RGB, slow switching (3 levels), composite video and audio-stereo. Outputs are composite video and audio (mode dependent on received transmission). Scart connector B: Inputs are RGB, slow switching (3 levels), composite video, SVideo and audio-stereo. Outputs are composite video and audio (audio mode is dependent on received transmission). Front Audio / Vídeo connector: 3 RCA connectors, composite video and audio stereo. 220 - 240 Vac 50Hz

AV Connectors

Power source

Model CE21FFV1: 49 W Power consumption according to IEC 107- Models CE21FA4, CE28FV4: 48 W Models CE25FA4, CE25FV4, CE25GN3: 61 W 1 Models CE28FA4, CE28FV4, CE28GN3: 66 W Stand-by Power 1,5W Consumption Teletext Special Modes Circuit variants Level 1.5 FLOF and LIST. 10 page teletext memory. Hotel and Hotel Rental Mode available A variety of circuits allow to generate the whole television set model's range based on the EB5-C chassis: Variant I3, Variant BBE, Variant Comb-Filter, Variant A/V Frontal, Variant L'

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Service Manual CHASIS 2114 (EB5-C Series)

3. BLOCK DIAGRAM.

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Service Manual CHASIS 2114 (EB5-C Series)

3.1.
3.1.1.

Integrated Circuits
General PCB .

IC100 (SAA5563PS) 8 bits microprocessor with embedded ROM memory, where the TV control software is stored. Also it includes the teletext handling block with a storage capacity of 10 pages. IC125 (SLA24C08-SR) Non volatile memory, EEPROM, of 8 Kbits. Contains data related to TV controls, configuration and adjustments data and tuning data for each programme. IC300 (TDA8946J) Audio power amplifier. IC350 (KA2209B/TDA2822M) Headphones amplifier. IC400 (TDA8874/TDA8879) IF Demodulator circuit, video processor and deflection processor, for multi-standard signals. IC701 (LA7846N) Vertical deflection power amplifier. IC800 (MC44603ADW) Power supply controller. IC801 (TCET1101G) Power supply opto-coupler. IC850 (KA431LZTA) Power supply voltage reference regulator. IC852 (LD1117V33C) 3.3V Voltage regulator. IC852 (LD1117V33C) 8 V Voltage regulator. IC852 (LD1117V33C) 5 V Voltage regulator. IC900 (LA 7221) Video switch. IC1050 (TDA9181T ) Comb-filter.

3.1.2.

PCB Audio.

IC1300 (TDA 9875AH) Audio processor. IC1380 (BA3880AFS) BBE sound effect function.

3.1.3.

PCB Socket.

IC500 (TDA6107Q N2) RGB. Amplifier.

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Service Manual CHASIS 2114 (EB5-C Series)

4. DETAILED BLOCK DESCRIPTION . 4.1. Power supply.
It is a switched mode power supply (SMPS) with flyback configuration and current mode controlled. It is based on the MC44603 SMPS controller IC (IC800) and an external MOS transistor (Q800) as the switch. The SMPS outputs are the following: B1: Main output, for deflexion and EHV. The "+33V" voltage used for the TV tuning circuit, is also obtained from this SMPS output through a switch (Q862), that is open in STANDBY. B2: Audio Amplifier supply. Its consumption is reduced practically to zero in STANDBY. B4+ and B4-: Symmetric supplies (approximately +/-15 Volts) for the vertical amplifier. In STANDBY they are switched off with Q850 and Q852 transistors respectively. B5: It is approximately +10 Volts. From this output and with IC853, the 8 Volts to feed processor IC400, is obtained. It is also used for the regulation-circuit polarisation (opto-coupler IC801) and to feed infrared receiver (RI100). In STANDBY IC853 is switched off. B6: It is approximately 7 Volts. From this output it is obtained the microprocessor's 3,3 Volts supply with the linear regulator IC852 and the +5 Volts for the tuner and the audio processor with the regulator IC854. It is also disconnected in STANDBY. B8: Auxiliary output in the primary of the SMPS to feed and provide the necessary control signals for IC800.

4.1.1.

Switched mode power supply (SMPS).

4.1.1.1. IC800 Controller start-up. The power for starting up IC800 comes from the charge of C811 through R805. When the voltage at pin 1 exceeds 14,5 Volts (threshold voltage), the IC initiates oscillation (pin 3). Once started, the IC consumption increase is fed by B8 output. The current circulating through R805 is not continuous, because since it is taken from one of the mains' poles, there is half-cycle conduction only, thus keeping it with reduced dissipation. 4.1.1.2. Normal working mode ("on"). 4.1.1.2.1. Duty cycle. Each cycle starts when Q800 begins conducting, and it is cut off when primary current has reached a certain level. From this moment, the diodes on the secondary side begin conducting, and remain this way until the energy stored in the core of the SMPS transformer during the transistor conduction state, has passed to secondary, in which moment the SMPS-transformer output voltages drop to zero. This zero crossing point is detected by IC800 (pin 8 "DEMAG. DETEC"), which then begins a new cycle provided that its oscillator (pin 10 "CT") has dropped to the low level. Otherwise it waits until that condition is fulfilled. 4.1.1.2.2. Regulation. The SMPS controller makes two regulations. The first one controls peak current in the primary, in order to maintain the energy level that passes to secondary in each cycle (current mode). If only this was done, the output voltages would vary depending of the load consumption. In order to prevent this there is a voltage regulation that controls the reference of the current regulation: if consumption increases, the output voltages tends to decrease and the IC raises the current control setting to transfer more power. Current readout is performed by measuring the voltage drop at pin 7, which is caused by the current flow through R820 and R821 resistors. This signal is applied to a comparator, which controls the transistor's conduction time. The comparator's reference comes from the voltage regulation output as explained ahead. This reference is internally limited to 1 Volt. Therefore in case of outputs overload, the maximum possible current in the primary is that which produces1 Volt in pin 7 of the IC. From this point on, if there is an increase in consumption, the output voltages decrease, remaining the SMPS protected. It is important to point out that a good performance of the current control depends on the condition of R820 and R821, whose resistance can be altered in case of failure of Q800. Therefore, whenever the transistor is replaced because of a failure, R820 and R821 resistors must also be replaced with new ones. The current reference for IC800 is obtained at pin 13 "E_A_OUT". This pin is the output of a unity gain amplifier, which is made up of an internal differential amplifier plus R803 and R806 resistors and which input comes from opto-coupler IC801. Voltage regulation is performed on the secondary side of the SMPS with IC850, which compares the signal coming from the B1 voltage divider, R855/R856-VR850, with an internal reference of 2,5 Volts. The output of IC850 controls the opto-coupler, thus closing the regulation loop. 4.1.1.3. STANDBY. MC44603P has a STANDBY mode based on the primary peak current measurement. If this peak current does not reach a certain level (programmable with R804), it turns to work at a fixed frequency of around 16Khz (R813 determines this frequency). The value of R804 has been chosen in the design stage so that when the TV set goes into its STANDBY mode, IC800 does the same, too.

4.1.2.

Voltage regulation in STANDBY

When the load on B1 (main output) decreases (in fact, in standby mode it is switched off) the voltage at the 7

Service Manual CHASIS 2114 (EB5-C Series)

remaining outputs tends to drop. The network associated to D866 determines the minimum voltage at B6 to prevent the microprocessor from being left out without supply. This network begins to work when B6 reaches 5 Volts from the 7 Volts that are present in the "ON" state. From this point on, the voltage regulation is tied to B6; B1 is not regulated and increases up to 20 regarding to the "ON" state voltage. On the primary side, zener D804 performs the same function for B8, to prevent IC800 from stopping during the start-up transients and in the transients between STANDBY and ON states.

4.1.3.

Outputs post-regulation and STANDBY/ON control.

It is done by the following signal and components chain as shown in the diagram below: microprocessor's "ON" signal ! Q862 (B1_S) ! Q850 (B4+S) ! IC853 (+8V) and Q852 (B4-S) ! (+5V)

T800 CHOPPER

D850

B1 RELE DEGAUSSING B1_S

Q862

R250

+33V

"DEGAUS" "-PD"

Q855

+
"-PDandFAIL"

"-FAIL"

Q859 B6

"RESET"

3V3_M
IC852 3V3

D855

IC125 NVM

IIC_E

IC100 MICRO

"ON" "-SUP_FAIL"

IC854

+5V Sintonizador y audio

D854

B5 IC853 +8V: IC400 F.I., proc. vídeo y deflexión

D852

B4+ Q850 B4+S Positivo de vertical

D853

B4Q852 B4-S Negativo de vertical

4.1.3.1. Protection of regulator outputs short-circuits. Short-circuits on "+5V" and vertical voltage supplies are controlled thanks to the above mentioned chain, by the microprocessor monitoring signal "-SUP_FAIL" (actually "+5V"): if a low level is detected, it deactivates the "ON" signal, thus switching the regulators off. In this case the microprocessor signals the problem with four LED blinks (ERROR_4). Regarding the "+8V" short-circuit protection there is already the rest of the TV set protections (activated by deflection circuit failures) as well as the IC's own self-protection. Regarding vertical supply switches they have current limiting of about 2A (Q853 and Q854) to avoid the current peaks that would happen when charging the amplifier's decoupling capacitors (C701 and C704). The control of "+5V" comes from B4-S switch saturation-detection (Q852) by means of transistor Q857.

4.1.4.

Mains switch-off detection.

When the mains is switched off, and while C810 (the main primary side, electrolytic capacitor) is discharging, the microprocessor performs two switch-off related functions: activate speakers mute to prevent undesired "pop" noises, and discharge the CRT. The discharge of C810 is detected in the secondary winding B6 of the SMPS transformer, due to the negative voltage of the SMPS switching pulses, as this voltage mirrors the rectified voltage of the primary, according to the turns ratio of the SMPS transformer. The circuit used for this function is that related to Q855 (negative level detection, filtering and comparison with a triggering level) which generates signal "-PD" for the microprocessor. 8

Service Manual CHASIS 2114 (EB5-C Series)

4.2.
· · · ·

Microprocessor and Teletext.
Management of commands coming through its input ports. Actuation on the different parts of the circuit through its output ports. Teletext management. User interface through OSD menus and LED indicator.

Main microprocessor (IC100) functions can be divided in four classes:

4.2.1.

Ports description

Ports, names of associated signals and its basic function description, are shown in the table below.
Signal V_SINT LB MB HB LP ROTATION HP_SW FRONT_SW SCA SCB KEY PBL FRENO_CAG LED_G LED_R I/O O O O O O O I I I I I I O O I O O I I O O O O O O I I O O I/O O I/O Type PWM PP OD OD OD PP PWM PP Port / Pin Nº DESCRIPTION P2.0 / 1 DAC for tuning voltage. P2.1 / 2 P2.2 / 3 P2.3 / 4 P2.4 / 5 P2.5 / 6 P2.6 / 7 P2.7 / 8 P3.0 / 9 P3.1 / 10 P3.2 / 11 P3.3 / 12 P0.0 / 14 P0.1 / 15 P0.2 / 16 Tuner low band activation Tuner mid band activation Tuner high band activation H: activates L' standard related circuits Picture rotation control At high level indicates inserted headphones' jack. At high level indicates inserted camera connectors Scart A Pin 8 analog reading Scart B Pin 8 analog reading Keyboard analog reading PBL voltage analog reading H: limits tuner gain. O: Green LED control . I: I2C Hold, at low level stops I2C and passes to test machine mode. O Red LED control . O Timer 40ms (used by test machine). O in test machine, it indicates i2cBusy (if high) / i2cHold (if low). Low level indicates failure in the power supply regulators Input for signal Power Down and Fail (failure in horizontal deflection). LED intensity control. Maximum I_led 8 mA. H: Activates degaussing relay. Maximum beam current selection. At high level (mode 16:9) reduced 25%. At high level activates power supply regulators. Video source selection O: Video Selection. I: "-FAIL" reading (failure in horizontal deflection). Infrared pulses input. At high level allows sound in speakers and headphones Peripherals' I2C Bus Clock Peripherals' I2C Bus Data NVM I2C Bus Clock NVM I2C Bus Data

AD AD AD AD PP OD OD

-SUP_FAIL -PD&FAIL LED_I DEGAUSS 16_9 ON CTL1 CTL2 IR SOUND_EN SCL SDA SCL_E SDA_E

OD PP PP PP PP OD

P0.3 / 17 P0.4 / 18 P0.5 / 19 P0.6 / 20 P0.7 / 21 P3.4 / 30 P1.0 / 45 P1.1 / 46 P1.2 / 47 P1.3 / 48 P1.6 / 49 P1.7 / 50 P1.4 / 51 P1.5 / 52

PP OD OD OD OD

4.2.2.
· · ·

Voltage supplies

The microprocessor has the following voltage supply pins: Pin 31: Analog supply (VDDA). Pin 39: CPU core supply (VDDC). Pin 44: Internal peripherals supply (VDDP).

4.2.3.
·

Working modes

There are two working modes: Idle: In this state the microprocessor consumes very little power. When TV set is in standby, the microprocessor remains in this state. Most internal circuits are disabled, keeping in use only those required for handling the remote control and keyboard. Normal: It is the state in which the microprocessor works when TV set is ON. All of its circuits are working. 9

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Service Manual CHASIS 2114 (EB5-C Series)

4.2.4.

Oscillator

The oscillator is based on a 12MHz quartz crystal (X100), which is connected to pins 41 and 42. Pin 40 is the oscillator's ground and it is internally connected in the microprocessor (it is not connected to ground through printed circuit).

4.2.5.

Reset

The reset signal is active at high level. This signal initialises the microprocessor (provided that the voltage supply is correct and the 12MHz oscillator has already started). The reset signal is generated by Q859 and its periphery. When voltage B6 is smaller than 4,9 Volts, the reset signal is activated.

4.2.6.

I C Bus and peripherals

2

The I2C bus hardware is made of signals SDA0 and SCL0 (microprocessor, IC100, pins 50 and 49 ) and signals SDA1 and SCL1 (pins 50 and 49). The microprocessor has two I2C buses The video processor (IC400) and the audio processor (IC1300) are the peripherals connected to the first I2C bus (pins 50 and 49). The non-volatile memory (IC125) is the only peripheral connected to the second I2C (pins 52 and 51). Most of the TV set functions (audio and video functions) are handled through I2C bus.

4.2.7.

RGB outputs, character generator

Integrated in the microprocessor there is a character generator with the following outputs: RGB (pins 34,33,32) and Fast Blanking (pin 35). These RGB outputs are activated when an OSD or when Teletext is to be displayed. 4.2.7.1. Character generator synchronisation Character generator synchronisation is done by means of signals VSYNC (pin 37) and HSYNC (pin 36). The HSYNC signal is used to synchronise the character generator horizontally. It is taken directly from the line flyback pulses and conformed to microprocessor levels. The horizontal position can be adjusted in the service menu. The VSYNC signal is used to synchronise the character generator vertically. Vertical blanking information is taken out from the SANDCASTLE signal (Q104, Q105 and its periphery perform this function) and the resulting signal is fed to VSYNC. Wrong values in VSYNC separation-filter components (R130, R131 and C106) can make teletext to be displayed with vertical instability. 4.2.7.2. Range of RGB outputs RGB outputs amplitude inversely follows the contrast adjustment of the user. The lower the user's contrast adjustment, the higher the OSD or teletext contrast (bigger RGB outputs) The aim is that OSD be at least noticeable for low user's contrast adjustments. 4.2.7.3. Half Tone There is an OSD display mode in which the background is shown with a contrast reduction (Half Tone). This display mode is controlled by the HALFT video processor's signal (IC400 pin 3) connected to the CORB microprocessor's signal (IC100 pin 29) (signal intended to enable this effect and that in our case, it is activated whenever the OSD background is shown). Whether the Half Tone function is enabled or not, is selectable by means of the user's menu option "Background (inside OSD others/Adjustments). Half Tone will not operate when a menu is shown but in the rest of the OSD messages.

4.2.8.

Teletext

The microprocessor has integrated teletext processing circuitry: Data slicer, decoder, memory (10 pages) and character generator. The microprocessor pins related to teletext function are: · · · 4.2.8.1. Video input (CVBS_TXT signal): pin 23. Input synchronism filter SYNC_FILTER): pin 25. Reference current for analog circuitry: pin 26. De-Interlace.

When TV set is in normal TXT mode (background is black), display is in non interlaced mode. When TV set is in mix TXT mode (background is picture), display is in interlaced mode. Interlaced/non-interlaced mode selection is performed by the microprocessor by means of a command given through I2C bus to IC400. It is the video processor (IC400) that produces the proper vertical signal for each mode.

4.2.9.

User commands reception
10

User commands reception is done in the conventional way: by local keyboard and by remote control. The

Service Manual CHASIS 2114 (EB5-C Series)

microprocessor reads the keyboard through the analog signal KEY. Regarding the remote control, its commands are detected by RI100 infrared receiver and decoded by the microprocessor.

4.2.10. LED control signals
Signals -LED_G, -LED_R and -LED_I are outputs active at low level. They control D100, bicolour red/green LED. -LED_G switches on green LED, -LED_R switches on red LEAD and -LED_I controls LED's intensity.

4.2.11. Tuning control signals
" " " Tuning voltage (V_SINT). Obtained through integration of the high resolution PWM signal (TPWM, pin 1) of the microprocessor. Band selection. Ports 2.1 (-LB: low band (VL)); 2.2 (-MB: mid band (VH)) and 2.3 (-HB: high band (U)). AGC low (-AGC_LS), port 0.0 (microprocessor's pin 14). This signal is active only in the initial auto tuning s and automatic tuning search. Its purpose is to fix a low AGC voltage to decrease the tuner's gain and thus discard weak broadcast signals.

4.2.12. CTL1 and CTL2 Signals
While the TV set is ON these signals are outputs that control the video switch IC900. Their states are the following:
Selection TV CTL1 CTL2 H H SCART_A H L SCART_B L L A/V FRONTAL L H

In case of PD&FAIL signal activation, CTL2 becomes input. As input, it is used to discriminate whether PD&FAIL signal has been asserted by a secondary supply voltage dip, and then it is possible that the power supply is going to stop ("Power Down") or because of a failure in horizontal deflection ("Fail"). CTL2 indicates "FAIL" i.e. an "0" indicates failure in horizontal deflection.

4.2.13. -PD&FAIL Signal
This signal goes to an input port and is active at low level. This signal is activated by the protection circuits of the power supply and horizontal deflection, as well as by the power-supply voltage dip detector. It indicates that the supply voltage can drop soon (PD: "Power Down") or a failure in horizontal deflection (FAIL).

4.2.14. SCA and SCB signals
Signals SCA and SCB are connected to two A/D converters input ports. These signals are the readings of pin 8 of the SCART connectors (TV/AV switching). Pin 8 levels are: " " " From 0V to 3.25V ! TV mode. From 3.25V to 8.25V ! AV Mode, 16/9 format. From 8.25V to 12V ! AV Mode, 4/3 format.

4.2.15. KEY Signal
This is the voltage value produced by pressed keys. Key detection will be performed by using of one of the microprocessor ADC's

4.2.16. LP Signal
Output port (active at high level) that selects L' system (used only in France).

4.2.17. SOUND_EN Signal
This is an output, active at high level, enabling sound at speakers and headphones. It is deactivated when passing to STAND_BY and when, there is no video synchronism in the ON state. Sound enabling or disabling at programme changes or under user's command by remote control is not done by this signal, but by the audio processor through the I2C bus.

4.2.18. HP_SW Signal
This signal goes to an input port, which in case of being at a high level indicates that a headphone jack has been plugged into the socket. When this happens, headphone sound and headphone related OSD are enabled.

4.2.19. FRONT_SW Signal
This signal goes to an input port, which in case of being at a high level indicates that a RCAconnector has been plugged into the front video socket. When this happens, AV3 is enabled and automatically selected. 11

Service Manual CHASIS 2114 (EB5-C Series)

4.2.20. PBL Signal
This signal goes to an A/D converter input. The signal read is a D.C. voltage coming from the peak beam-current limiting circuit (Q670, Q671 and periphery). If its level is 2,5V, there is no reduction of the video processor's contrast register. When it is lower than 2,5V, the contrast register content is decreased proportionally to the read voltage value.

4.2.21. ON Signal
It is an output, active at high level. Its function is to connect or disconnect the secondary voltage supplies of the power supply circuit.

4.2.22. Rotation Signal.
It is a PWM signal that manages the picture rotation value selected by the user (the rotation circuit is optional, depending on models).

4.2.23. IR Signal
Infrared signal input. This signal produces a microprocessor interrupt at each falling edge. Which remote-control key has been pressed, is detected by measuring the delay between these interrupts.

4.2.24. SUP_FAIL signal
It is an input active at low level, that indicates a voltage dip at the regulators outputs.

4.2.25. DEGAUSS Signal
It is an output that activates the relay for CRT degaussing. It is active at TV switch-on time.

4.2.26. 16_9 Signal
Maximum beam current selection. At high level the maximum beam current is reduced by 25%. It activates when picture is displayed in 16:9 format.

4.2.27. Microprocessor block diagram

4.3.
4.3.1.

Horizontal Deflection
Driver stage

This stage is used as an interface between IC400, which generates the line-frequency oscillation, and the base of the lines transistor, Q650. It is necessary, as the output of IC400 can not directly drive the base Q650. The square signal at pin 40 ( Hout signal) drives the base of Q604 configured as an emitter follower (it does not work in cut-off / saturation mode, but in the active working range). Q604 output (emitter) drives the base of Q600, to which R605, C603 and R602 are connected. C603 is a speed-up capacitor that charges and discharges the base of Q600 when Q604 emitter switches. Thus Q600 switching (it works in cut-off / saturation mode) is not influenced by temperature nor by transistor parameters tolerances. Q600 drives the primary of T600. In parallel with the primary of T600 there are C601, R601 and C602, which are key components which function ist to limit the maximum voltage peak at the collector of the Q600, as well as to conform the current wave to the base of Q650. 12

Service Manual CHASIS 2114 (EB5-C Series)

The secondary of T600 drives the base Q650, final lines transistor. L600 is also a key component since it determines the slope of current drain from the base of Q650 Its value is chosen to minimise Q650 switching losses. R612 minimises the influence of the tolerance in B11 voltage values, over the base current of Q650. 4.3.1.1. Driver stage supply. A secondary winding of T650 gives a positive flyback pulse which is rectified by D663 and smoothed by C668, delivering the D.C. voltage B10. The supply for the driver stage, B11, is obtained from B100. R603 and R606 determine B11 voltage, being this about 70V for models of 110º and 50V for the 90º. 4.3.1.2. Lines-Stage Starting ,Since the lines-stage is off before it starts working, B10 is 0V initially. Therefore, it is necessary for the linesstage to start working, an extra driver-stage supply that is already active in advance. In this chassis the start supply is provided by B1 through R608.

4.3.2.

Lines-stage.

The innovation over EB5-A chassis is that the deflection circuit topology is the same for 100º and 90º CRTs. Up to this chassis, diode modulators and E/W correction circuits were not used in Sanyo models of 90º CRTs. The width adjustment was done manually with an adjustable coil. The classic diode modulator circuit configuration has been slightly modified to achieve a bigger "S" correction when the deflection current is higher (more width) and less "S" correction with smaller deflection current (less width). With this new configuration the "S" correction is automatically regulated for each picture width. This new configuration is named "Linear Zoom". Even though this configuration is especially suited for 16:9 CRTs, it also gives an improvement in "S" correction for 4:3 CRTs. The main difference regarding classic configuration is in the location of the auxiliary "S" capacitor (C653 in this chassis). The smaller the picture width, the bigger the current flows through C653 and vice versa. Thus there is "Inverse S" current modulation through C653. "S" correction in current flow through the deflection yoke, is mainly determined by the value of C652. Current circulating through C652 and through the deflection yoke, is influenced by current circulating through C653, thus achieving the right amount of "S" correction for each picture width. The supply of the lines stage (voltage B1_F) is provided by the SMPS. Its value depends of each CRT model and it is essential to adjust it to the value mentioned in the Adjustments section.

4.3.3.

EHV flyback transformer (FBT)

The EHV flyback transformer T650 is resposible for generating the CRT polarisation voltages (MAT, G2, focus and heaters) as well as several auxiliary voltage supplies for the chassis. In the case of failure it is absolutely essential that its replacement has the same Sanyo code. If in doubt about it, please ask the Service Department Only "multi-layer"-technology FBTs are used in this chassis. They do not have embedded bleeder (it is a high ohmic value resistance for discharging the tube at switch-off) so care should be taken to discharge the tube before disconnecting the EHV cable. The auxiliary generated voltage supplies are the following: · · · · B10: Driver stage supply. B3: RGB amplifier supply. B7: negative polarisation for the PBL circuit. -B negative flyback pulse for linearity dynamic correction.

4.3.3.1. Heaters supply. CRT heaters supply voltage value is determined by T650, R655 and L506. In order to keep the heaters supply within the right limits, B1 adjustment, the values of deflection components and R655 and L506 must be those shown in the schematic diagram for the corresponding model. An excessively high heaters supply voltage considerably shortens the CRT lifetime. Whenever measuring the heaters supply voltage, the voltmeter must fulfil the following requirements: minimum crest factor of 10 and minimum bandwidth of 5MHz. Portable multi-meters do not usually comply with these characteristics. 4.3.3.2. EHV Discharge. The television set does a partial EHV discharge every time is switched off. The process is as follows: before switching the TV set off, the microprocessor writes `1' to the STB bit of the video processor (IC400) via I2C bus. This bit setting makes the video processor linearly increase the lines oscillation frequency for 43mS up to twice the normal line frequency value while shifting the RGB outputs to white. As a consequence, the flyback pulse amplitude decreases linearly making the flyback transformer (T650) to generate an EHV that decreases in the same way. Meanwhile, since beam current is flowing (because RGB outputs are at white), there is EHV load consumption, making EHV drop below half its normal working value. However, for this partial EHV discharge to happen, the CRT heaters have to be hot (otherwise there would be no beam current). So, in the case of switching the set on with cold heaters and switching it off immediately without 13

Service Manual CHASIS 2114 (EB5-C Series)

letting them time enough to worm up, then EHV remains at its maximum value. Two different EHV discharge visual appearances are available, selected by Service menu OSO bit : OSO OFF: Discharge with vertical deflection active: A white, wide strip with flyback lines and decreasing width along the screen is displayed. OSO ON: Discharge with vertical deflection shifted upwards: A white halo can be seen in the upper part of the screen. It is recommended to program the OSO bit to OFF. In case of turning off the mains switch or disconnecting the AC line, the circuit that produces the PD&FAIL signal (Q855 and its periphery) warns the microprocessor, with certain anticipation, that the supply is going down. Thanks to the energy stored in C810 there is still some time left before the SMPS stops oscillating. This time is enough for the microprocessor to perform the switching off and EHV discharge process.

4.3.4.

E/W Phase.

The final E/W amplifier is made up of Q750, Q753, Q754 and their periphery. Its input signal ( EW signal, pin 45 of IC400) is in current mode, therefore the parabola cannot be monitored in voltage at the base of Q754. Instead it is possible to monitor the parabola in the amplifier's output (emitter of Q750). IC400 requires a D.C. level greater than 1V at its E/W output. D750 guarantees the correct polarisation of IC400. The D.C. level at the amplifiers output determines the width of the picture. The bigger the D.C. the narrower the picture. The parabola's amplitude determines the pin-cushion distortion. By correctly adjusting the geometry parameters, the parabola's amplitude becomes adequate to obtain straight lines on the picture sides. R754 determines the circuit's gain. It is of metal film type, with a temperature coefficient of 50ppm, to prevent temperature drifts. R750 and R760 limit current transients when starting and stopping deflection, while acting as sensing resistors for the over current E/W protection circuit. L750 is the output coil. It provides high impedance at lines frequency and a low impedance at frame frequency. With this it is possible to modulate the width without noticeably affecting the deflection-circuit tuning. C753 filters line frequency, preventing it from reaching the E/W amplifier. C751 gives stability to the circuit at high frequencies, preventing undesired oscillations.. The purpose of D753 is to activate the protection circuit in the case of current overflow through Q750 Therefore it is not conducting under normal conditions.

4.3.5.

H_FLY signal Generation.

The capacitive devider made up of C654 and C655, which is connected to the main flyback (Q650 collector), determines an smaller flyback (about 60Vpp) which is used to generate the horizontal synchronisation signal H FLY with which the video processor generates the SANDCASTLE signal. R653 damps an oscillation produced at the end of the line flyback.

4.3.6.

Anti-"mouse-teeth" effect circuit.

Whenever the picture has a bright horizontal line and in the following lines the picture contents is much darker, an oscillation is produced in the deflection circuit. The circuit made up of L656, R661 and C656 damps and minimises this oscillation.

4.3.7.

Protections.

Several horizontal deflection protections converge to the same point: they polarise the base of Q652 and consequently activate the following signals. PD&FAIL and CTL2. The microprocessor reads this situation and puts the TV into ERROR_3 mode. The horizontal deflection protection is not operative in the following cases: · · · · I2C BUS is selected in service mode. The TV set is in standby During TV set on/off transients In forced start mode.

4.3.7.1. Low B12 protection. In case of very low B12 voltage, D655 and D661 stop conducting, Q651 switches off and R658 polarises the base of Q652. 4.3.7.2. CRT heaters short-circuit protection. In case of heaters short-circuit, the whole voltage generated by T650 drops in R655, therefore D656 and D657 14

Service Manual CHASIS 2114 (EB5-C Series)

conduct thus polarising the base of Q652. This protection is not used when L506 is assembled, since the coil withstands the heaters' short-circuit. 4.3.7.3. B1 overload protection. B1 overload produces a voltage drop on R666 that polarises Q653. Then Q653 enters conduction state and polarises the base of Q652 through R668. Normal B1 consumption an insufficient voltage drop in R666 to polarise Q653 4.3.7.4. Low-E/W output protection. E/W output of 0V is a symptom of a failure of the E/W amplifier or in the diode modulator stage. Under this circumstance, Q751 remains in cut off and polarises the base of Q652 through R758 and D752. 4.3.7.5. E/W overload protection. Certain deflection failures produce an increase of current flow in the E/W branch. In this case, the voltage drop in R750-R760 increases, polarising D751 and Q752. Then Q752 conducts polarising the base of Q652 through R753. 4.3.7.6. Excessive beam current protection. Excessive beam current produces a consumption increase on B1 supply. Thismay be enough to activate the B1 overload protection. If this is not so, another consequence of beam current overload is that the BCI signal decreases under 0V permanently, thus entering D704 and D705 into conduction, Then V_GUARD pulses decrease under the correct working threshold established by IC400 and the TV set goes to ERROR_2.

4.3.8.

New deflection adjustments.

As the EB5-C chassis is prepared to incorporate flat tubes, there are new adjustments in respect to older chassis. These new adjustments are found in the Geom Adv menu: " " " " HOR BOW: horizontal phase curve adjustment HOR PARALL: horizontal phase angle adjustment UPPER CORNER: upper corners adjustment LOWER CORNER: lower corners adjustment

4.4.
4.4.1.

Beam current limiter and geometry compensations.
BCI and HVI signals generation.

BCI signal (Beam Current Information) reflects the CRT beam current. This signal is used by ACL (Automatic Contrast Limiting) a circuit internal to IC400, that starts reducing contrast and brightness when a certain voltage threshold is reached. The less the beam current, the bigger is this signal's voltage. HVI signal (High Voltage Information) reflects EHV changes. This signal is used by geometry (height, width and phase) compensations. It is formed by the BCI signal plus the voltage drop in R675, which is proportional to EHV's current charge. The time constant of BCI and HVI must be about 0,5mS to be able to be used in geometry compensations. In order to achieve this time constant, the CRT return connection (aquadag) is made through R670 to the BCI signal. Therefore CRT aquadag is not ground. The circuit composed by R677, R676, R678, D672 and R679 generates a voltage transfer function of HVI with respect to the beam current that resembles EHV behaviour. With this, HVI information is optimum to be used in geometry compensations.

4.4.2.

Geometry compensation.

4.4.2.1. Width (W) and height (H) compensations Through R425 the HVI signal is taken to the video processor pin 50 (IC400). This video processor does width compensation by decreasing o increasing the E/W output and the height compensation by decreasing or increasing the level of the vertical sawtooth output. 4.4.2.2. Phase compensation. The second phase comparator (PHI-2) corrects the delay produced by the final lines transistor, but there are other phenomena which affect the horizontal phase and that are not corrected by PHI-2. This can create distortions in the picture because of phase deviation. The HVI signal is taken through R417 to the video processor pin 42 (IC400). To this pin, the capacitor providing the time constant to PHI-2 is connected. Extracting current from this pin makes the ipicture move to the left, and injecting current moves the picture to the right. Values of R417, C418, R416, D401 and D402 are adequate to minimise distortions due to phase deviations. The purpose of D401 and D402 is to prevent a phase shift to the right when the beam current is very low.

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Service Manual CHASIS 2114 (EB5-C Series)

4.4.3.

ACL Descriptión

ACL circuit is the average beam current limiter. The aim of this circuit is to limit the maximum average beam current. When the BCL signal is lower than 3.1 V, IC400 starts decreasing contrast. When this voltage falls below 1.8 V, brightness also decreases. 4.4.3.1. BCL signal description. R682, R683, R688, C674, C675 and C680 make a low-pass filter for the BCI signal. From this a D.C. is obtained and applied to the base of Q673, which is configurated as an emitter-follower. At Q673's emitter the BCL signal is available. This reaches IC400 pin 22 through Q674 and C435. D683, R694 and R698 improve the speed of the response to small load steps. D674, D675 and R654 improve the speed of the response to big load steps (in the case of changing from dark to white picture).

4.4.4.

PBL description.

PBL circuit is assembled in the models that incorporate steel mask CRT. It is not mounted when the model has an Invar mask tube. When the situation arises that there is a dark picture with highly bright contents in small areas, the average beam current is very low, so there is no limitation but in these areas the beam current is locally high, however. This is not dangerous, neither for the circuit nor for the tube, but the drawback of this situation remaining for a certain time, is that the TRC's shadow mask gets hot, thus suffering thermal expansion and deviating the electron beams paths consequently, and spotting on the wrong phosphors. This effect is known as "Doming" and affects the purity of the colour. "Doming" disappears some time after the picture causing the mask heating has disappeared, i.e. when the shadow mask is cooler. PBL is a circuit that detects situations in which there is a small bright area that can cause "Doming" and limits the contrast with the aim of minimising the effect. 4.4.4.1. PBL signal Generation. The current circulating back from the CRT (aquadag) produces a voltage drop in R670, which when reaching 1.2V, triggers the conduction of Q670, D681 and Q671. At the emitter of Q671 there is a negative polarisation voltage so that when Q671 is conducting, altogether behaves as a current source. The voltage divider made up of R681 and R697 fixes a voltage level of 2.5V in the PBL signal provided that Q671 is not conducting. In the case of Q671 conduction the PBL signal voltage decreases. R681, C676, R680 and C679 work as a low-pass filter to extract a D.C. voltage. This voltage is 2.5V when there is no Doming, and less than 2.5V when there is Dooming, being then proportional to it. 4.4.4.2. PBL blanking. Due to a parasitic capacitive coupling between the deflection yoke and the aquadag, 0Q670 might enter conduction during flyback without being a Doming situation. In order to avoid this, the network made up of L655, R673, C667, R686 and C672 equalises the parasitic pulse, preventing Q670 from conducting during the blanking interval. Because of deviations in the parasitic capacitive coupling between the deflection yoke and the aquadag, a secondary blanking circuit, made up of D676, D677 and D678, blocks conduction of Q670 and Q671. 4.4.4.3. Contrast reduction The PBL signal is taken to a microprocessor's A/D converter port. The microprocessor decreases the video processor's contrast register when PBL is lower than 2.5V. Contrast reduction is done with a time constant that is programmable in service mode (PBL SPEED). The time constant value is related to the time constant of the CRT's mask expansion. It is possible to see in the picture the contrast-value reduction if, while in "Factory" mode, we press keys "-/-" and the green one. This value must be equal to zero for flat picture patterns.

4.5.

Vertical Deflection

The vertical deflection amplifier is LA7846N for all models from 21'' to 29''. It is an amplifier designed for big screens as it can work with vertical deflection currents up to 3 App. It is from the same family of amplifiers as LA7840 and LA7841, which are used in Sanyo chassis EC7-A and EC7-B. IC400 vertical output signal is balanced and in current mode. Because of that, there are two outputs, +V_DRIVE and -V_DRIVE. Their currents are amplified in IC701 and applied to the vertical deflection yoke. R702, R711 and R712 define the height and the centre. It is mandatory for them to be of metal film type to prevent geometry deviations due to temperature variations. The amplifier's output coupling is in D.C. (there is no coupling capacitor) as IC400 has no N/S linearity correction. Having no coupling capacitor and the amplifier's output configuration not being a transistor bridge, symmetrical supply must be used.

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Service Manual CHASIS 2114 (EB5-C Series)

4.5.1.

Vertical deflection supply.

The vertical amplifier supply is symmetrical and it is the same for scan for blanking. Supply during flyback is internally generated by means of a switch. B4+S: Vertical voltage supply during the upper half of the screen. B4-S: Vertical voltage supply during the lower half of the screen. Their value depends on the TRC type. For the 21" models, it is about 15V and for 25" and 28" models, it is14V. Due to power supply leaving voltages in a high state in STANDBY, and the vertical amplifier having a certain quiescent current consumption (with inputs at zero), the vertical supply is switched in STANDBY by Q850, Q852 and their periphery.

4.5.2.

Vertical deflection protection.

Whenever there is a potentially dangerous failure in the vertical deflection, the vertical flyback disappears The vertical flyback is fed back to pin 18 of IC400 by means of signal V_GUARD. In the case of missing vertical flyback pulses, the video processor (IC400) activates the NDF bit, which is periodically checked by the microprocessor through the I2C bus. The action performed by the microprocessor when reading the indicated failure is to turn to ERROR2. Vertical protection is not operative in these cases. · · · · V-STAT, S-STAT or I2C BUS is selected in the service mode. The TV set is in standby During TV set on/off transients. Forced start mode.

4.6.

Tuner and tuning circuit

Tuner TU250 allows the reception of all broadcast as well as cable TV channels. The whole frequency range is distributed among three bands (LB, MB y HB) which selection is done by the microprocessor (IC100). These signals activate Q252, Q253 and Q254 respectively, which then feed the corresponding circuit section inside the tuner. There will only be one active signal at one time. Tuning function is voltage synthesis type: The channel tuned depends on the tuning voltage. This is a D.C. voltage in the 0V to 28V range approximately. This voltage is originally generated by the microprocessor as a pulse-width modulated signal (PWM) which is later amplified and low-pass filtered by circuit made up of D250 and Q251 and their periphery. The automatic frequency control (AFC) is performed by the microprocessor by correcting the tuner voltage as a function of two bits, provided by the video processor via I2C, which contain the information about the difference between really tuned frequency and the right frequency. (See paragraph "Video I.F." below). AGC voltage controls the tuner gain. This D.C. voltage is generated by IC400. (See also paragraph "F1 video" ). The tuner I.F. output is fed to the two surface acoustic wave filters, SF200 and SF201 (picture and sound respectively).

4.7.
4.7.1.

Video signal processing.
Video Processor

The video processor is IC400. Inside IC400 the following blocks are found: " " " " " " " Video I.F. QSS (Quasi Split Sound) I.F. Horizontal and vertical synchronisation Geometry Processor Video filters and switches Colour decoder RGB processing (inside which Pack I is found)
3

4.7.1.1. Video processor versions The available video processor versions are: TDA8874: Used in models without pack i TDA8874: Used in models with pack i
3 3

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Service Manual CHASIS 2114 (EB5-C Series)

4.7.1.2. Video I.F. In the video I.F. block, the following sections can be found.: " " " " " " " I.F. Amplifier PLL and VCO demodulator Video Buffer AGC Tuner AGC AFC Video identification

The tuner (TU250) signal output is applied to the surface acoustic wave filter SF200, which only lets the picture carrier and information to pass through. SF200 output is applied to the I.F. amplifier symmetrical input. The I.F. signal is demodulated by a PLL detector. This PLL is used to generate a reference signal in phase with the video carrier. Demodulation is achieved by multiplying this reference with the I.F. signal. The demodulator can handle positive video (in the case of SECAM L) and negative video (the rest of the TV systems.) VCO does not need adjustment nor external coild. The frequency selection is done by the microprocessor via 2 I C bus. Components related to PLL are the connected to the pin5 (PLLLF) The video buffer adapts levels and output impedance so that the signal can be treated afterwards. The demodulated video is supply on pin 6 (IFVO) and has a typical level of 2.5 Vpp. AGC controls the I.F. amplifier gain to achieve a constant video amplitude. The demodulated video is fed to detector, which directly controls the gain of the I.F. stages. Tuner AGC decreases tuner gain when receiving strong R.F. signals. The level at which tuner gain reduction 2 begins, is programmable via I C (AGC in service menu). AFC information is available in two bits that are accessible by the microprocessor via I C. This information is used for searching and tracking broa