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October 1997
FDC6320C
Dual N & P Channel , Digital FET
General Description Features
These dual N & P Channel logic level enhancement mode field N-Ch 25 V, 0.22 A, RDS(ON) = 5 @ VGS= 2.7 V.
effec transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density P-Ch 25 V, -0.12 A, RDS(ON) = 13 @ VGS= -2.7 V.
process is especially tailored to minimize on-state resistance.
The device is an improved design especially for low voltage Very low level gate drive requirements allowing direct
applications as a replacement for bipolar digital transistors in operation in 3 V circuits. VGS(th) < 1.5 V.
load switching applications. Since bias resistors are not
Gate-Source Zener for ESD ruggedness.
required, this dual digital FET can replace several digital
>6kV Human Body Model
transistors with difference bias resistors.
Replace NPN & PNP digital transistors.
SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16
4 3
5 2
6 1
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter N-Channel P-Channel Units
VDSS, VCC Drain-Source Voltage, Power Supply Voltage 25 -25 V
VGSS, VIN Gate-Source Voltage, 8 -8 V
ID, IO Drain/Output Current - Continuous 0.22 -0.12 A
- Pulsed 0.5 -0.5
PD Maximum Power Dissipation (Note 1a) 0.9 W
(Note 1b) 0.7
TJ,TSTG Operating and Storage Tempature Ranger -55 to 150