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DVD-2012
R

Service Manual - DVD-2012

A
24.576MHz Page Index 0 1 74AC04 3 27MHz 5 6 7 Video OUT Audio OUT (Debug) UARTs (Debug) Flash Emulator 96kHz Clock 9 10 RESET 8 IDE / DVD LOADER 4 2 EM8500 Main I/Os EM8500 Power and decoupling EM8500 Sys SDRAM + Flash EM8500 MPEG SDRAM + UART Block Diagram/Notes Power, FIP input, Reset, 96kHz clock

B

C

D

E

4

4

Analog AUDIO
DAC Audio OUT

Right SDRAM 2Mx32

Left

Op-Amp

Digital AUDIO
S/PDIF EEPROM

Optical

Coax. EM8500
Video DACs

3

Composite

3

TV OUT HDTV OUT SDRAM 2Mx32
PWR: 3.3V/1.8V

S-Video

Y

C

Y

Component

Pr

Pb

FLASH 2MB IDE Connector F.I.Pannel

Emulator conn.

2
COM 1 COM 2 Debug Only

2

1

1

A

B

C

D

E

A

B

C

D

E

Reset
Vcc3V3 C96 Z1 AMS1117-1V8 U11A U11F 2 74HC04 Vcc1V8 X5 3 2 1 1 24.576MHz 1 C101 10pF 2 22 IDE_RESET# 2 C100 00 1 2 2 10pF 1 R56 R47 74HC04 13 12 1 R75 2 33 AUDCLK96 22 R46 RESET# VIN VCC3v3 GND OUT 4 4 1 R74 2 1M 1 R76 2 220 1 2 0.1uF

1.8V Regulator

24.576MHz

Vcc3V3

2

4
14 1 7

D12 Dual

3

10K

R72

47K

R70

4

1

U11B

U11D

10K

R71

3

4

9

8

R73 1K NOT FITTING

74HC04

74HC04

J14

1 2

U11C

5

6

10uF/35V C102

HDR1x2

74HC04 U11E

11

10

74HC04

3
22 C81 C83 R91

Panel cn
Vcc5V AUDP5V

3

J16

L26 BEAD

J_FIP_IR 10uF/35V Vcc12V 22 C84 C10 R90 AUDP12V 0.1uF

GND IR CLK CS DATA

1 2 3 4 5

L27 BEAD

J_FIP_CLKO

L28 BEAD

J_FIP_FSTB

HDR1x5

L29 BEAD

J_FIP_DATA Vcc5V 2 Vcc5V 2 R38 47k 1 1 R?? 0R jump for power standby direct STBY# 1 R40 2 1 R39 10K STANDBY

Power
Vcc12V 0.1uF Neg12V

Input

2
10uF/35V

Vcc3V3

Vcc5V

2
2 1k 1 3 Q8 2 2N3904

J10

BEAD

L19 STANDBY

Stby +3.3V

BEAD

L20

+5V Neg12V 22 R92

BEAD

L21 AUDN12V

+12V

BEAD

L22

-12V

1 2 3 4 5 6 7 8 C82 10uF/35V

BEAD

L23

47uF/25V C206

47uF/25V C126

47uF/25V C208

CONFIDENTIAL

1

47uF/25V C210

0.1uF

C9

HDR1x8

1

A

B

C

D

E

A

B

C

D

E

VSYNC HSYNC

E2 E3 F4 F5 D3 E4 D2 D1 C2 C1 B1 E5 D4 D6 C3 B2 D7 A2 B3 C4 A1 C5 D9 A3

D5

B4 C6 C7

4
P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 PCLK VCLK CVBS Y U G1 TV_U/B/CVBS TV_V/R/C G5 H3 TV_Y/G/Y VSYNC HSYNC VVLD J1 TV_CVBS

U1A

D8

4

VIDEO OUT TV OUT
V

Vcc3V3

A4 C8 ACLK1 SCOUT1 SDOUT1 SFOUT1 K3 K2 M1 L2 AMCLK ASCLK ADATA ALRCK

PIO1_8 PIO1_7

10K

R67

AUDIO OUT

ACLK2 SCOUT2 SDOUT2 SFOUT2

K5 M5 J5 L5 1 1 1 1 T1 T2 T3 T4

O3P O3N O4P O4N

J_FIP_CLKO ACLK3 SCOUT3 SDOUT3 SFOUT3 N5 P6 R7 R5 1 1 1 1 T5 T6 T7 T8 O5P O5N O6P O6N

3
SCIN EM8500 DAMCK DADAT DABCK G6 J4 K1 AUDCLK96

J_FIP_DATA J_FIP_FSTB

V14 W13 W14 Y13

FCLK FDIN FDOUT FSTB

FIP

3

I2S_SCLK I2S_SDATA I2S_LRCLK

Y14 T15 U15

I2S_SCLK I2S_SDATA I2S_LRCLK

I2S

I2S IN-OUT

Vcc3V3

24C0x

J_IDE_CS0# J_IDE_CS1# J_IDE_IRQ J_IDE_DIOW# J_IDE_DIOR# J_IDE_DMARQ J_IDE_DACK# J_IDE_RDY J_IDE_NPCBLID J_IDE_PD[15..0] S/PDIF OUT J3 I2CM_SCLK I2CM_SDATA U14 T14

N16 Y20 R18 P16 R17 T18 V18 U18 V19

SPDIFOUT

1 2 3 4 I2CM_SCK I2CM_SDA

A0 A1 A2 VSS U2

CS0 CS1 IRQ IOW IOR DMAREQ ACK IORDY NPCBLID

VCC WP SCL SDA

8 7 6 5

I2CM_SCK I2CM_SDA

Vcc3V3

2

J_IDE_PD0 J_IDE_PD1 J_IDE_PD2 J_IDE_PD3 J_IDE_PD4 J_IDE_PD5 J_IDE_PD6 J_IDE_PD7 J_IDE_PD8 J_IDE_PD9 J_IDE_PD10 J_IDE_PD11 J_IDE_PD12 J_IDE_PD13 J_IDE_PD14 J_IDE_PD15 PIO_14 PIO_13 PIO_12 PIO_11 PIO_10 PIO_9 PIO_8 PIO_7 PIO_6 PIO_5 PIO_4 PIO_3 PIO_2 PIO_1 PIO_0 D17 A16 B16 C16 D16 B15 FLASH_CRT C15 D15 D13 A14 B14 A15 D14 C14 FLASH_CRT E15

W18 Y17 V17 U17 V16 W16 W15 V15 Y15 Y16 U16 T16 T17 W17 R16 Y18

HD_0 HD_1 HD_2 HD_3 HD_4 HD_5 HD_6 HD_7 HD_8 HD_9 HD_10 HD_11 HD_12 HD_13 HD_14 HD_15

IDE

RP3 1 2 3 4

4x10K 8 7 6 5

2

J_IDE_PA[2..0]

1 2 3 4

HA_0 HA_1 HA_2

J_IDE_DCLK

P17

DVD_CLKIN

RP1 4x10K 8 7 6 5 8 7 6 5

1 2 3 4

J_IDE_PA0 J_IDE_PA1 J_IDE_PA2

Y19 P18 W19

SCT-169 SCT-ENB VGAEN# STBY# nSELYUV MUTE J_FIP_IR

RP4 4x10K

1

1

A

B

C

D

E

A
Vcc1V8

B

C

D

E

C18

C26

C27

C19

C20

C23

C28

C31 0.1uF 0.1uF

0.1uF

0.1uF

0.1uF

10uF/35V

10uF/35V

U1C

Vcc3V3 V_DAC_3V3 Vcc3V3 G4 H5 H2 G2 F1 C38 C39 C40 C41 C42 C43 C44 C45 C36 C24 C52 C53 C56 C57 C58 C60 C61 Use 200ohm if single terminated 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 100 0.1uF C17 R9 F3 F2

10uF/35V

4

0.1uF

C32

4

C62

C29 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

0.1uF C106

0.1uF C172

VIDEO DACs
RSET VREF

10uF/35V

10uF/35V

10uF/35V

E12 E13 T12 T13 T10 T9 U9 U10 E6 E7 E8 U7 T7 L1 AVDD_D_33 AVDD_C_33 AVVD_Y_33 AVDD_U_33 AVDD_V_33 10uF/35V AVSS_D CVBS_VSS YB UB VB VGND R9 SET VIDEO OUTPUT LEVEL E1 J2 H4 H1 G3

C8

3V3 3V3 3V3 3V3 3V3 3V3 3V3 3V3 3V3 3V3 3V3 3V3 3V3 VCC_3V3

3

0.1uF C175

0.1uF

C35

3

Vcc1V8 EM8500 RESET# PLL_ENABLE XOUT A11 B11 B13 B8 W10 B7 B5 B6 A5 Y9 T17 GND JTAG_TCK CLK_OUT 1 R8 2 22 XIN 1 C5 27pF 1 27MHz A13 Vcc3V3 Y8 RESET# 1 R1 X1 2 1 2 2 XOUT 2 1M

OSC.
XIN CLK_OUT TCK CLK32K TDO NTRST TDI TMS SCAN_MODE

2

K16 M16 L16 D11 T11 U11 V11 W11 C9 C10 D10 E9 E10 V10

1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8 1V8

C6 27pF

2

Vcc3V3 1 L4 26@100 2 C16 C12 C13 C14 0.1uF 0.1uF 0.1uF VGND 10uF/35V C15 0.1uF

V_DAC_3V3

Vcc1V8

L1 1 26@100 2

V_PLL_1V8

2 0.1uF

D12 A12

AVDD_P1_18 AVDD_P2_18

PLLs

1 C1

B12 C12

AVSS_P1 AVSS_P2

1

E14 F14 R15 P15 E11 J11 J12 K11 K12 L11 L12 M11 M12 J9 J10 K9 K10 L9 L10 M9 M10 F7 T8 U8 V7 W7 K4

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VSS

1

A

B

C

D

E

A
J20 4x22 RP10 IDE_PD8 IDE_PD7 IDE_PD9 R105 10K 1 2 3 4 4x22 RP11 Vcc3V3 1 2 3 4 1 2 3 4 4x22 RP12 IDE_CSEL IDE_NPCBLID IDE_PA2 IDE_CS1# 1 2 3 4 4x22 RP13 IDE_PD2 IDE_PD14 IDE_PD1 IDE_PD15 IDE_PD4 IDE_PD12 IDE_PD3 IDE_PD13 IDE_PD6 IDE_PD10 IDE_PD5 IDE_PD11 J_IDE_PD7 J_IDE_PD6 J_IDE_PD5 J_IDE_PD4 J_IDE_PD3 J_IDE_PD2 J_IDE_PD1 J_IDE_PD0 IDE_RESET# IDE_PD7 IDE_PD6 IDE_PD5 IDE_PD4 IDE_PD3 IDE_PD2 IDE_PD1 IDE_PD0 IDE_PD8 IDE_PD9 IDE_PD10 IDE_PD11 IDE_PD12 IDE_PD13 IDE_PD14 IDE_PD15 J_IDE_PD8 J_IDE_PD9 J_IDE_PD10 J_IDE_PD11 J_IDE_PD12 J_IDE_PD13 J_IDE_PD14 J_IDE_PD15

B

C

D

E

IDE_RESET#

IDE_PD8 IDE_PD7 IDE_PD9

J_IDE_PD8 J_IDE_PD7 J_IDE_PD9

8 7 6 5

J_IDE_PD[15..0]

4
J_IDE_CSEL J_IDE_NPCBLID J_IDE_PA2 J_IDE_CS1#

IDE_PD6 IDE_PD10 IDE_PD5 IDE_PD11

J_IDE_PD6 J_IDE_PD10 J_IDE_PD5 J_IDE_PD11

8 7 6 5

4
1 R107 2 0

IDE_PD4 IDE_PD12 IDE_PD3 IDE_PD13 J_IDE_DMARQ J_IDE_DIOW# R106 10K J_IDE_DIOR# J_IDE_RDY R108 X 10k J_IDE_DACK# R109 10K J_IDE_IRQ J_IDE_PA1 J_IDE_PA0 R108 J_IDE_CS0# NOT FITTING

J_IDE_PD4 J_IDE_PD12 J_IDE_PD3 J_IDE_PD13

8 7 6 5

J_IDE_PD0 J_IDE_PD1 J_IDE_PD2 J_IDE_PD3 J_IDE_PD4 J_IDE_PD5 J_IDE_PD6 J_IDE_PD7 J_IDE_PD8 J_IDE_PD9 J_IDE_PD10 J_IDE_PD11 J_IDE_PD12 J_IDE_PD13 J_IDE_PD14 J_IDE_PD15

IDE_PD2 IDE_PD14 IDE_PD1 IDE_PD15

J_IDE_PD2 J_IDE_PD14 J_IDE_PD1 J_IDE_PD15

8 7 6 5

X

IDE_DMARQ IDE_DIOW# IDE_DIOR# IDE_RDY IDE_DACK# IDE_IRQ IDE_PA1 IDE_PA0 IDE_CS0# IDE_DSAP# IDE

J_IDE_PA[2..0] GND GND GND

IDE_PD0 IDE_DMARQ IDE_DIOW# IDE_DCLK 1 2 3 4 4x22 RP14 1 2 3 4 4x22 RP15 IDE_DIOR# IDE_RDY IDE_DACK# IDE_PA1 IDE_PD0 IDE_DMARQ IDE_DIOW# IDE_DCLK

J_IDE_PD0 J_IDE_DMARQ J_IDE_DIOW# J_IDE_DCLK

8 7 6 5

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

2 4 6 8 10 12 14 16 18 20 KEY 22 24 26 28 30 reserved 32 34 36 38 40

J_IDE_PA0 J_IDE_PA1 J_IDE_PA2

IDE_DIOR# IDE_RDY IDE_DACK# IDE_PA1

J_IDE_DIOR# J_IDE_RDY J_IDE_DACK# J_IDE_PA1

J_IDE_IRQ 4x22 RP16

J_IDE_IRQ

8 7 6 5

GND

J_IDE_DIOR#

J_IDE_DIOR#

3
1 2 3 4 4x22 RP17 IDE_IRQ IDE_PA0 IDE_CS0# IDE_DSAP#

J_IDE_DIOW#

J_IDE_DIOW#

IDE_CSEL IDE_NPCBLID IDE_PA2 IDE_CS1# 1 2 3 4

J_IDE_CSEL J_IDE_NPCBLID J_IDE_PA2 J_IDE_CS1#

8 7 6 5

IDE_CSEL IDE_NPCBLID IDE_PA2 IDE_CS1#

3

J_IDE_RDY

J_IDE_RDY

J_IDE_CS0#

J_IDE_CS0#

IDE_IRQ IDE_PA0 IDE_CS0#

J_IDE_IRQ J_IDE_PA0 J_IDE_CS0#

J_IDE_CS1#

J_IDE_CS1#

8 7 6 5

J_IDE_DMARQ

J_IDE_DMARQ

J_IDE_DACK#

J_IDE_DACK#

Do Not Stuff Shorted on PCB

J_IDE_NPCBLID

J_IDE_NPCBLID

J_IDE_DCLK

J_IDE_DCLK

RP25

Vcc3V3

A/V
J23

2
R114 X 4.7k

I2S_SDATA I2S_SCLK I2S_LRCLK

I2S_SDATA I2S_SCLK I2S_LRCLK

5 6 7 8

4 3 LDR_I2S_DATA 2 LDR_I2S_CLK 1 LDR_I2S_FRAME

I2S_SDATA I2S_SCLK I2S_LRCLK

2

4x22

Vcc3V3

Vcc3V3

26@100

R116

L31

1

IDE_PD7 IDE_PD6 IDE_PD5 IDE_PD4 IDE_PD3 IDE_PD2 IDE_PD1 IDE_PD0 IDE_DIOW# IDE_IRQ IDE_CS1# IDE_RDY IDE_DCLK 1 3 5 7 9 11 13 15 17 19 21 23 25

2

R113 R116 NOT FITTING IDE_RESET#

U23 IDE_DMARQ IDE_PA0 IDE_DACK# IDE_NPCBLID IDE_16MHz

4

VDD OUT

3

1 R161

2 IDE_16MHz 22

GND

2

1
LDR_I2S_FRAME LDR_I2S_CLK LDR_I2S_DATA

OSC 16MHz U23A

X 4.7k

2 1 C169 0.1uF

J_IDE_DIOW#

1

4

VDD OUT

3

NOT FITTING

GND

2

OSC 16MHz

SDT7 GND 2 SDT6 GND 4 SDT5 GND 6 STD4 GND 8 STD3 GND 10 STD2 GND 12 STD1 GND 14 STD0 GND 16 DREQ# GND 18 DACK# GND 20 DERR GND 22 DBGN GND 24 DCLK GND 26 JST 26FMN-SMT-TF J25 GND 1 NC 2 HRST 3 GND_D HOST 4 TxD 5 RxD 6 SCLK 7 RDY_HIF 8 GND 9 16M 10 GND 11 EMPH 12 C2PO 13 LRCK 14 BCK 15 CDDAT 16 SPDIF JST 16FMN-SMT-TF GND

A

B

C

D

E

A
Use 00-ohm resistor to by-pass the Mux C-Pr VBS-Y CVBS-Pb L2 FB VMODE CVBS_out BEAD 2 U31 SVid-C BEAD BEAD L33 3 4 L32 S1A S2A SVid-Y S1B S2B Pb 5 7 8 9 6 S1C S2C 11 10 5 6 Y SVid-Y 2 3 Pr SVid-C C-Pr VBS-Y 7 DB DC DD GND PI5V330 nSELYUV 9 12 8 CVBS-Pb L3 FB VFMT 16 4 VDD DA L10 1 Vcc5V J9 RCA+DIN4 stacked R84 Pb 0R R82 R83 0R 0R Y SVid-Y R80 R81 Pr SVid-C 0R 0R

+12V

R13

R15

2K2

2K2

R19 2K2

3

SCT-169

1

Q3

R16 1K5

Composite

3904

2

R35 2K2

GND

VGAEN#

1

3

VCC

R17 220R

R18 220R

S-Video

Q6 3904

R36 1K

SCT-ENB

1

3

GND S1D S2D EN IN1/IN2 14 13 15 1

2

Q7 3904

2

GND

THESE COMPONENTS ARE POPULATED ONLY WHEN IF SCART USED LINK CONCEPT TECHNOLOGY
Optional

Component
J8 Stacked RCA 1

SCART VIDEO FORMAT DRIVERS
Pr Y Pb BEAD BEAD BEAD L6 L8 L9 3

1
SCART TYPE 1 (CVBS/RGB) ONLY: 0..0.4V: CVBS MODE [0.2V] 1..3V: RGB MODE [2.0V]

R
2

1
G

SCART TYPE 1 (CVBS/RGB) & TYPE 2 (Y/C): 0..2V: "TV" MODE [0.3V] 5..8V: "AV" WIDE SCREEN MODE (SCART) [ 6.5V] 9.5..12V: "AV" NORMAL SCREEN MODE (SCART) [12V]

B

4 C-Pr VBS-Y CVBS-Pb CVBS_out DACL DACL DACR CON13 DACR GND VFMT VMODE CVBS_out Pr Y Pb BEAD L14 BEAD 2 2 L13 HSYNC VSYNC Vcc3V3 C77 C78 C79 C80 3 1 D8 BAT54S 1 3 D9 BAT54S SCART OUTPUT CONNECTER R G B VGND 13 12 11 10 9 8 7 6 5 4 3 2 1 J1A 330pF 330pF 330pF 330pF

22pF

C73

TV_V/R/C

1.8uH

L5

22pF

C74

TV_Y/G/Y

1.8uH

L7

22pF

C75

TV_U/B/CVBS

1.8uH

L11

22pF

C76

TV_CVBS

1.8uH

L12

Vcc3V3

2

2

2

R59 R60 R61 R62

3

3

3

2

3

75 75 75 75

1

1

1

VGND

No Stuff for Single termination

1

A

5

D4

Dual

Dual D1

Dual D2

Dual D3

A
330pF R68 4.7k 10K AUDP12V 8 2 1 R41 3 4 U5A 4558 1 R149 Stacked RCA J4 2 4 L2 R2 L1 R1 . . . . When SCART output R41,R49 changed to 1k from 100k 1 3 RIGHT 5 6 7 8 LEFT D17 1N4148 MUTE 0: sound ON 1: MUTE AUDP12V 8 5 7 R49 6 4 U5B 4558 R50 100K C70 1 R150 2 1 1k 3 Q5 2 2N3904 R5 4.7k R69 4.7k 330pF AUDN12V 10K 10uF/35V 1 R152 2 1k DACR C68 MUTE_A 100K 2 1 1k 3 Q4 2 2N3904 AUDN12V 10uF/35V 1 R151 2 1k DACL C65 R37 C63

MIC_IN

R6 4.7k

ANALOG AUDIO OUT

AUDP5V

AUDP5V

ADATA ASCLK ALRCK AMCLK

8 9

10uF/35V

C33

6

10uF/35V

C34

WM8725/PCM1725 2 DATA VCC 3 SCLK L 1 LRCK 14 MCLK R 10 MUTE 12 DM CAP 13 I2S GND

5 7

10uF/35V

C30

U38

MIC_IN

AUDP5V AUDP5V Q2 3906 MUTE_A 1 AUDN12V R12 + C2 220uF D6 1N4148 R11 470 + 100k 2 R7 100K D5 1N4148

AUDP12V

AUDN12V

J7

1

1

R2

1K

1 2 3 4 5 6

MIC_IN

CON6

+12v

1

3

Q1 3904

R3 10k C3 47uF

R4 1K

MIC SIGNAL INPUT

2

DIGITAL AUDIO OUT
J6 S/PDIF 0.1uF 2 1 RCA1x1 Orange 120 R55 C71 220 R54

SPDIFOUT

0.1uF C72

VCC5V J7 2 1 3 VCC Vin GND Optical

GP1FA550TZ

A

A

B

C

D

E

Vcc5V 1 2 C125 10uF/25V GND 1 2 C129 0.1uF Vcc5V

4

4

GND C131 1 C1+ 0.47uF 4 1 C1V+ 1 2 C138 0.47uF GND 3 VCC SHTDN DI1 DI2 DI3 RO1 RO2 RO3 RO4 RO5 DO1 DO2 DO3 RI1 RI2 RI3 RI4 RI5 DS14C535 22 21 20 19 18 17 16 15 U2_DTR U2_RTS U2_TXD U2_RXD U2_CTS U2_DSR U2_CD U2_RI GND GND 23 U1_DTR U1_RTS U1_TXD U1_RXD U1_CTS U1_DSR U1_CD U1_RI J_UART2_DTR J_UART2_RTS J_UART2_TXD J_UART2_RXD J_UART2_CTS J_UART2_DSR J_UART2_CD J_UART2_RI 7 8 9 10 11 12 13 14 J_UART2_DTR J_UART2_RTS J_UART2_TXD J_UART2_RXD J_UART2_CTS J_UART2_DSR J_UART2_CD J_UART2_RI 5 27 C2VVcc5V GND 0.47uF 26 25 C2+ 0.47uF C134 1 2 1 2 C136 0.47uF Vcc5V 2 2 1 C133 0.47uF 2 28 1 2 1 2 C130 0.1uF C137

U17

U18

2 1 C135 0.47uF

2

C1+

C2+

28

Vcc5V

C132

1

2

4 1

C1V+

C2V-

26 25

Vcc5V

0.47uF

3

VCC

GND GND

5 27

3

23

SHTDN

J_UART1_DTR J_UART1_RTS J_UART1_TXD J_UART1_RXD J_UART1_CTS J_UART1_DSR J_UART1_CD J_UART1_RI

J_UART1_DTR J_UART1_RTS J_UART1_TXD J_UART1_RXD J_UART1_CTS J_UART1_DSR J_UART1_CD J_UART1_RI

7 8 9 10 11 12 13 14

DI1 DI2 DI3 RO1 RO2 RO3 RO4 RO5

DO1 DO2 DO3 RI1 RI2 RI3 RI4 RI5

22 21 20 19 18 17 16 15

3

DS14C535

U1_DTR U1_TXD U1_RXD U1_CD

U2_DTR U2_TXD U2_RXD U2_CD

10

1 2 3 4 5

10

2
GND

1 2 3 4 5

2
case J19 case DSR RTS CTS RI CD RxD TxD DTR GND GND

case

J18

CD RxD TxD DTR GND

UART1

UART2

case

11

6 7 8 9

DSR RTS CTS RI

11 GND U2_DSR U2_RTS U2_CTS U2_RI

GND

U1_DSR U1_RTS U1_CTS U1_RI

1

6 7 8 9

1

A

B

C

D

E