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V /V CCD BAT

VC CA1/ V / V c CCD Os

VSYN VR F

LCD CON .
- KS0 723( ± )
Res et _B D[ 7: 0] A(0)

Spk r+ Spk rLed_ct l Vbat Lcd_Se

M4 6
CS LCD EL 3/ _S M r _En M TO N i O R_E S YS_CLK F T _R RX CLK RXD A AT RXR E AT C AT DCR E D AT ECD A E AT NCD A CDC CLK C AT TLR E C AT TLD A RE AT SPD A CTLCLK

20420
Rxm xo C MC ERA I FI LT ER Cl k_Rqs t Res et _B Sys _Cl k F_Rt Rx_C k l Rx_D at Rx_R t Cdc _Rt Dcdr_Dat Enc dr _D at Cdc _Cl k Cnt l _Frm Cnt l _Dat Rspns _D at Cnt l _Cl k CLK_RQS T RE T_B SE SY S_CLK F_RT RX LK _C RX AT _D RX T _R CD C_RT DE C_DAT EN C_DAT CD C_CLK CLT_FRM CT L_DAT N _I CT L_DAT UT _O CT L_CLK R F_P X_I R F_M X_I R _I f + x R _I f x RX O M F 2+ I F 2I F 20+ F 20385. 4M z H m xer & i Am p IFN I + I FI N I I ( 14. 6M z ) I H I

RF13 7

T FS4 00 B 7 (SA W 4 00 M Hz)
R i f i n+ f O 2 UT O 1 UT IN 2 IN 1 R i f i nf

RF21 0
FI R ST M XER I & LN A
Hi ghband ( M 46) Rx_E n1 ( 20420) Rx_G n0 ( 20420) ai

SAW FI L TER FAR F5 C E G _R sm x SAW FI L TER FAR F5 C E G : 935~960M SM Hz D R cs_ x

A[ 20: 0] D[ 15: 0]

TX 1 _EN RX 1 _EN S _EN YN

Tx_E n1 Rx_E n1 Syn_En

TX NA _E RX A EN SX A EN

Rxl o1

MEM ORY
- 16M F SH & LA 2M S M RA - ON C P( S RP) E HI HA

Fl ash_S el Read W te ri Cl k _Rqst Res et _B Audi o_F as h l Upper _B t e y Lower _B t e y Ram _Sel S_Dat S_Cl k

EEP ROM
- 126K

A[ 20: 0] D[ 15: 0] FLAS EL H_S RD W R CLKR EQ RE T SE CS AUD LAS 4/ _F H BS 1 BS 0 RA _SEL M SD A SC L

Tx_En0 TX 0 _EN T _E x n2 TX 2 _EN Syn_Ref S YN_RE F RX I N Rx_G n0 _GA 0 ai S YN_CLK S YN_DA T S YN_EN 1 S YN_LC K Syn_Cl k Syn_Dat Syn1_En SY N0_LC K

FR EF
CLK DA TA LE LD

UH F_TUN E VH UN F_T E V 6 CC R 1 ES R 2 ES V 5 CC

U _Tune hf H ghband i Vhf _Tune

D S : 1805 ~1880 M z C H AN T _SWIT CH ( LM C36- )
RX SM _G RX CS _D TX SM _G TX CS _D A NT Gsm _Tr V C1 V Dcs _Tr C2 V C3 V C4 Hi ghband ( M 46) Tx_E ( 20420) n0

M C 173 H-

OSC 3 01 RXV C O

JTAG
TRE S TCLK TM S TD I TD O

Txl o1 LOI N LO N I R

Kbd_St rb[ 7: 0] Kbd_Rt n[ 2: 0] KB RB[ 7: 0] DS KB TN[ 2: 0] DR RE D_LED N _E GR N_LED EE LE D_CNT L FLI P S _SN Psw_Sns PS _SNS W

G ND

G : 890~915M SM Hz Buzze r ci r cui t
TX L_P TX L_M TX_Q_P TX_Q_M HI _BA ND_SE L Tx_I + Tx_I Tx_Q + Tx_Q Hi ghband Txi f + Txi f Txm op Txm om I+ IQ+ QTXI N T N XI R Txr f 1

MM I C ON .
- 30 P N I

Red_Led_E n Green_Led_Eb Lde_Ct l Fl i p_Sns

Bu zzer _En

M QW0 10 Tx V CO
T cpo l O UT2 VC O UT1

RM 008
GSM N I DCS N I Gsm _Pa G O SM UT Dcs _Pa D UT CSO

DU AL_CO LER UP ( LDC15D ) FL FH FL_O UT FH UT _O

D S : 1710 ~1785 M z C H

TLCP O

XTL0 XTLI

X- t al
32. 768ß' TX F I + TX F I TX O M+ TX O MG 369M SM Hz D 358M CS Hz Hi ghband Tx _En1

SW 1 SW 2 Dcs _Sw Gm s _Sw

P _OnOf f wr

VR TC

BAT
I rda_En Sds _Rx Sds _Tx

GD N
I R _EN DA SD S_RX SD S_TX

LC f i l t er

G ATE

PA M

IRD A - H L- 3201 SD

VR F
XT AL_OU T XT AL_I N AU DC N X_A _I TX W _P R_P TX W _P R_M Li Li Li Li ne_Q ne_Q + ne_I + ne_I Tem p_Sns LM 60CIM Tx_P + wr Tx_P wr

OSC1 0 1
19. 5MHz

RF 14 2
VA + VP M PC CGS VA PC VP S CDC B D AN TX_EN 2 RF + PC GS A M PC DC PC SA Dcs _Sw Tx_E n2

IF CON . - H L- 3201 SD

Sds _Rx Sds _Tx Debug_R x Debug_T x M ci M c+ i Ta_D et Vex t Bp_V f P or

M c+ i M ci Spk r+ Spk rPor Bp_D et

R _Cpl f

M c _Bi as i

VSI M
Si m am _Cl p VP VCC AC D V 1 CCA VOS C VR F VTI C VSI M VSY N VS W Vbat Vsi m _Ref V est t Rx_E n1 Tx_E n1 Sys _Ee Pw _OnO f r f Al arm Ta_D et S_Dat S_Cl k Res et _B Si m _Reset Si m k _Cl Si m _Dat Si m _En Cl k _Rqst Por Boost _E n Vset B _Det _E at n Ta_P esent r C harger _D sabl e i Bp_V f Bat _Det _E n Ta_P esent r Ta_D et Charger_D s abl e i Send_End Hds t _Det R t _Ct l m Dai _R eset D _Cl k ai Vex t VB at Bp_D et Power I c

PM IC
20 436

Audi o ci r c ui t

2000. 03. 07

SGH-A110 Integrated Analog Circuit Diagram
2000.6.12
REV: MP1.3

SGH-A188 Integrated Analog Circuit Diagram
2000.6.12
REV: MP1.4

2000. 03. 07

SGH-A110 SGH-A1 M46 Asic Circuit Diagram
2000.6.12
REV: MP1.3

SGH-A188 M46 Asic Circuit Diagram
2000.6.12
REV: MP1.4

200. 03.0 7

SGH-A110 Dual Synthesizer + Transceiver Circuit Diagram
2000.6.12
REV: MP1.3

SGH-A188 Dual Synthesizer + Transceiver Circuit Diagram
2000.6.12
REV: MP1.4

2000 .03. 07

SGH-A110 Power Managenemt Circuit Diagram
2000.6.12
REV: MP1.3

SGH-A188 Power Managenemt Circuit Diagram
2000.6.12
REV MP1.4

Receiver FrontEnd

Transmit/Receive Switch

M em or y

Transmitter

Receiver Front End

Transmit / Receive Switch

Memory Transmitter
2000.6.12
REV: MP1.3

SGH-A188 Transmit / Receive Switch Transmitter Receiver Front End Memory Circuit Diagram

Receiver Front End

Transmit / Receive Switch

Memory

Transmitter
2000.6.12
REV: MP1.4

SGH-A188 Transmit / Receive Switch Transmitter Receiver Front End Memory Circuit Diagram

SGH-A110

MMI and System Connector Interface
2000.6.12
REV: MP1.3

MMI and System Connector Interface Circuit Diagram

SGH-A188

MMI and System Connector Interface
2000.6.12

MMI and System Connector Interface Circuit Diagram
REV: MP1.4