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16. INTERNAL BLOCK DIAGRAM & PIN FUNCTION OF IC 1
lm KA9220
1
(1) BLOCK DIAGRAM
(S) (9
SET APDI BPF EFMO AASC DVEE MCK MLT MOAT RESET 01% TRCNT AVEE TEST1 ISTAT PFSET CBH CPH TESTH SSTOP SLEI SLEO SLEN TEST2
AVCC (S)
I EFM
TDF CT
TKEI
AMP a
COMPARATOR TKEO
AVCC (RF)
`CO 1-TIME1 IVCD 2;lMESl
TGSW
PHASE I A
SMPD fi2-_- I I . .a--. . -n-hmrn3.,e m- - ---. -/II 1. COMPENSATION -16)
RTG
Y I CLV I
AU I U 3tUUtNb,el
SMON m-4 LPF 1 ATS
I I I
SMEF TZC
TE2
SPDI
I FSl TO4 TGI TO2 TMI TO7 psi TO4
I TEl
FOCUS PHASE
SPDLO
WDCH FSCH
AP"1; AMY
FDFCT
t '
I 1 t- FCE
LOON FSEO
RFI RF0 RF- P/N LO PO PO1 PO2 CV N/C F E EO El RV DCC2 DCCl AVEE FBIAS FE1 FE2 HFGD FSW LFR
(RF)
(2) PIN DESCRIPTION
.
Pin No. 1 Symbol 1 Description
1 AVEE (R) Analog negative power supply input pin for RF part
2 CPH Capacitor connection pin of mirror hold.
3 CBH Capacitor connection pin of defect bottom-hold
4 TESTD Defect test pin
TESTM Mirror test pin
TEST1 Input pin for test
PFSET Peak frequency setting pin for focus, tracking compensation and fc
(cut off frequency) of CLV LPF.
8 SSTOP Check the position pin of pick-up whether inside or not.
9 DIRC Direct 1 Track Jump Control Pin
10 AVCC (S) Analog positive power supply input pin for SERVO part.
11 WDCH Auto-sequencer clock-input pin
e (Normal speed=88.2kHz, Double speed=1 76.4kHz)
12 SMPD Connection pin of DSP SMPD
13 SMON Connection pin of DSP SMON, spindle servo ON at "H"
14 N/C No connection pin
-211
IPin No. 1 Symbol Description I
15 TGSW Providing time constant to change the high frequency tracking gain -
16 RTG Capacitor connection pin switch the tracking gain of high frequency
17 LFR Capacitor connection pin to perform rising low bandwidth of focus
servo loop
18 FSW High frequency gain of focus servo loop can be changed by FS3
switch ON or OFF
Reducing high frequency gain with capacitor connected between
1 I9 1 HFGD 1 pin 18andpin 19.
20 FSCH Time constant external pin to generate focus search waveform
21 VREGI External regulator voltage input pin for VCO
22 ISET Determing the peak value of focus search, track jump and SLED kick
23 1 VREG 1 3.5V Reaulator output pin
24 1 FVC 1 Pin connected external resistor to adjust free runnina freauencv of VCO
I 25 1 SMEF 1 Providinq an external LPF time constant of CLV SERVO Loop I
26 BPF Providing time constant for Loop filter of VCO
27 MCK Clock input pin from micom
28 MLT Latch input pin from micom
29 MDAT Data input pin from micom
30 RESET Reset input pin from micom, reset at UL"
31 LOCK Pin for operation of the sied runaway prevention function at "L"
32 TRCNT Track count output pin
133~~ 1 Internal status output pin I
34 AVEE (S) Analog negative power supply input pin for SERVO part
35 APDI Input pin of DSP phase comparison output (PHAS)
36 F8M Output pin of analog VCO
1 I Normal speed=8.64MHz. Double speed=1 7.28MHz
37 AASC Auto-Asymmetry control input pin
38 EFMO EFM comparator output pin
39 SLEN Non-inverting input pin of SLED SERVO amplifier
40 SLEO Output pin of SLED SERVO amplifier
41 SLEI lnvertina input pin of SLED SERVO amplifier
42 TEST2 Test input pin to change speed mode
Normal speed= "H" , Double speed= "L"
43 SPDI Inverting input pin of spindle servo amplifier
44 SPDLO Spindle servo amplifier output pin
45 FCE Inverting input pin of focus servo complifier.
46 FSEO Output pin of focus servo amplifer
-
47 TKEI Non-inverting input pin of tracking servo amplifier
48 TKEO Output pin of tracking servo amplifier
IPin No. 1 Symbol 1 Description
1 49 ( N/C 1 No connection
I 50 ( ATS 1 Anti-shock input pin
I 51 1 TZC 1 Tracking Zero Crossing input pin
I 52 / TE2 1 Tracking Error Servo input pin
53 TEI Output pin of tracking Error Amplifer
54 TDFCT Capacitor Connection pin for Defect Compensation of tracking servo
55 DVCC(S) Digital positive power supply input pin for servo part
56 FE2 Focus error servo input pin
57 FE1 Output pin of focus error Amplifer
58 FDFCT Capacitor connection pin for defect compensation of focus servo
59 FOK Output pin of Focus ok comparator.
60 LDON Laser diode ON/OFF control pin
6TlEl I Feedback input pin of E I-V amplifier
I 62 1 EO 1 Output pin of E I-V Amplifier
I 63 I FBIAS I Bias pin of non-inverting input of focus error amplifier
64 DVEE (S) Digital negative power supply input pin for servo part
I 65 1 RFI 1 Output Sianal of RF summing amplifier is inputed through capacitor
I 66 [ RF0 I Output pin of RF summing amplifier
I 67 I RF- I invertino input pin of RF summing amplifier
I 68 1 RV 1 Output pin of (AVCC+AVEE)/2 Voltage
1 69 1 CV 1Bias input pin of Center Voltage buffer
I 70 I LD 1 Output pin of APC amplifier
71 PD Input pin of APC amplifier
72 AVCC( R) Analog positive power supply input pin for RF part
73 N/C No connection
74 PD2 Inverting input pin of RF I-V AMP2
75 PDI Inverting input pin of RF I-V AMP1
76 F Inverting input pin of FI-V AMP
I 77 I E I Inverting input pin of E I-V AMP
I 78 I P/N I Selecting P-sub/N-sub of Laser diode
I 79 I DCC2 I Defect bottom-hold output is inputed through capacitor
I 80 1 DCCI 1 Output pin of defect bottom-hold
- 23 I
2. KS9282
(1)BLOCK DIAGRAM -
SOS1 SBCK SDAT SQEN SQCK
SQDT
SQOK
r
I I
EFMI
EFM 28 bits EFM
APDO . phase * shift
+ demodulator
detector register
\
"1
I
. I I
r
I
DPDO
DPFIN Frame
sync
DPFOUT DPLL detector
protector
CNTVOL insertor
+ 16K SRAM
.
-
SMON SRAM
SMPD * Address
SMSD
LOCK + Interpolator
h \
MCK b&3- I I I
D/A Converter
DATX RCHOUT LCHOUT
(2)PIN CONFIGURATION
AVDDl SEL4
DPDO SEL3
DPFIN SEL2
DPFOUT SELl
CNNOL ICS
AVSSl MIE
DATX C16M
XIN cm/l
XOUT /JIT
WDCHl ULKFS
LRCHl FSDW
ADATAl DVSS2
DVSSl KS9282 /PBCK
BCK c2FL
C2PO C2F2
TIM2 C2Fl
/BCKl ClF2
/BCK2 ClFl -
BCK2 DBl
LRCH2 082
ADATA 083
N.C 084
WDCH2 DB5
EMPH DB6
--
(3) PIN DESCRIPTION
Pin No. Symbol l/O Description
1 1 AVDDI 1 1 Analog Vcc 1 I
2 I DPDO 1 0 1 Charge pump output for master PLL I
~~~~
3 I DPFIN I I 1 Filter input for master PLL I
YIP DPFOUT I o 1 Filter output for master PLL I
5 [ CNTVOL I I I VCO Control Voltage for master PLL I
mVSS1 I I Analog Ground 1
7 DATX 0 Digital audio output
8 XIN I X-tal oscillator input
9 XOUT 0 X-tal oscillator output
10 1 WDCHI / 0 1 Wordclockof 48 bit/SLOT
(Normal speed=88.2kHz, Double speed=1 76.4kHz)
Pin No. Symbol l/O Description
11 LRCH 0 Channel clock of 48 bit/SLOT
(Normal speed=44.1 kHz, Double speed=88.2kHz)
12 ADATA 0 Serial audio data output of 48 bit/SLOT (MSB first)
13 DVSSI Digital Ground 1
14 BCK 0 Audio data Bit clock for 48 bit/SLOT
(Normal speed=2.1168kHz, Double speed=4.2336kHz)
15 C2PO 0 C2 pointer for output audio data
16 VREFL2 I Input terminal 2 of reference voltage "L" (Floating)
17 VREFLI I Input terminal 1 of reference voltage `I" (GND connection)
18 AVDD2 Analog VCC2
19 RCHOUT 0 Right-channel audio output through D/A convenes
20 LCHOUT 0 Left-channel audio output through D/A converter
21 AVSS2 Analog ground 2
22 VREFHI I Input terminal 1 of reference voltage "H" (VDD connection)
23 VREFH2 I Input terminal 2 of reference voltage "H" (Floating)
24 EMPH 0 Emphasis/Non-Emphasis output ("H": Emphasis)
25 LKFS 0 The lock status output of frame sync
26 SOS1 0 Output of subcode sync signal (SO+Sl)
27 RESET I System reset at "L"
28 SQEN I SQCK I/O Control ("L" : internal CK, "H" : external CK)
\
29 SQCK I/O Clock for output subcode-Q data
30 SQDT 0 Serial output of subcode-Q data
31 SQOK 0 The CRC Check result signal output of subcode-Q
32 SBCK I Clock for output subcode-Q data
33 SDAT 0 Subcode Serial data output
34 DVDDI Digital Vcc 1
35 MUTE I Mute control Input ("H" : Mute ON)
36 MLT I Latch signal input from Micom
37 MDAT I Serial data input from Micom
38 MCK I Serial clock input from Micom
39 DB8 I/O SRAM data I/O Port 8 (MSB)
40 087 I/O SRAM data I/O Port 7
41 DB6 I/O SRAM data I/O Port 6
42 DB5 I/O SRAM data I/O Port 5
43 DB4 I/O SRAM data I/O Port 4
44 DB3 I/O SRAM data I/O Port 3
45 DB2 I/O SRAM data I/O Port 2
46 DBI I/O SRAM data I/O Port I (LSB)
1
- 26 I
Pin No. Symbol l/O Description
-
47 Cl Fl I/O Monitoring output for Cl error Correction (RAI )
48 ClF2 I/O Monitoring output for Cl error Correction (RA2)
49 C2Fl I/O Monitoring output for C2 error Correction (RA3)
50 C2F2 I/O Monitoring output for C2 error Correction (RA4)
51 C2FL I/O C2 decoder flag (High: When the processing C2 code is
impossible correction state) (RA5)
VCO (Normal speed = 4.3218MHz
52 /PBCK I/O output of -
2 Double speed = 8.6436MHz) (RA6)
53 DVss2 . Digital Ground 2
54 FSDW I/O Unprotected frame Sync (RA7)
55 ULKFS I/O Frame sync protection state (RA8)
56 /JIT I/O Display of either RAM overflow or underflow for =t4 frame Jitter margin
(RA9)
57 C4M I/O Only Monitoring signal (Normal playback: 4.2336MHz)
(RAIO)
58 C16M I/O 16.9344MHz signal output (RAI 1)
59 /WE I/O Terminal for test
60 ICS I/O Terminal for test
61 SELI I Mode Selection Terminal 1 (H: 33.8688MHz)
(L: 16.9344MHz)
62 SEL2 I Mode Selection Terminal 2 (H: APLL)
(L: DPLL)
63 SEL3 I Mode Selection Terminal 3 (H: CDROM)
(L: CDP)
64 SEL4 I Mode Selection Terminal 4 (L: Internal SRAM)
65 TEST I Test Terminal (L: Normal operating state)
66 EFMI I EFM Signal input
67 APDO 0 Charge Pump output for analog PLL
68 /ISTAT 0 The internal status output
69 TRCNT I Tracking counter input signal
PBFR
70 LOCK 0 Output signal of LKFS condition sampled 16
(If LKFS is "H", Lock is "H".
PBFR
If the LKFS is sampled "L" at least 8 times by ?, Lock is I")
71 PBFR 0 Write frame clock (Lock: 7.35kHz)
72 SMEF 0 LPF time constant control of the spindle servo error signal
73 SMON 0 ON/OFF control signal for spindle servo
74 DVDD2 Digital Vcc2
75 SMPD 0 Spindle Motor drive (Rough control in the CLV-S mode
Phase control in the CLV-P mode)
76 SMSD 0 Spindle Motor drive (Velocity control in the CLV-P mode)
77 VCOOl 0 VCO output signal (When the state is Lock by means of PBFR it is
4 8.643MHz)
78 VCOH I VCO input signal
79 DSPEED I Double speed mode control (H: Normal speed)
(L: Double speed)
80 APD02 0 Analog PLL charge pump output for Double speed mode
I
27 -