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5 4 3 2 1




2008.04.01
VTERM(+0.9V) ZG5 NB Block Diagram
VTT(+1.05V)
+1.5VSUS VID[0:6]
+1.5V Diamondville CPU VCORE
D P 29 D

+1.8VSUS VCORE:+1.196 ~ +0.748
+1.8V VCCP:+1.05V
+2.5V VCCA:+1.8V or +1.5V
+/- CPU_CLK
3VPCU P 4,5 Clock Gengerator
+/- HCLK
+3.3V FSB TBD. P 3
+3.3VSUS
LCD_3.3V CRT 17
P
LCD_5V 945GMS
HOST P 6
DDRII
+5V DDR P 7
CHA 256M/512M/1GB
C 8.9" panel LVDS LVDS, DMI, DDR CLK P 8
POWER P 9
P 14,15,16 C


SATA
P 17 GND P 10 HDD, ODD P 22

10/100 Ethernet PCI-E DMI SSD module
RJ-45 IDE/USB P 22
P 21 RTL8102EL 21
P
USB Camera Conn.
Camera
Card Reader PCI-E
ICH7M P 17 Module
5in1 USB
JBM385 P 24 RTC, AC97, SATA, IDE, LPC, CPU P 11 3G module
PCI-E, USB, DMI, PCI P 12 P 23 SIM card
B SMB, GPIO, CLK P 13 PCI-E/USB B
P 19
Int. HDA CODEC HD Audio WLAN + WMAX WLAN +WMAX
P 23
SPK ALC268 P 19 Module
USB USB PORT X 3
P 20,24
Audio MDC Modem LPC BUS
Jack P 19 EC SPI
WPCE775L
Int. P 25 Flash
Card Reader PCI-E
A
Mic JBM385 P 26
A




Quanta Computer Inc.
RJ-11 SD Card Int. KB T/P Charger Battery PROJECT : ZG5
Size Document Number Rev
P 26 1A
P 18 P 18 P 27 P 27 Block Diagram
Date: Thursday, June 05, 2008 Sheet 1 of 34
5 4 3 2 1
5 4 3 2 1




5VPCU
1A 5VUSB
SW

USBON Control By EC
D D
0.64A +5V
SW

MAINON
1.18A +VCCP
PWM
(1.05V)
VRON
5VPCU(3A) 2A
PWM +1.5V
VIN Always ON
3VPCU(3A) 0.038A SUSB#
PWM 3VPCU
SW 0.055A
+3.3VSUS
3VSUSON Control By EC
C C




LDO 0.008A
+1.5VSUS
1.5VSUSON Control By EC
2.35A
SW +3.3V
MAINON
0.04A
LDO +2.5V
3.83A 3.1A MAINON
VCC18MEM
B B

VIN 0.13A
PWM SW +1.8V
MAINON
SUSC# 0.6A
LDO VTERM
SUSB# (0.9V)



VIN 6A
PWM +VCORE
(0.762V~1.3V)
VRON
A
DCIN ALWAYS ON S4 OFF S3 OFF
A




Quanta Computer Inc.
PROJECT : ZG5
Size Document Number Rev
1A
Block Diagram
Date: Thursday, June 05, 2008 Sheet 2 of 34
5 4 3 2 1
5 4 3 2 1



Clock Generator +3V


+1.05V_VDD PM_STPPCI# R133 2.2K_4

+3V C148 L32 +1.05V
L31 0.1u/10V_4 PBY160808T-301Y-N_6 PM_STPCPU# R132 2.2K_4
PBY160808T-301Y-N_6 C159 C150 C419 C147 C145 C156 C413 C171 C172
0.1u/10V_4
C417 10u/10V_8 10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 NEW_CLKREQ#_R R356 10K_4
10u/10V_8
D
C146 U7 D
0.1u/10V_4 VDD_CK_VDD_PCI 9 55
C165 VDD_CK_VDD_48 VDD_PCI IO_VOUT
16 VDD_48
0.1u/10V_4 VDD_CK_VDD_PCI 23 7 SMBCK1
C174 VDD_CK_VDD_REF VDD_PLL3 SCLK SMBDT1 PCLK_591 C153 *33p/50V_4
4 VDD_REF SDA 6
0.1u/10V_4 CK505
C167 VDD_CK_VDD_PCI 46 45 PM_STPPCI# PM_STPPCI# 13
0.1u/10V_4 VDD_CK_VDD_CPU VDD_SRC SRC5/PCI_STOP# PM_STPCPU# CLKUSB_48 C135 15p/50V_4
62 VDD_CPU SRC5#/CPU_STOP# 44 PM_STPCPU# 13 To SB
+1.05V_VDD
C408 19 61 CLK_CPU_BCLK_R
VDD_96_IO CPU0 CLK_CPU_BCLK 4
27 60 CLK_CPU_BCLK#_R To CPU 14M_ICH C152 *33p/50V_4
VDD_PLL3_IO CPU0# CLK_CPU_BCLK# 4
10u/10V_8 33 VDD_SRC_IO_1 CLK_MCH_BCLK_R
52 VDD_SRC_IO_3 CPU1 58 CLK_MCH_BCLK 6
43 57 CLK_MCH_BCLK#_R To NB PCLK_ICH C151 *33p/50V_4
VDD_SRC_IO_2 CPU1# CLK_MCH_BCLK# 6
56 VDD_CPU_IO
54 CLK_PCIE_MINI2&4_R T44
SRC8/ITP CLK_PCIE_MINI2&4#_R T43
SRC8#/ITP# 53

PCLK_DEBUG R129 47_4 PCLK_DEBUG_R 8 42 CLK_PCIE_3GPLL_R
23 PCLK_DEBUG PCI0/CR#_A SRC10# CLK_PCIE_3GPLL 8
41 CLK_PCIE_3GPLL#_R To NB
SRC10 CLK_PCIE_3GPLL# 8
T65 PCLK_PCM_R 10 PCI1/CR#_B CLK_MCH_OE#_R R126 475/F_4
SRC11/CR#_H 40 MCH_CLKREQ# 8
PCLK_OZ129_R 11 39 NEW_CLKREQ#_R R355 475/F_4 CLKREQ_WLAN# 23
PCI2/TME SRC11#/CR#_G
T64 PCI_CLK_SIO_R 12 37 CLK_PCIE_NEW_R
PCI3 SRC9 PE2CLK+ 23
38 CLK_PCIE_NEW_R# To WLAN
C SRC9# PE2CLK- 23 C
PCLK_591 R121 33_4 PCLK_591_R 13
25 LCLK_EC PCI4/SRC5_EN
51 CLK_PCIE_MINI3#_R
SRC7/CR#_F PE1CLK- 21
PCLK_ICH R117 33_4 PCLK_ICH_R 14 50 CLK_PCIE_MINI3_R To LAN
12 PCLK_ICH PCIF5/ITP_EN SRC7#/CR#_E PE1CLK+ 21
SEL2 SEL1 SEL0 Frequence select
CG_XIN 3 48 CLK_PCIE_MINI_R
XTAL_IN SRC6 PE0CLK+ 24
CLK_PCIE_MINI#_R To Card Reader FSC FSB FSA CPU SRC PCI
rev. C CG_XOUT 2
SRC6# 47 PE0CLK- 24
XTAL_OUT
R102 47 ->33 R102 33_4 FSA SRC4 34 CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
PE3CLK+ 26 1 0 1 100 100 33
13 CLKUSB_48 17 USB_48/FSA SRC4# 35 PE3CLK- 26 To SDIO
CLK_BSEL0 R105 2.2K_4 0 0 1 133 100 33 Default
CLK_BSEL1 FSB 64 31 CLK_PCIE_ICH_R
FSB/TEST/MODE SRC3/CR#_C CLK_PCIE_ICH 12
CLK_BSEL2 R358 10K_4 32 CLK_PCIE_ICH#_R To SB 0 1 1 166 100 33
SRC3#/CR#_D CLK_PCIE_ICH# 12
R131 47_4 FSC 5
13 14M_ICH REF0/FSC/TESTSEL
65 28 CLK_PCIE_SATA_R 0 1 0 200 100 33
VSS_BODY SRC2/SATA CLK_PCIE_SATA 11
15 29 CLK_PCIE_SATA#_R To SB
VSS_PCI SRC2#/SATA# CLK_PCIE_SATA# 11
C166 18 0 0 0 266 100 33
27p/50V_4 CG_XIN VSS_48 DREFSSCLK_R
22 VSS_IO SRC1/SE1 24 DREFSSCLK 8
26 25 DREFSSCLK#_R To NB 1 0 0 333 100 33
VSS_PLL3 SRC1#/SE2 DREFSSCLK# 8
2




Y2 59 VSS_CPU DREFCLK_R
CL=20p 30 VSS_SRC1 SRC0/DOT96 20 DREFCLK 8 1 1 0 400 100 33
14.318MHZ 36 21 DREFCLK#_R To NB
VSS_SRC2 SRC0#/DOT96# DREFCLK# 8
C168 49 1 1 1 Reserved
1




27p/50V_4 CG_XOUT VSS_SRC3
1 VSS_REF CKPWRGD/PWRDWN# 63 VR_PWRGD_CK410 13
SLG8SP513 +1.05V R101 56_4
B B
SLG8SP513VTR ,ICS9LPRS365BKLFT To NB
+3V R124 10K_4 PCLK_OZ129_R R96 *0_4 CLK_BSEL0 R94 1K_4 MCH_BSEL0 8
4 CPU_BSEL0
ICS9LPRS365 RTM875T-606 R100 *1K_4
(ALPRS365K13) (AL000875K06) PULL HIGH PULL DOWN R122 *10K_4
+1.05V R137 *1K_4
PCI2/TME
Pin 11 PCI2/TME internal PD NO OVERCLOCKING (default) NORMAL RUN
+3V R111 *10K_4 PCLK_591 R139 *0_4 CLK_BSEL1 R140 1K_4 MCH_BSEL1 8
PCI-3/SRC5_EN PIN37/38 IS HIGH 27MHz 4 CPU_BSEL1
Pin 12 PCI-3 internal PD PIN37/38 IS SRC5 PCI_STOP/CPU_STOP (default) LOW SRC R138 0_4
R116 10K_4
PCI-4/27M_SEL PIN 17/18 R363 *1K_4
+1.05V
Pin 13 PCI-4/27M_SEL internal PD PIN 17/18 IS 27MHz IS SRC/DOT (default)
+3V R104 *10K_4 PCLK_ICH
PCIF-5/ITP_EN R361 *0_4 CLK_BSEL2 R362 1K_4
Pin 14 PCIF-5/ITP_EN internal PD PIN 46/47 IS CPUITP PIN 46/47 IS SRC8 (default) 4 CPU_BSEL2 MCH_BSEL2 8
R109 10K_4 R359 0_4


+3V +3V
Clock Gen I2C
:ICS9LPRS365BGLFT QCI:ALPRS365K13
:SLG8SP512TTR: QCI:AL8SP512K05
A
R351 R354 Quanta Computer Inc. A
4.7K_4 4.7K_4
2




2




Q28 Q29
PROJECT : ZG5
3 1 SMBDT1 3 1 SMBCK1 Size Document Number Rev
13,23 SMBDT SMBDT1 14,16,23 13,23 SMBCK SMBCK1 14,16,23
1A
CLOCK GENERATOR
2N7002E 2N7002E Date: Thursday, June 05, 2008 Sheet 3 of 34




5 4 3 2 1
5 4 3 2 1


CPU U25A U25B
04
6 H_A#[31:3] 6 H_D#[63:0] H_D#[63:0] 6
H_A#3 P21 V19 H_D#0 Y11 R3 H_D#32
A[3]# ADS# H_ADS# 6 D[0]# D[32]#
H_A#4 H20 Y19 H_D#1 W10 R2 H_D#33
A[4]# BNR# H_BNR# 6 D[1]# D[33]#
H_A#5 N20 U21 H_D#2 Y12 P1 H_D#34
A[5]# BPRI# H_BPRI# 6 D[2]# D[34]#
H_A#6 R20 H_D#3 AA14 N1 H_D#35
A[6]# D[3]# D[35]#




0
0
GROUP
GROUP
ADDR
ADDR




DATA GRP 0
H_A#7 J19 T21 H_D#4 AA11 M2 H_D#36
A[7]# DEFER# H_DEFER# 6 D[4]# D[36]#
H_A#8 N19 T19 H_D#5 W12 P2 H_D#37
A[8]# DRDY# H_DRDY# 6 D[5]# D[37]#
H_A#9 G20 Y18 H_D#6 AA16 J3 H_D#38




DATA GRP 2
A[9]# DBSY# H_DBSY# 6 D[6]# D[38]#
D
H_A#10 M19 H_D#7 Y10 N3 H_D#39 D
H_A#11 A[10]# H_D#8 D[7]# D[39]# H_D#40
H21 A[11]# BR0# T20 H_BREQ#0 6 Y9 D[8]# D[40]# G3
H_A#12 L20 H_D#9 Y13 H2 H_D#41
A[12]# D[9]# D[41]#




CONTROL
H_A#13 M20 F16 IERR# R60 56_4 +1.05V H_D#10 W15 N2 H_D#42
H_A#14 A[13]# IERR# D[10]# D[42]#
K19 A[14]# INIT# V16 H_INIT#R R72 H_INIT# 11
H_D#11 AA13 D[11]# D[43]# L2 H_D#43
H_A#15 J20 1K/F_4 R67 330_4 +1.05V H_D#12 Y16 M3 H_D#44
H_A#16 A[15]# H_D#13 D[12]# D[44]# H_D#45
L21 A[16]# LOCK# W20 H_LOCK# 6 W13 D[13]# D[45]# J2
K20 H_D#14 AA9 H1 H_D#46
6 H_ADSTB#0 ADSTB[0]# H_CPURST# 6 D[14]# D[46]#
T11 H_AP0 D17 D15 H_D#15 W9 J1 H_D#47
6 H_REQ#[4:0] AP0 RESET# H_RS#[2:0] 6 D[15]# D[47]#
H_REQ#0 N21 W18 H_RS#0 Y14 K2
REQ[0]# RS[0]# 6 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 6
H_REQ#1 J21 Y17 H_RS#1 Y15 K3
REQ[1]# RS[1]# 6 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 6
H_REQ#2 G19 U20 H_RS#2 W16 L1
REQ[2]# RS[2]# 6 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 6
H_REQ#3 P20 W19 T18 H_DP#0 V9 M4 H_DP#2 T31
REQ[3]# TRDY# H_TRDY# 6 DP#0 DP#2
H_REQ#4 R19
REQ[4]# 6 H_D#[63:0] H_D#[63:0] 6
AA17 H_D#16 AA5 C2 H_D#48
6 H_A#[31:3] HIT# H_HIT# 6 D[16]# D[48]#
H_A#17 C19 V20 H_D#17 Y8 G2 H_D#49
A[17]# HITM# H_HITM# 6 D[17]# D[49]#
H_A#18 F19 H_D#18 W3 F1 H_D#50
H_A#19 A[18]# XDP_BPM#0 T12 H_D#19 D[18]# D[50]# H_D#51
E21 A[19]# BPM[0]# K17 U1 D[19]# D[51]# D3
H_A#20 A16 J18 XDP_BPM#1 T6 H_D#20 W7 B4 H_D#52
A[20]# BPM[1]# D[20]# D[52]#




DATA GRP 1
H_A#21 D19 H15 XDP_BPM#2 T15 H_D#21 W6 E1 H_D#53
H_A#22 A[21]# BPM[2]# XDP_BPM#3 T17 H_D#22 D[21]# D[53]# H_D#54
C14 A[22]# BPM[3]# J15 Y7 D[22]# D[54]# A5
ADDR GROUP 1

H_A#23 XDP_BPM#4 T3 H_D#23 H_D#55




DATA GRP 3
C18 K18 AA6 C3

XDP/ITP SIGNALS
C
H_A#24 A[23]# PRDY# XDP_BPM#5 H_D#24 D[23]# D[55]# H_D#56 C
C20 A[24]# PREQ# J16 XDP_BPM#5 Y3 D[24]# D[56]# A6
H_A#25 E20 M17 XDP_TCK H_D#25 W2 F2 H_D#57
A[25]# TCK XDP_TCK D[25]# D[57]#
H_A#26 D20 N16 XDP_TDI H_D#26 V3 C6 H_D#58
A[26]# TDI XPD_TDI D[26]# D[58]#
H_A#27 B18 M16 XDP_TDO T13 H_D#27 U2 B6 H_D#59
H_A#28 A[27]# TDO XDP_TMS H_D#28 D[27]# D[59]# H_D#60
C15 A[28]# TMS L17 XPD_TMS T3 D[28]# D[60]# B3
H_A#29 B16 K16 XDP_TRST# H_D#29 AA8 C4 H_D#61
A[29]# TRST# XPD_TRST# D[29]# D[61]#
H_A#30 B17 V15 BR1# R74 H_D#30 V2 C7 H_D#62
A[30]# BR1# PM_SYSRST# 13 D[30]# D[62]#
H_A#31 C16 *0_4 R42 R33 +1.05V H_D#31 W4 D2 H_D#63
H_A#32 A[31]# H_PROCHOT#_R 22_4 68_4 D[31]# D[63]#
A17 A[32]# PROCHOT# G17 H_PROCHOT# 29 6 H_DSTBN#1 Y4 DSTBN[1]# DSTBN[3]# E2 H_DSTBN#3 6
H_A#33 B14 E4 Y5 F3
THERM




A[33]# THRMDA H_THERMDA 5 6 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 6
H_A#34 B15 E5 Y6 C5
A[34]# THRMDC H_THERMDC 5 6 H_DINV#1 DINV[1]# DI