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HD3000U
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Downloaded from www.Manualslib.com manuals search engine Table of Contents NO. Item Page Cover Sheet 1 Table of Contents 2 Record of Revision 3 1 Features 4 2 General Specifications 4 3 Input / Output Terminals 5 4 Absolute Maximum Ratings 7 5 Electrical Characteristics 8 6 Timing Chart 9 7 Optical Characteristics 17 8 Reliability 19 9 Handling Cautions 20 10 Mechanical Drawing 21 11 Packing Drawing 22
Downloaded from www.Manualslib.com manuals search engine Record of Revision Rev Issued Date Description 0.00 Aug. 21, 2006 New create.
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Downloaded from www.Manualslib.com manuals search engine 1. FEATURES The 3.0" LCD module is the active matrix color TFT LCD module. LTPS (Low Temperature Poly Silicon) TFT technology is applied with vertical and horizontal drivers built on the panel. Both of horizontal and vertical scan are reversible and controlled by the serial interface commands. The product is designed for the requirement of the green product, and the specification complies with Toppoly's "Green Product Chemical Substance Specification Standard Hand Book".
2. GENERAL SPECIFICATIONS Item Description Unit Display Size (Diagonal) 3.0 Inch Aspect ratio 16:9 - Display Type Transmissive - Active Area (HxV) 65.31 x 36.84 mm Number of Dots (HxV) 960 x 240 Dot Dot Pitch (HxV) 0.068 x 0.1535 mm Color Arrangement RGB Delta - Color Numbers 16Million - NTSC 40 % Outline Dimension (HxVxT) 75.31x43.44x2.58*(Approx.) mm Weight TBD G Panel surface treatment Hard Coating (3H) - *Exclude FPC and protrusions.
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Downloaded from www.Manualslib.com manuals search engine Recommend connector: Compatible with JAE IL-FHJ-39S-HF-A1 Pin Symbol I/O Description Remark 1 CP3 C Capacitor for charge pump 2 CP4 C Capacitor for charge pump 3 CP5 C Capacitor for charge pump 4 CP6 C Capacitor for charge pump 5 CP7 C Capacitor for charge pump 6 CP8 C Capacitor for charge pump 7 NC -- No connection 8 PCDL C Capacitor for pre-charge data signal low 9 PCDH C Capacitor for pre-charge data signal high 10 VCOML C Capacitor for VCOM low 11 VCOMH C Capacitor for VCOM high 12 AGND -- Analog ground 13 PVDD C Regulation capacitor for charge pump 14 AVDD C Regulation capacitor for analog voltage 15 CP1 C Capacitor for charge pump 16 CP2 C Capacitor for charge pump 17 PWM O Power transistor gate signal for the boost converter 18 FB I Main boost regulator feedback input 19 LED- -- LED power: cathode Note 3-1 20 LED+ -- LED power: anode 21 NC -- No connection 22 GND -- Ground 23 VCC -- Power supply 24 VD I Vertical sync input 25 HD I Horizontal sync input 26 DCLK I Clock signal, latch data onto line latches at the rising edge 27 DIN0 I Data input 28 DIN1 I Data input 29 DIN2 I Data input 30 DIN3 I Data input 31 DIN4 I Data input
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Downloaded from www.Manualslib.com manuals search engine 32 DIN5 I Data input 33 DIN6 I Data input 34 DIN7 I Data input 35 SDA I/O Serial interface data line 36 SCL I Serial interface clock line 37 SCEN I Serial interface chip enable line 38 SHDB I Sleep mode setting pin 39 GRESTB I Global reset pin Note 3-1: The figure below shows the connection of backlight LED.
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Downloaded from www.Manualslib.com manuals search engine Ta = 25 Item Symbol MIN MAX Unit Remark Logic Power Supply Voltage VCC -0.5 4.5 V VD, HD, DCLK, DIN[0:7], SDA, Input Signal Voltage VIN1 0 VCC V SCL, SCEN, SHDB, GRESTB Back Light Forward Current IF -- 25 mA Operating Temperature TOPR -10 +60 Storage Temperature TSTG -30 +80
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Downloaded from www.Manualslib.com manuals search engine GND=0V, Ta=25 Item Symbol MIN TYP MAX Unit Remark Power Supply Voltage VCC 2.85 3.3 3.6 V Note 5-1 VD, HD, DCLK, Low Level VIL GND - 0.2x Vcc* V Input Signal DIN[0:7], SDA, SCL, Voltage SCEN, SHDB, High Level VIH 0.8x Vcc* - Vcc* V GRESTB PWM Output Voltage VPWM 0 - Vcc* V Feedback Voltage VFB 0.55 0.6 0.65 V Note 5-2 Panel Power Consumption WP - 70 mW Vcc* =Vcc (TYP) Note 5-1: The Vcc power is provided for overall panel module supply voltage. Note 5-2: DC/DC feedback control voltage
5.2 Driving Backlight Ta=25 Item Symbol MIN TYP MAX Unit Remark Forward Current IF -- 23 25 mA Forward Current Voltage VF -- 9.6 10.8 V Note 5-3 Backlight Power Consumption W BL -- 221 270 mW Note 5-3: Backlight driving circuit is recommended as the fix current circuit.
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Downloaded from www.Manualslib.com manuals search engine 6. TIMING CHART Serial RGBDummy or Serial-YUV 4:2:2 mode --Horizontal--
(1) NTSC Mode:
Parameter Symbol MIN TYP MAX Unit DCLK Frequency FDCLK -- 27 -- MHz Horizontal valid data thd -- 1440 -- DCLK 1 Horizontal Line th -- 1716 -- DCLK HSYNC Pulse Width thpw 1 1 -- DCLK Hsync blanking thp -- 240 -- DCLK Horizontal Front Porch thfp -- 36 -- DCLK Horizontal Dummy Time thdm -- 0 -- DCLK
Parameter Symbol MIN TYP MAX Unit DCLK Frequency FDCLK -- 24.54 -- MHz Horizontal valid data thd -- 1280 -- DCLK 1 Horizontal Line th -- 1560 -- DCLK HSYNC Pulse Width thpw 1 1 -- DCLK Hsync blanking thp -- 240 -- DCLK Horizontal Front Porch thfp -- 40 -- DCLK Horizontal Dummy Time thdm -- 0 -- DCLK
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Downloaded from www.Manualslib.com manuals search engine (2) PAL Mode: Parameter Symbol MIN TYP MAX Unit DCLK Frequency FDCLK -- 27 -- MHz Horizontal valid data thd -- 1440 -- DCLK 1 Horizontal Line th -- 1728 -- DCLK HSYNC Pulse Width thpw 1 1 -- DCLK Hsync blanking thp -- 240 -- DCLK Horizontal Front Porch thfp -- 48 -- DCLK Horizontal Dummy Time thdm -- 0 -- DCLK
Parameter Symbol MIN TYP MAX Unit DCLK Frequency FDCLK -- 24.38 -- MHz Horizontal valid data thd -- 1280 -- DCLK 1 Horizontal Line th -- 1560 -- DCLK HSYNC Pulse Width thpw 1 1 -- DCLK Hsync blanking thp -- 240 -- DCLK Horizontal Front Porch thfp -- 40 -- DCLK Horizontal Dummy Time thdm -- 0 -- DCLK
(3) QVGA Mode: Parameter Symbol MIN TYP MAX Unit DCLK Frequency FDCLK -- 25 -- MHz Horizontal valid data thd -- 1280 -- DCLK 1 Horizontal Line th -- 1560 -- DCLK HSYNC Pulse Width thpw 1 1 -- DCLK Hsync blanking thp -- 240 -- DCLK Horizontal Front Porch thfp -- 40 -- DCLK Horizontal Dummy Time thdm -- 0 -- DCLK
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Downloaded from www.Manualslib.com manuals search engine --Vertical-- Interlace: ODD Field: same phase VD and HD EVEN Field: same phase VD and Half-HD
Non-interlace:
(1) Interlace Mode: NTSC/QVGA
Parameter Symbol MIN TYP MAX Unit Vertical valid data tvd - 240 - H 1 Vertical field tv - 262.5 - H VSYNC Pulse Width tvpw 1 1 - DCLK Vsync blanking Odd Field tvbo - 21 - H Even Field tvbe - 21.5 - H Vertical Front Odd Field tvfpo - 1.5 - H Porch Even Field tvfpe - 1 - H Vertical dummy time tvdm - 0 - H
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Downloaded from www.Manualslib.com manuals search engine (2) Interlace Mode: PAL
Parameter Symbol MIN TYP MAX Unit Vertical valid data tvd - 288 - H 1 Vertical field tv - 312.5 - H VSYNC Pulse Width tvpw 1 1 - DCLK Vsync blanking Odd Field tvbo - 24 - H Even Field tvbe - 24.5 - H Vertical Front Odd Field tvfpo - 0.5 - H Porch Even Field tvfpe - 0 - H Vertical dummy time tvdm - 0 - H
(3) Non-Interlace Mode: NTSC/QVGA
Parameter Symbol MIN TYP MAX Unit Vertical valid data tvd - 240 - H 1 Vertical field tv - 262 - H VSYNC Pulse Width tvpw 1 1 - DCLK Vsync blanking Odd Field tvbo - 21 - H Even Field tvbe - 21 - H Vertical Front Odd Field tvfpo - 1 - H Porch Even Field tvfpe - 1 - H Vertical dummy time tvdm - 0 - H
(4) Non-Interlace Mode: PAL
Parameter Symbol MIN TYP MAX Unit Vertical valid data tvd - 288 - H 1 Vertical field tv - 312 - H VSYNC Pulse Width tvpw 1 1 - DCLK Vsync blanking Odd Field tvbo - 24 - H Even Field tvbe - 24 - H Vertical Front Odd Field tvfpo - 0 - H Porch Even Field tvfpe - 0 - H Vertical dummy time tvdm - 0 - H
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Downloaded from www.Manualslib.com manuals search engine Through mode --Horizontal-
thpw
HD
DCLK
DIN[7:0] Valid Data
thdm Display Area thdm
Active Area
thb thd thfp
1 Horizontal Line(tb)
Parameter Symbol MIN TYP MAX Unit DCLK Frequency FDCLK -- 18.42 -- MHz Horizontal valid data thd -- 960 -- DCLK 1 Horizontal Line th -- 1171 -- DCLK HSYNC Pulse Width thpw 1 1 -- DCLK Hsync blanking thp -- 152 -- DCLK Hsync front porch thfp -- 59 -- DCLK Horizontal dummy time thdm -- 0 -- DCLK (1) Input RGB Sequence Resolution (960 x 240)
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Downloaded from www.Manualslib.com manuals search engine --Vertical-- Interlace: ODD Field: same phase VD and HD EVEN Field: same phase VD and Half-HD
VD
HD
DIN[7:0] Valid Data Valid Data
tvdm Display Area tvdm tvdm Display Area tvdm Active Area Active Area
tvbo tvd tvfpo tvbe tvd tvfpe
Odd Field(tv) Even Field(tv)
1 Frame
Non-interlace: tvpw
VD
HD
DIN[7:0] Valid Data Valid Data tvdm Display Area tvdm tvdm Display Area tvdm Active Area Active Area
tvbo tvd tvfpo tvbe tvd tvfpe
Odd Field(tv ) Even Field(t v) 1 Frame
(1) Interlace Mode
Parameter Symbol MIN TYP MAX Unit Vertical valid data tvd - 240 - H 1 Vertical field tv - 262.5 - H Vsync pulse width tvpw 1 1 - DCLK Vsync blanking Odd Field tvbo - 14 - H Even Field tvbe - 14.5 - H Vsync Odd Field tvfpo - 8.5 - H front porch Even Field tvfpe - 8 H Vertical dummy time tvdm - 0 - H
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Downloaded from www.Manualslib.com manuals search engine (2) Non-Interlace Mode
Parameter Symbol MIN TYP MAX Unit Vertical valid data tvd - 240 - H 1 Vertical field tv - 262 - H Vsync pulse width tvpw 1 1 - DCLK Vsync blanking Odd Field tvbo - 14 - H Even Field tvbe - 14 - H Vsync Odd Field tvfpo - 8 - H front porch Even Field tvfpe - 8 - H Vertical dummy time tvdm - 0 - H
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Downloaded from www.Manualslib.com manuals search engine Timing Diagram
D0 D1 D2 D3 D4 D5 D6 D7 DIN[7:0] tds tdh
DCLK tss tsh
HD
VD
Item Symbol MIN TYP MAX Unit DCLK Duty Ratio Duty 40 - 60 % Data Setup Time tds 12 - - ns Data Hold Time tdh 12 - - ns Control Signal Setup Time tss 12 - - ns Control Signal Hold Time tsh 12 - - ns
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Downloaded from www.Manualslib.com manuals search engine 7. OPTICAL CHARACTERISTICS 7.1 Optical Specification Ta=25 Item Symbol Condition MIN TYP MAX Unit Remarks 11 TBD 80 - 12 TBD 80 - Viewing Angles CR 10 Degree Note 7-1 21 TBD 80 - 22 TBD 80 - Contrast Ratio CR TBD 450 - Note 7-2 Rising Tr - 30 TBD Response Time ms Note 7-3 Falling Tf - 10 TBD =0