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5 4 3 2 1
PCI DEVICE IDSEL# REQ# / GNT# Interrupts CLOCK
CB1410 AD17 REQ0# / GNT0# INTE# CK410/PCI3
ZU2 SYSTEM BLOCK DIAGRAM
TIAB23 AD25 REQ2# / GNT2# INTF# CK410/PCI8
DVI / 7307 CLOCK GENERATOR
Chrontel
Yonah/Celeron-M CPU
MR510 AD18 REQ1# / GNT1# INTG# CK410/PCI4
CK410-M
(only for ezDock) (479 FCPGA) Thermal Sensor
D D
Page 17
Page 2 Page 3
Page 3,4
S-VIDEO CONN HOST BUS
Page 16
533/667MHz
DDRII
+1.5V +2.5V +1.05V
SDVO Dual Channel DDR2
LCD CONN +1.8VSUS
SO-DIMM 0
TV 533/667 MHz RJ45
(12.1"WXGA) LVDS NB SO-DIMM 1 Page 14
Page 16 VGA CALISTOGA-GM/PM Page 9,10
1466FCBGA Transformer
CRT Port Page 5~8 Page 14
Page 15
DMI interface
Mini Card / Giga Lan
HDD (SATA) SATA
C +1.5V
WLAN (BCM 5787)
C
Page 22 +2.5V
+3V
SB Page 23 Page 14
PATA +3VSUS ICH7-M PCIE-1 PCIE-2
ODD (PATA) PCI-Express
+1.5VSUS
Page 22
USB 2.0 652BGA
+1.05V
Azalia
Page 11~13
PCI Bus
USB Port x 3
USB1,4,5 Page 23
LPC
Bluetooth PCMCIA Card Reader
USB2 Page 23 1394
Controller Controller Controller
Super I/O (CB 1410) (MR510)
Finger Printer uR PC8763L (TI 43AB23)
USB7 Page 29 NS PC87383
Page 24 Page 26 Page 18 Page 19 Page 21
B B
CCD
USB3 Page 16
SPI ROM Touch Pad K/B CONN FIR PCMCIA Card Reader 1394 CONN
Page 24 Page 25 Page 25 Page 26 Page 20 Page 20 Page 25
HP HP AMP
Page 28 Page 27
5V/3V (ISL6236) 1.25V 1.5V 2.5V
Audio Codec PCI-Express PCIE-3
(ALC268) ezDockII/II+ Page 30 Page 34
INT SPK SPK AMP DVI
Page 28 Page 28 Connector USB0
USB VCORE(ISL6262A) Discharge
PCIE , Lan ,1394
Ser & Par Port 1394*2 Page 31 Page 34
Line in & MIC
Page 28 Page 27 PS2 , VGA, DVI TV out / CRT Switch
SPDIF,SM BUS Page 15
A
VTT 1.05V (SC411) Charger (ISL6251) A
MediaBay
Express Card Audio Page 32 Page 35
MDC 1.5 10/100/1G Switch 1.8V (TPS51116)
Page 27 Page 29 Page 14 PROJECT : ZU2
Page 33 Quanta Computer Inc.
Size Document Number Rev
Block Diagram 1A
Date: Wednesday, March 21, 2007 Sheet 1 of 39
5 4 3 2 1
A B C D E
VDD_A
Close to IC <500mils
25 mils C262 27P/50V_4 CG_XIN
L54 Place these termination to close CK410M.
45
46
2
BK2125HS121-T_8 U15
VDD_SRC_CPU Y2 58 60 14M_REF R373 33_4
VDDA
GNDA
+3V X1 REF0 14M_ICH (13)
14.318MHZ
120 ohms@100Mhz C274 27P/50V_4 CG_XOUT 57 52 R_HCLK_CPU RP31 1 2 33_4P2R CLK_CPU_BCLK (3)
1
C275 C256 C279 C260 C520 X2 CPUCLKT0 R_HCLK_CPU# C518
CPUCLKC0 51 3 4 CLK_CPU_BCLK# (3)
L:300mA .1U_4 10U_8 +3V R381 *10K_4 CK-410M *10P_4
.1U_4 .1U_4 .1U_4 (13,31) VR_PWRGD_CK410# 10 49 R_HCLK_MCH RP32 1 2 33_4P2R
Vtt_PwrGd#/PD CPUCLKT1 CLK_MCH_BCLK (5)
(13) PM_STPCPU# 62 48 R_HCLK_MCH# 3 4
CPU_STOP# CPUCLKC1 CLK_MCH_BCLK# (5)
R374 2.2/F_6 VDD_A (13) PM_STPPCI# 63
PCI/PCIE_STOP#
44
4 C259 C519 CGCLK_SMB CPUCLKT2/PCIET8 4
54 SCLK CPUCLKC2/PCIEC8 43
.1U_4 10U_8 CGDAT_SMB 55
SDATA
41
CLK_BSEL0 R164 4.7K_4 R_48M REQ1#/PCIET7
12 FSA/USB_48MHz REQ2#/PCIEC7 40
CLK_BSEL1 16
CLK_BSEL2 R152 4.7K_4 R_14M_SIO 61 FSB/TEST_MODE R_CLK_PCIE_3GPLL RP33 1
REF1/FSLC/TEST_SEL PCIET6 39 2 33_4P2R CLK_PCIE_3GPLL (6)
38 R_CLK_PCIE_3GPLL# 3 4
PCIEC6 CLK_PCIE_3GPLL# (6)
VDD_REF 56
VDD_SRC_CPU VDD_REF R_CLK_PCIE_DOCK RP34 1
50 36 2 33_4P2R CLK_PCIE_DOCK (29)
VDDCPU PCIET5 R_CLK_PCIE_DOCK#
25 mils PCIEC5
35 3 4 CLK_PCIE_DOCK# (29)
VDD_PCI 1
L55 VDD_PCI VDD_PCI_1 R_CLK_PCIE_ICH RP40 3
+3V 7 VDD_PCI_2 PCIET4 30 4 33_4P2R CLK_PCIE_ICH (12)
BK2125HS121-T_8 31 R_CLK_PCIE_ICH# 1 2
PCIEC4 CLK_PCIE_ICH# (12)
L:300mA C277 C276 C283 VDD_SRC_CPU 21
VDD_PCIE R_CLK_PCIE_SATA RP39 3
28 26 4 33_4P2R CLK_PCIE_SATA (11)
.1U_4 .1U_4 10U_8 VDDPCIE SATA_CKT R_CLK_PCIE_SATA#
42 27 1 2 CLK_PCIE_SATA# (11)
VDD_PCIE SATA_CKC
VDD_48 11 24
VDD_48 PCIET3
PCIEC3 25
CLKGN_REQ3_PCIE 32
R156 475_4 CLKGN_REQ4_PCIE REQ3(PCIE) R_CLK_PCIE_MINI1 RP38 3
(29) PCIE_CLKREQ# 33 REQ4(PCIE) PCIET2 22 4 33_4P2R CLK_PCIE_MINI1 (23)
R162 2.2/F_6 VDD_48 23 R_CLK_PCIE_MINI1# 1 2
PCIEC2 CLK_PCIE_MINI1# (23)
R150 475/F_6 IREF 47
C278 C530 IREF R_CLK_PCIE_LAN RP37 3
Iref=5mA, Ioh=4*Iref
PCIET1 19 4 33_4P2R CLK_PCIE_LAN (14)
20 R_CLK_PCIE_LAN# 1 2
PCIEC1 CLK_PCIE_LAN# (14)
.1U_4 10U_8
RP35 1 2 33_4P2R R_DOT96 14 17 R_DREFSSCLK RP36 3 4 33_4P2R
(6) DREFCLK DOT96MHz 27Mfix/LCD_SSCGT/PCIE0T DREFSSCLK (6)
3 4 R_DOT96# 15 18 R_DREFSSCLK# 1 2
(6) DREFCLK# DOT96MHz# 27SS/LCD_SSCGC/PCIE0C DREFSSCLK# (6)
5 R_PCLK_SIO R385 33_4
selPCIEX0_LCD#/PCI5 PCI_CLK_SIO (26)
T58 34 4 R_PCI_CLK_510 R160 33_4
GND_PCI_1
GND_PCI_2
PWRSAVE# PCI4 PCI_CLK_510 (19)
R_PCLK_PCM R379 33_4
GND_SRC
PCI3 3 PCI_CLK_CB714 (18)
GND_48
R149 1_6 VDD_REF INTERNAL PULL HIGH 64 R_PCLK_1394 R151 33_4
PCICLK2/REQ_SEL PCLK_1394 (21)
9 R_PCLK_ICH R163 33_4
GND
GND
GND
3 PCIF1/selLCD_27# PCLK_ICH (12) 3
C255 C248 R165 33_4 R_48M 8 R_PCLK_591 R386 33_4
(13) CLKUSB_48 PCIF0/ITP_EN PCLK_591 (24)
.1U_4 10U_8 ICS954310BGLF
53
13
59
2
6
29
37
pin5,pin9,pin32,pin33,pin34 internal PU
R153 33_4 R_14M_SIO pin64 internal PD
(26) SIO_14M
"EA report, fail in PCI_CLK_SIO. It is too fast.
C251 BOM change. R385 change to 33 ohm and unstuff R384."
*10P_4
R_PCLK_SIO R384 *10_4
PCLK_DEBUG_SW (24)
R383 10_4
PCLK_DEBUG_HW (23)
SEL2 SEL1 SEL0
PCIE CLK enable/disable control Starpping Terminal Resistor
R_PCLK_SIO R380 10K_4
Frequence select FSC FSB FSA CPU SRC PCI
1 0 1 100 100 33 CLK_CPU_BCLK# RP29 3 4 49.9_4P2R
+3V CLK_CPU_BCLK 1 2
Latched Select. (Pin 17,18) 0 0 1 133 100 33
R159 *10K_4CLKGN_REQ3_PCIE "0" : LCD CLK CLK_MCH_BCLK# RP30 3 4 49.9_4P2R
"1" : PCIEX CLK 0 1 1 166 100 33 Default CLK_MCH_BCLK 1 2
REQ3 Latched Select
"0" : CLK Enable 0 1 0 200 100 33 CLK_PCIE_SATA RP41 3 4 49.9_4P2R
CLK_PCIE_SATA# 1 2
"1" : CLK Disable Control : PCIE 2,4
R_PCLK_591 R382 10K_4
0 0 0 266 100 33 CLK_PCIE_LAN RP49 3 4 49.9_4P2R
1 0 0 333 100 33 CLK_PCIE_LAN# 1 2
ITP/SRC8 SELECT
0: SRC8 1 1 0 400 100 33 CLK_PCIE_3GPLL RP47 1 2 49.9_4P2R
2 1: ITP CLK_PCIE_3GPLL# 3 4 2
1 1 1 200 100 33 CLK_PCIE_MINI1 RP50 3 4 49.9_4P2R
CLK_PCIE_MINI1# 1 2
BSEL strappings need to be set for 533MHz Moby Dick
R_PCLK_ICH R161 10K_4 (Intel?915GM - Calistoga Interposer) CLK_PCIE_ICH RP42 3 4 49.9_4P2R
+3V
+3V (if Calistoga is designed for 667MHz board). CLK_PCIE_ICH# 1 2
SELLCD_27# Select. (Pin 17,18)
R155 10K_4 CLKGN_REQ4_PCIE "0" : 27MHzSS/27MHzSS# pair DREFSSCLK# RP51 3 4 49.9_4P2R
"1" : LCD CLK pair DREFSSCLK 1 2
REQ2 Latched Select +1.05V R390 *1K_4
"0" : CLK Enable DREFCLK# RP52 3 4 49.9_4P2R
DREFCLK 1 2
"1" : CLK Disable Control : PCIE 3,5,7 R389 0_4 CLK_BSEL0 R396 1K_4
(3) CPU_BSEL0 MCH_BSEL0 (6)
CLK_PCIE_DOCK RP48 1 2 49.9_4P2R
R_PCLK_1394 R154 *10K_4 R391 *1K_4 CLK_PCIE_DOCK# 3 4
+3V
PCIE CLK/REQ select
"0" : PCIE CLK
"1" : REQ pin
R394 *1K_4
Reserve for EMI
+1.05V
SM BUS level shift PCI_CLK_SIO C533 *10P_4
R393 0_4 CLK_BSEL1 R392 1K_4 MCH_BSEL1 (6)
(3) CPU_BSEL1
PCI_CLK_510 C284 *10P_4
+3V R395 *0_4
PCI_CLK_CB714 C526 *10P_4
PCLK_DEBUG_SW C534 *10P_4
R375 R376 PCLK_ICH C285 *10P_4
Q29
2
1 RHU002N06 10K_4 10K_4 +1.05V R372 *1K_4 PCLK_591 C286 *10P_4 1
3 1 CGDAT_SMB PCLK_1394 C250 *10P_4
(13,29) PDAT_SMB CGDAT_SMB (9,23)
R369 0_4 CLK_BSEL2 R370 1K_4
(3) CPU_BSEL2 MCH_BSEL2 (6)
R371 *0_4
+3V
PROJECT : ZU2
Q30
2
RHU002N06 Power check Quanta Computer Inc.
3 1 CGCLK_SMB
(13,29) PCLK_SMB CGCLK_SMB (9,23) +3V (3,6,8,9,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,32,34)
Size Document Number Rev
+1.05V (3,4,5,8,11,13,31,32,34)
Clock Gen. 1B
PCLK_SMB/PDAT_SMB(SB&LAN&MINI CARD&EZ,+3V_S5) CGCLK_SMB/CGDAT_SMB(CLK GEN&DDR,+3V) Date: Thursday, March 22, 2007 Sheet 2 of 39
A B C D E
5 4 3 2 1
T36
U28A
(5) H_A#[31:3] (5) H_D#[63:0] H_D#[63:0] (5)
H_A#3 J4 H1
A[3]# ADS# H_ADS# (5)
H_A#4 L4