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Ordering number: EN 2651B
Monolithic Linear IC
LA3246 Stereo Preamplifier for Compact Double Cassette Playback-only Use
Overview
The LA3246 is a stereo preamplifier IC for double cassette tape playback-only use. The LA3246 is intended for use in portable radio-cassette tape recorders and tape decks.
Package Dimensions
unit : mm
3021B-DIP20
[LA3246]
Applications
. Stereo compact cassette player for playback-only use . Stereo cassette deck player
Functions
. Preamplifier × 2, Mixing amplifier × 1, Electronic switch × 6
SANYO : DIP20 (300 mil)
Features
. On-chip electronic switch for input select (auto reverse or deck select) . A deck/Belectronic switch for normal/higher dubbing select On-chip metal/normal tape . and electronic switch forrange (V op = 3.5select V) Wide operating voltage to . With output MIX pin (for music select control) 14 . Low noise voltage range (V = 0.9 µV typ, Rg = 2.2 k NAB) . Can be used in conjunction with the LA3240, 3241, 3242 to
CC NI
easily make up a doublecassette dubbing system.
Specifications
Maximum Ratings at Ta = 25°C
Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC max Pd max Topr Tstg Conditions Ratings 16 500 20 to +75 40 to +125 Unit V mW °C °C
Maxiumum Ratings at Ta = 25°C
Parameter Recommended supply voltage Operating voltage range Symbol VCC VCC op Conditions Ratings 6 3.5 to 14 Unit V V
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
D3097HA(II)/41594HK/N107TA, TS No.2651-1/13
LA3246
Operating Characteristics at Ta = 25°C, VCC = 6.0 V, RL = 10 k, f = 1 kHz, 0 dB = 0.775 V
Parameter Quiescent current Voltage gain (Open) Voltage gain (Closed) Total harmonic distortion Maximum output voltage Crosstalk (between channels) Crosstalk (between F/R) Channel balance Equivalent input noise voltage MIX output voltage Ripple filter output current Electronic switch ON-state resistance DC feedback resistance Input bias current Symbol Icco Iccs VGo VG THD VO max CT1 CT2 VBL VNI VOMIX IF OUT Ron RF IF Conditions Nor/Nor speed forward Metal/High speed forward Nor/Nor speed, NAB VO = 0.65 V, Nor/Nor speed THD = 1%, Nor/Nor speed VO = 5 dBm, Rg = 2.2 k, Nor/Nor speed VO = 5 dBm, Rg = 2.2 k, Nor/Nor speed VIN = 50 dBm Rg = 2.2 k, B.P.F 20 Hz to 20 kHz, Nor/Nor speed VO1, VO2 = 0 dBm Between P1 to P4 and 5, between pin 16 and 17 Between P1 to P7 and 10, between pin 10 and 14 240 min 5 7 75 39.5 0.7 50 50 typ 7 10 85 40.5 0.03 1.2 65 65 0 0.9 0 10 100 30 300 0.5 max 12 17 41.5 0.2 Unit mA mA dB dB % V dB dB dB µV dB mA µA
3
2 1.7 +3 15 250 70 360 3.0
Allowable power dissipation, Pd max mW
Pd max Ta
Ambient temperature, Ta °C
Equivalent Circuit Block Diagram
Top view
No.2651-2/13
LA3246
Test Circuit
Sample Application Circuit
Unit (resistance: , capacitance: F) Note 1. The output frequency characteristic for Nor Tape/High speed mode (pin 6: High, pin 15: Low) and that for Metal Tape/Nor speed mode (pin 6: Low, pin 15: Low) are set to be the same. 2. Since the input bias current flows out of pins 1, 2 and pins 19, 20, a resistor (recommended value: 30 k to 350 k, maximum value: 500 k) must be connected a coupling capacitor in series with these pins. 3. *: A capacitor must be connected to the input to absorb a surge. 4. The electronic select switching level is approximately 1/2 × (VCC0.9). 5. The value of the capacitor connected to pin 12 can be increased/decreased to adjust starting time ts at the time of application of VCC. (C = 100 µF, ts = 0.4 s.) If the capacitor value is made less than 47 µF, the ripple rejection will get worse. 6. No capacitor is connected to pin 13. (Even if connected, the ripple can not be rejected.) 7. Extreme caution should be exercised when handling the IC as it is subject to dielectric breakdown. No.2651-3/13
LA3246
Sample Printed Circuit Pattern (Cu-foiled area)
Unit (resistance: , capacitance: F)
IC Usage Notes
(1) It is recommended to connect a surge absorbing capacitor across input pins 1, 2 and GND and across input pins 19, 20 and GND. (2) The base of a PNP transistor is connected to input pins 1, 2 and 19, 20. If an electrolytic capacitor is connected in series with the input pins, connect input resistor RIN must not exceed 500 k. (Reason: To minimize the variation in output DC voltage at the time of input switching)
If a resistor of more than 500 k is connected across input pin and GND, the noise (output) caused by amp 1 and amp 2 select is liable to increase at the time of F/R switching.
No.2651-4/13
LA3246
(3) When an electrolytic capacitor is connected to input pins 1, 2 (or 23, 24), make the value of RIN1 as equal to that of RIN2 as possible.
The difference in the value between RIN1 and RIN2 causes the variation in amp output DC voltage at the time of F/R switching. Therefore, the input DC voltage (voltage across RIN) must be made as equal as possible. (4) The amplifier output characteristics are designed to be the same in the Nor Tape/High Speed (pin 15 GND/pin 6 VCC) and Me Tape/Nor Speed (pin 15 VCC/pin 6 GND) modes. (Refer to sample application circuit, external constants.) (5) When externally turning ON/OFF power supply pin 11 (by bringing pin 11 to +VCC/GND level) with a capacitor connected to pin 13, connect external diode D, as shown below, so that no breakdown (or deterioration) of the IC system is caused by ICD when the switch is turned OFF. When no capacitor is connected to pin 13, diode D is not required.
(6) The output MIX circuit is of the emitter follower configuration as shown below.
Unit (resistance: ) The MIX OUT output level VO MIX at the time a signal is applied to preamp1 (or preamp2) only is 1/2 as compared with output levels VO1, VO2 at the time the same input signal is applied to both channels. VO MIX = 1/2 VO1(= 1/2 × VO2) where VO1 = VO2
No.2651-5/13
LA3246
(7) Output waveform starting time
Example of rise waveform at pin 4 (or 17)
When supply voltage VCC is switched ON, the amplifier output (pins 4, 17) will rise. Output waveform ON time ts can be varied by capacitor Cr connected to pin 12. Refer to Data Cr ts. The minimum value of Cr is 47 µF. (8) Electronic select switching level The switch level at VCC = 6.0 V is shown below.
.
Switching Level Pin Switch Mode Operation Start 6 9 15 Normal/Metal Forward/Reverse Normal/Higher 2.1 V 2.1 V 2.1 V Operation Finish 2.4 V 3.1 V 2.4 V Clamp Voltage
Control Current typ (flow-in) (at operation finish) 2 µA 2 µA 2 µA
Mode (+) Metal Reverse Higher () Normal Forward Normal
3.7 V 3.4 V 3.7 V
As shown above, there is a difference in the switching level at three control pins (6, 9, 15) between operation start and operation finish.
. Switching level and mode at each pin (experimental value)
Switching level (reverse) on pin 9 at VCC = 6.0 V, Ta = 25°C
(Metal) (Higher) Switching level region at pins 6, 15.
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LA3246
. Control circuit
The control circuit for each CONT pin is configured as shown below. When a voltage more than a given value is applied, the level on the pin is fixed by clamp diode D1.
Control pin
Current route at clamp mode Note: For D1, a Schottky diode is used for pin 9 and a silicon diode is used for pins 6, 15.
Unit (resistance: , capacitance: F)
Description
. Switching level V . Clamp voltage V
SW
of the control circuit is fixed by voltage V13 which is 1/2 of the voltage on pin 13.
VSW = 1/2 V13
CLP
at the time a voltage is applied to the CONT pin
VCLP = 1/2 × V13 + VD1 + VBE1 = 1/2 × V13 + 0.6 (0.3) + 0.6 = 1/2 × V13 + (0.9 or 1.2)
where 0.9 V is for pin 9. 1.2 V is for pins 6, 15.
. The maximum voltage at which the CONT pin is brought to GND level is fixed by the level at which the Q2 is completely
turned OFF. This level is: 1/2 × V13 VBE2 = 1/2 × V13 0.6 [V] Switching is performed at a level less than this.
. To turn ON/OFF
When turning ON:
To turn ON the control circuit to finish the operation, IB is required. Control voltage
VOUT is obtained with IB of 4 µA min.
.V .
min = R × IB max + Operation finish voltage. IB = 4 µA Operation finish voltage Pins 6, 15 : = 1/2 × V13 Pin 9 : = 1/2 × V13 + VBE = 1/2 × V13 + 0.6 [V] VCONT max = R × IB max + Clamp voltage R is restricted by IB max. When the supply voltage is fixed, clamp voltage VCLP is fixed. When resistor R is fixed based on a balance with capacitor C, resistor R is restricted by VCONT max. as shown below.
CONT
IB max = 100 µA ^
VCONT max VCLP R
The minimum value of resistor R is fixed by this equation. Example Assuming VCC = 10 V, VCONT max = 10 V, Rmin is 50 k. Therefore, R = 100 k presents no problem. When turning OFF: Bring the level on the CONT pin to a level less than: 1/2 × V13 VBE2 = 1/2 × V13 0.6 [V] No.2651-7/13
LA3246
(9) Example of voltage on each pin
Rg = 2.2 k, Ta = 25°C, VIN = 0, pins 6, 9 and 15 = GND Supply voltage, VCC V 4.5 V 0.3 0.3 0.59 1.63 1.63 (GND) 0 0 1.63 (GND) 0 (GND) 0 VCC 4.48 3.72 0 (GND) 0 1.63 1.63 0.59 0.3 0.3 6.0 V 0.3 0.3 0.58 2.23 2.23 (GND) 0 0 2.29 (GND) 0 (GND) 0 VCC 5.96 5.20 0 (GND) 0 2.23 2.23 0.58 0.3 0.3 9.0 V 0.3 0.3 0.57 3.65 3.65 (GND) 0 0 3.64 (GND) 0 (GND) 0 VCC 8.97 8.21 0 (GND) 0 3.65 3.65 0.57 0.3 0.3 12.0 V 0.3 0.3 0.56 5.02 5.02 (GND) 0 0 5.01 (GND) 0 (GND) 0 VCC 11.23 11.98 0 (GND) 0 5.02 5.02 0.56 0.3 0.3
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Unit mV mV V V V V V V V V V V V V V V V V mV mV
Quiescent current, Iccs (Electronic SW ON) mA Quiescent current, Icco mA
Iccs, Icco VCC
IB VCC
Nor/High and Me/Nor SW on: Pins 6 and 15 are brought to supply voltage level.
Supply voltage, VCC V VDC VCC Voltage gain (open), VGo dB Voltage gain (closed), VG dB
Input bias current, IB µA
Supply voltage, VCC V VGo, VG fi
DC voltage, VDC V
Pin 12 Pin 13 Pins 4, 19 Pins 3,18
Supply voltage, VCC V
Input frequency, fi Hz No.2651-8/13
LA3246
VG fi Voltage gain (closed), VG dB Voltage gain (closed), VG dB VG VCC
Input frequency, fi Hz VO max VCC Maximum output voltage, VO max V Output voltage, VO V Total harmonic distortion, THD %
Supply voltage, VCC V VO, THD VIN
Supply voltage, VCC V VNO VCC Output noise voltage, VNO µV
Input voltage, VIN dBm VO MIX VCC
Maximum output voltage, VO max, VO MIX V
CH1 only operated
Supply voltage, VCC V
Crosstalk (between channels), CT1 dB
Supply voltage, VCC V VO max, VO MIX VCC
Pin 8 voltage, VO MIX V
Supply voltage, VCC V CT1 VCC
Supply voltage, VCC V No.2651-9/13
CH2 crosstalk (between forward and reverse), CT8 dB c
Crosstalk (between channels), CT6 dB
Crosstalk (between channels), CT4 dB
Crosstalk (between forward and reverse), CT2 dB
CT2 VCC
Input frequency, fi Hz CT6 fi
Input frequency, fi Hz
CT8 fi
LA3246
Output noise voltage, VNO µV
CH1 Crosstalk (between forward and reverse), CT7 dB
Crosstalk (between channels), CT5 dB
Supply voltage, VCC V CT4 fi
Input frequency, fi Hz Input frequency, fi Hz CT5 fi Input frequency, fi Hz CT7 fi
Crosstalk (between channels), CT3 dB
CT3 fi
Input frequency, fi Hz
VNO Rg
Signal source resistance, Rg
No.2651-10/13
LA3246
Equivalent input noise voltage, VNI µV VNO Rg Output noise voltage, VNO µV VNI Rg
Signal source resistance, Rg VGo VCC Voltage gain (open), VGo dB Voltage gain (closed), VG dB
Signal source resistance, Rg VG fi
Supply voltage, VCC V Rr fr Ripple rejection ratio, Rr dB Ripple rejection ratio, Rr dB
Input frequency, fi Hz Rr Cr
Cr = 47 µF or greater
(Pin 12)
Ripple frequency, fr Hz tS Cr
Capacitor for ripple filter (pin 12), Cr µF tS CNF
Starting time, tS sec
Starting time, tS sec
Cr = 47 µF or greater
or less
Capacitor for ripple filter (pin 12), Cr µF
Reverse transfer capacitance, CNF µF No.2651-11/13
LA3246
Ron, V VCC Iccs, Icco Ta
Quiescent current, Iccs mA Quiescent current, Icco mA
ON Resistance, Ron Voltage drop, V mV
* Me/High SW on: Pins 6, 15 are
brought to supply voltage level.
VR: Voltage across 2.7 k resistor
Supply voltage, VCC V Maximum output voltage, VO max V VG Ta Voltage gain (closed), VG dB
Ambient temperature, Ta °C VO max Ta
Ambient temperature, Ta °C Crosstalk (between channels), CT9 dB VBL Ta
Ambient temperature, Ta °C CT9 Ta
Channel balance, VBL V
Ambient temperature, Ta °C VODC Ta
Ambient temperature, Ta °C IB Ta
Ambient temperature, Ta °C
Input bias current, IB µA
DC voltage, VODC V
Ambient temperature, Ta °C No.2651-12/13
LA3246
No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. Anyone purchasing any products described or contained herein for an above-mentioned use shall: 1 Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: 2 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice.
No.2651-13/13