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Application Note 120
Cyrix III CPU BIOS
Writer's Guide
Cyrix Processors
Running H/F 2
REVISION HISTORY
Date Version Revision
11/24/99 1.1 Updated register 49h and DIR1 table
5/20/99 1.0 Updated for Cyrix III
4/19/99 0.43 Format changes, chapter 6.
3/22/99 0.42 Changed processor internal code name from MXs to Cyrix III.
3/17/99 0.41 Page 55: Added Core to Bus Clock Ratio Configuration Register.
2/23/99 0.4 Added Confidential Notice. Made all pages same width.
1/29/99 0.3 Minor changes:
Changed fonts, added revision page, changed DIR table titles
12/14/98 0.2 Cyrix III information added. Completed Table page 32
9/21/98 0.1 Intial First Draft based on App Notes 112 and 118.
C:\documentation\joshua\appnotes\j120ap.fm (confidential)
1 Cyrix Application Note 120 - Cyrix III BIOS Writer's Guide
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Table of Contents
1.0 Introduction
1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Cyrix Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Summary of Cyrix III, MII, 6x86MX and 6x86 Differences . . . . . . . . . . . . . . . . . . . . 4
2.0 Cyrix III CPU Detection
2.1 CPU Detection and Inquiry Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 CPU Detection Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Standard and Extended CPUID Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Non CPUID Test and Inquiry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.0 Cyrix III Configuration Register Index Assignments
3.1 Accessing a Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Cyrix III Configuration Register Index Assignments . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 Configuration Control Registers (CCR0-6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4 Address Region Registers (ARR0-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5 Region Control Registers (RCR0-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6 BIOS Clock Multiplier Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.0 Recommended Cyrix III Configuration Register Settings
4.1 PC Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2 General Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3 Recommended Bit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.0 Model Specific Registers
5.1 Time Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.2 Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3 Performance Monitoring Counters 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.4 Counter Event Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.5 PM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.0 Programming Model Differences
6.1 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.2 Configuring Internal Cyrix III Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3 INVD and WBINVD Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.4 Control Register 0 (CR0) CD and NW Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Appendix A -Sample Code: Detecting a Cyrix CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Appendix B -Sample Code: Determining CPU MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Appendix C -Example CPU Type and Frequency Detection Program . . . . . . . . . . . . . . . . 63
Appendix D -Sample Code: Programming Cyrix III Configuration Registers . . . . . . . . . . 65
Appendix E -Sample Code: Controlling the L1 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Appendix F -Example Configuration Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Cyrix Application Note 120: Cyrix III BIOS Writer's Guide 2
APPLICATION NOTE 120 Cyrix III BIOS Writer's Guide
1. Introduction
1.1 Scope
This document is intended for Cyrix III system BIOS writers. It is not a stand-alone
document, but a supplement to other Cyrix documentation including the Cyrix III
Data Books, and Cyrix SMM Programmer's Guide. Recommendations for Cyrix
III detection and configuration register settings are included.
The recommended settings are optimized for performance and compatibility in
Windows95 or Windows NT, Plug and Play (Pnp), PCI-based system. Performance
optimization, CPU detection, chipset initialization, memory discovery, I/O recov-
ery time, and other functions are described in detail.
3 Cyrix Application Note 120 - Cyrix III BIOS Writer's Guide
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1.2 Cyrix Configuration Registers
The Cyrix III uses on-chip configuration registers to control the on-chip cache, system management mode
(SMM), device identification, and other Cyrix III specific features. The on-chip registers are used to activate
advanced performance features. These performance features may be enabled "globally" in some cases, or
by a user-defined address region. The flexible configuration of the Cyrix III is intended to fit a wide variety
of systems.
BIOS needs to perform 3 basic functions outlined in this document. They are:
1) Identification of Cyrix III cpu, frequency, and performance rating.
2) Set up of Configuration Registers in the cpu to enable features, turn on cache, and set clock multiplier.
3) Set up Address Region Registers and Region Control Registers to control memory accesses.
The Importance of Non-Cacheable Regions
The Cyrix III has fourteen internal user-defined Address Region Registers and Region Control Registers.
Among other attributes, the regions define cacheability of the address regions. Using this cacheability infor-
mation, the Cyrix III is able to implement high performance features, that would otherwise not be possible.
A non-cacheable region implies that read sourcing from the write buffers, data forwarding, data bypassing,
speculative reads, and fill buffer streaming are disabled for memory accesses within that region. Addition-
ally, strong cycle ordering is also enforced.
The Cyrix III also uses these Address Region Registers to setup the write gathering, or write combining, fea-
ture normally used for improving performance of video buffer memory. This feature is enabled differently
from the Intel Celeron. Celeron uses machine specific registers (MSR's) called memory type and range reg-
isters (MTRR's). Cyrix III uses the Address Region Registers (ARR's) and Region Control Registers
(RCR's) to perform this same feature. Thus BIOS, operating system calls, and video drivers should be
updated with ARR and RCR setup instead of MTRR setup whenever Cyrix III is detected to enable write
combining feature.
Cyrix Application Note 120: Cyrix III BIOS Writer's Guide 4
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2. CPU Detection
The Cyrix III cpu can be identified using the CPU_ID instruction as explained below. It can also be
identified using Cyrix specific Device Identification Registers (DIR). The methods for identifying the cpu
and its available features are explained below. Once the Cyrix III cpu is identified, it should be named
correctly as explained in the next section.
2.1 CPU Name and Performance Rating
The Cyrix III uses the performance rating system of speed measurement and reporting. The following table
is used to identify the performance rating of the Cyrix III compared to actual Mhz. The performance rating is
achieved by benchmarking the Cyrix III vs. a Celeron cpu in the same configuration.
CPU Name and PR rating Bus Speed Mhz Core Speed Mhz Clock Multiplier
Cyrix III - 433 100 350 3.5
Cyrix III - 466 122 366 3.0
Cyrix III - 500 133 400 3.0
Cyrix III - 533 124 433 3.5
Cyrix III - 533 100 450 4.5
Cyrix III - 566 133 466 3.5
Cyrix III - 600 100 500 5.0
2.2 Cyrix CPU Identification and Inquiry Flow Chart
The Cyrix CPU Identification process (Figure1 on page6) consists of up to three tests and three inquiries. If
CPUID is not supported, a 5/2 Test is performed to check if the CPU is a Cyrix part. If CPUID is supported,
a second test is made to see if extended level CPUID is supported.
5 Cyrix Application Note 120 - Cyrix III BIOS Writer's Guide
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The numbers in parenthesis shown in Figure 1 refer to the supporting paragraphs in this manual.
Cyrix CPU Detection and Inquiry
Supports CPUID? (3.1)
No Yes
Cyrix CPU (3.2)
(Perform "CyrixInstead" Test)?
Yes No
Perform DIR0, DIR1 Inquiry Non-Cyrix CPU
(3.4.2)
Exit
Supports Extended CPUID?
(3.3.1)
Yes
No
Perform Standard CPUID Perform Extended CPUID Inquiry
(3.3.2) (3.3.3)
FIGURE 1. CPU Identification and Inquiry
Note: The testing must be performed in the order shown in Figure 1 or testing may be invalid.
Cyrix Application Note 120: Cyrix III BIOS Writer's Guide 6
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2.3 CPU Detection Steps: CPUID Support Test
In order to avoid an invalid opcode exception on processors that do not support the CPUID instruction, soft-
ware must first verify that the processor supports the CPUID instruction. The presence of the CPUID
instruction is indicated by the ID bit (bit 21) in the EFLAGS register. If this bit can be toggled, the CPUID
instruction is present and enabled on the processor. The following code will check for the presence of the
CPUID instruction.
CPUID Support Test Sample Code*:
pushfd ; get extended flags
pop eax ; store extended flags in eax
mov ebx, eax ; save current flags
xor eax, 200000h ; toggle bit 21
push eax ; put new flags on stack
popfd ; flags updated now in flags
pushfd ; get extended flags
pop eax ; store extended flags in eax
xor eax, ebx ; if bit 21 r/w then eax <> 0
je no_cpuid ; can't toggle id bit (21) no cpuid here
*Note: It has been assumed that the tests for EFLAGS support has been complete prior to this point. If
CPUID is supported, it can be assumed that the CPU is an 80486 or above class processor.
2.3.1 "CyrixInstead" Test
The CPUID instruction level 0 provides vendor information. Following execution of the CPUID instruction
with an input value of "0" in EAX, the EBX, ECX and EDX registers contain the vendor string of the CPU.
To verify that the processor is a Cyrix CPU, the software checks for "CyrixInstead" in the return registers as
shown in the sample code below:
"CyrixInstead" Test Sample Code
mov eax, 0 ; CPUID standard level 0
cpuid
cmp ebx, 'iryC'
jne not_cyrix
cmp edx, 'snIx'
jne not_cyrix
cmp ecx, 'daet'
jne not_cyri
7 Cyrix Application Note 120 - Cyrix III BIOS Writer's Guide
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2.4 Standard and Extended CPUID Levels
The CPUID instruction has been extended on recent processors so that additional information can be
obtained from the CPU concerning items including stepping, model, family, type, TLB and cache informa-
tion. The original levels of the CPUID instruction are termed "the standard CPUID levels" and the newer
levels are termed the "extended CPUID levels."
The standard and extended CPUID levels differ in that the EAX register's most significant bit is set for the
extended CPUID levels. Both the standard and extended CPUID levels may be executed at any privilege
level. The EAX register provides the input value for the CPUID instruction to indicate what information
should be returned by the instruction.
2.4.1 Extended CPUID Level Support Testing
This test is performed to determine if the CPU supports the extended CPUID levels.
Extended CPUID Instruction support testing consists of executing a CPUID instruction with the EAX regis-
ter initialized to 8000 0000h and testing the return value in EAX. If a value greater than or equal to 8000
0000h is returned to the EAX register by the CPUID instruction, the CPU can execute extended CPUID
instructions. The following sample code tests for Extended CPUID support.
Extended CPUID Instruction Test Sample Code:
mov eax, 80000000h ; try extended cpuid level
cpuid ; execute cpuid instruction
cmp eax, 80000000h ; check if extended levels are supported
jb no_extended ; extended cpuid functions not available
Cyrix Application Note 120: Cyrix III BIOS Writer's Guide 8
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2.4.2 Standard CPUID Instruction Inquiry
The CPUID instruction provides processor and feature set information. This instruction may be executed at
any privilege level. The standard CPUID instruction is defined as a CPUID instruction with the EAX regis-
ter initialized to one of the following values:
0000 0000h - maximum standard levels supported and vendor string
0000 0001h - family, model and stepping information
0000 0002h - cache and TLB information
Table 1. summarizes the CPUID values returned by standard CPUID levels on Cyrix III processors.
Table 1. Summary of Returned
Standard CPUID Values
IN ITIAL
DESCRIPTION EAX CYRIX III
V ALUE
Maximum 0h 2h
Standard Value
Stepping 1h xxh
Model 1h 5h
Family 1h 6h
Type 1h 0h
TLB/Cache 2h xxh
Note: xx = stepping revision specific.
9 Cyrix Application Note 120 - Cyrix III BIOS Writer's Guide
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2.4.3 CPUID Instruction with EAX = 0000 0000h
Standard function 0h (EAX = 0) of the CPUID instruction returns the maximum standard CPUID levels sup-
ported by the current processor to the EAX register. The maximum standard CPUID level is the highest
acceptable value for the EAX register input.
After the instruction is executed registers EBX through EDX contain the vendor string of the processor.
Note that the middle section is placed (out of order) into the EDX register (Table 2).
Table 2. Standard CPUID with EAX = 0000 0000h
REGISTER * C ONT ENT S
EAX Max Standard Levels
EBX Vendor ID String 1="CYRI"
EDX Vendor ID String 2="XINS"
ECX Vendor ID String 3="TEAD"
*Note: The register order is correct.
Cyrix Application Note 120: Cyrix III BIOS Writer's Guide 10
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2.4.4 CPUID Instruction with EAX = 0000 0001h
Standard function 01h (EAX = 1) of the CPUID instruction returns the Processor Type, Family, Model, and
Stepping information of the current processor in EAX (Table 3). The Standard Feature Flags supported are
returned in the EDX register. The other registers upon return are currently reserved.
Table 3. Standard CPUID with EAX = 0000 0001h
REGISTER CONTENTS
EAX[3:0] Stepping ID=revision specific step id
EAX[7:4] Model=5 h
EAX[11:8] Family=6 h
EAX[15:12] Type=0 h
EAX[31:16] Reserved
EBX Reserved
ECX Reserved
EDX Standard Feature Flags=0080A13D h
Standard Feature Flags
The standard feature flags are returned in the EDX register when the CPUID instruction is called with stan-
dard function 01h (EAX = 1). Each flag refers to a specific feature and indicates if that feature is present on
the processor. Some of these features require enabling or have protection control in CR4. Table 4. summa-
rizes the standard feature flags.
11 Cyrix Application Note 120 - Cyrix III BIOS Writer's Guide
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Before using any of these features on the processor, the software should check the corresponding feature
flag (Table 4). Attempting to execute an unavailable feature can cause exceptions and unexpected behavior.
For example, software must check bit 4 before attempting to use the Time Stamp Counter instruction.
Table 4. Standard Feature Flags Values Returned
in EDX
EDX B IT
CR4 B IT
C YRIX III
FEATUR E F LAG
FPU On-Chip 0 - 1
Virtual Mode Extensions (V86) 1 0,1 01
Debug Extension 2 3 1
4 MB Page Size 3 4 1
Time Stamp Counter 4 2 1
RDMSR/WRMSR Instructions 5 8 1
Physical Address Extensions 6 5 0
Machine Check Exception 7 6 0
CMPXCHG8B Instruction Support 8 - 1
On-chip APIC Hardware 9 - 0
Reserved 10 - 0
SYSENTER/SYSEXIT Instructions 11 - 0
Memory Type Range Registers (MTRR) 12 - 0
Page Global Enable (PTE-PGE) 13 7 1
Machine Check Architecture 14 - 0
Conditional Move Instruction (CMOV) 15 - 1
Page Attribute Table 16 - 0
36-Bit Page Size Extensions 17 - 0
Reserved 18-22 - 00000
MMXTM Instructions 23 - 1
Fast FPU Save and Restore 24 - 0
Reserved 25-31 - 0000000
*Note: The CPUID instruction is disabled by default.
Cyrix Application Note 120: Cyrix III BIOS Writer's Guide 12
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2.4.5 CPUID Instruction with EAX = 0000 0002h
Standard function 02h (EAX = 02h) of the CPUID instruction returns information that is specific to the
Cyrix family of processors. Information about the TLB is returned in EAX. Information about the L1 Cache
is returned in EDX. This information is to be looked up in a lookup table. See Table 13 on page 19.
Table 5. Standard CPUID with EAX = 0000 0002h
REGISTER C ON TEN TS
EAX TLB Information = 00747701 h
EBX Reserved
ECX Reserved
EDX L1 Cache Information = 00008242 h
13 Cyrix Application Note 120 - Cyrix III BIOS Writer's Guide
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2.4.6 Extended CPUID Levels
The extended CPUID Instruction is defined when the EAX register is initialized to one of the following
values (Table 6.):
8000 0000h - Maximum Levels
8000 0001h - Processor Information/Extended features
8000 0002h - Processor Marketing Name
8000 0003h - Processor Marketing Name
8000 0004h - Processor Marketing Name
8000 0005h - TLB/Cache Information
Each of the extended CPUID levels reports information that is specific to the Cyrix family of processors.
Table 6. Summary of
Returned Extended CPUID
Values
INITIA L
D ESCRIPTION CYRIX III
EAX V ALU E
Extended 8000 0000h 5h
Levels
TLB Info 8000 0005h TBD
Cache Info 8000 0005h TBD
*Note: The CPUID instruction is disabled by default.
Table 7. Summary of CPUID Functions
E XTENDED
D ESCRIPTION CYRIX III
F UNCTION
8000 0000h Extended Levels X
8000 0001h Extended Processor Info. X
Extended Feature Flags
8000 0002h Processor Marketing Name X
8000 0003h Processor Marketing Name X
8000 0004h Processor Marketing Name X
8000 0005h TLB & Cache Information X
Cyrix Application Note 120: Cyrix III BIOS Writer's Guide 14
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2.4.7 CPUID Instruction with EAX = 8000 0000h
Extended function 8000 0000h (EAX = 8000 0000h) of the CPUID instruction returns the maximum
extended CPUID levels supported by the current processor in EAX (Table 8). The other registers are cur-
rently reserved.
Table 8. Maximum Extended CPUID Level
REGISTER C ON TENTS
EAX Maximum Extended Levels = 5 h
EBX Reserved
ECX Reserved
EDX Reserved
15 Cyrix Application Note 120 - Cyrix III BIOS Writer's Guide
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2.4.8 CPUID Instruction with EAX = 8000 0001h
Extended function 8000 0001h (EAX = 8000 0001h) of the CPUID instruction returns the Processor Type,
Family, Model, and Stepping information of the current processor in EAX (Table 9). The Extended Feature
Flags supported are returned in EDX. The other registers are currently reserved.
Table 9. . Processor Signature and Extended Feature Flags
REGISTER C ON TENTS
EAX[3:0] Stepping ID = revision specific step id
EAX[7:4] Model = 5
EAX[11:8] Family = 6
EAX[15:12] Processor Type = 0
EAX[31:16] Reserved
EBX Reserved
ECX Reserved
EDX Extended Feature Flags = 0080A13D
Extended Feature Flags
The extended feature flags are returned in the EDX register when the CPUID instruction is called with
extended function 8000 0001h (EAX = 8000 0001h). Each flag refers to a specific feature and indicates if
that feature is present on the processor. Some of these features require enabling or have protection control in
CR4. Table 10. summarizes the extended feature flags.
Cyrix Application Note 120: Cyrix III BIOS Writer's Guide 16
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Table 10. Extended Feature Flags
F EATURE F LAG EDX B IT CR4 B IT C YR IX III
Floating Point Unit 0 - 1
Virtual Mode Extensions (V86) 1 0,1 01
Debug Extension 2 3 -
Page Size Extensions (4 MByte) 3 4 -
Time Stamp Counter 4 2 X
Cyrix Model-Specific Registers (MSR) 5 8 X
Reserved 6 - -
Machine Check Exception 7 6 -
CMPXCHG8B Instruction 8 - X
SYSCALL and SYSRET Instructions 11 - -
Reserved 12 - -
Global Paging Extension (PTE-PGE) 13 7 -
Reserved 14 - -
Integer Conditional Move Instructions (CMOV) 15 - X
Floating-Point Conditonal Move Instructions 16
Reserved 17-22 - -
MMXTM Instructions 23 - X
Cyrix 6x86MX Multimedia Extensions 24 - X
Reserved 25 - 30 - -
3DNow!TM Instructions 31 - X
17 Cyrix Application Note 120 - Cyrix III BIOS Writer's Guide
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2.4.9 CPUID Instruction with EAX = 8000 0002h - 8000 0004h
Extended functions 8000 0002h through 8000 0004h (EAX = 8000 0002h through EAX = 8000 0004h) of
the CPUID instruction returns an ASCII string containing the name of the current processor (Table 11).
These functions eliminate the need to look up the processor name in a lookup table. Software can simply call
these functions to obtain the name of the processor. The string may be 48 ASCII characters long, and is
returned in little endian format. If the name is shorter than 48 characters long, the remaining bytes will be
filled with ASCII NUL character (00h).
Table 11. Official CPU Name
8000 0002 H 8000 0003H 8000 0004 H
EAX CPU Name 1 EAX CPU Name 5 EAX CPU Name 9
EBX CYRI EB X CPU Name 6 EBX CPU Name 10
ECX X II EC X CPU Name 7 ECX CPU Name 11
EDX I(tm) EDX CPU Name 8 EDX CPU Name 12
Cyrix Application Note 120: Cyrix III BIOS Writer's Guide 18
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2.4.10 CPUID Instruction with EAX = 8000 0005h
Extended function 8000 0005h (EAX = 8000 0005h) of the CPUID instruction returns information about the
TLB and L1 Cache to be looked up in a lookup table. Refer to Tables Figure 12 and Figure 13 shown below.
Table 12. Cache and TLB Information
R EGIST ER C ONT EN TS
EAX Reserved
EBX TLB Information
ECX L1 Cache Information
EDX Reserved
Table 13. Cache and Descriptor Lookup Table
CPUID
R EGISTER V ALUE COMMENTS
L EVEL
Standard EAX The CPUID instruction needs to be executed only once with an
xx xx xx 01h input value of 02h to retrieve complete information about the
Extended EBX cache and TLB.
Standard EAX
xx xx 70 xxh TLB is 32 Entry, 4-way set associative, and has 4 KByte Pages
Extended EBX
Standard EDX L1 cache is 16 KBytes, 4-way set associative, and has 16 bytes
xx xx xx 80h
Extended ECX per line.
19 Cyrix Application Note 120 - Cyrix III BIOS Writer's Guide
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2.5 Non-CPUID Testing and Inquiry
The Cyrix III processor supports CPUID to determine processor type. If it is a Cyrix processor, inquires may
also be made to the Device Identification Registers (DIR0 and DIR1) to determine which Cyrix processor is
present.
2.5.1 DIR0, DIR1 Inquiry
After determining that a Cyrix processor without CPUID exists, its Device ID Registers (DIR) can be read to
identify the Cyrix processor type. The Device ID Registers are located using register indexes FEh and FFh.
Access to these registers is achieved by writing the index of the register to I/O port 22h. I/O port 23h is then
used for data transfer. Each port 23h data transfer must be preceded by a port 22h-register index selection;
otherwise the second and later port 23h operations are directed off-chip and produce external I/O cycles.
The Tables 14 and 15 describe the bit definitions for the DIR0 and DIR1 Registers.
Table 14. DIR0 Bit Definitions
B IT P OSIT ION D ESCR IPTION
7-4 CPU Device Identification Number (read only)
3-0 CPU Clock Multiplier (read only)
Table 15. DIR1 Bit Definitions
B IT P OSIT ION DESCRIPTION
7-4 CPU Step Identification Number (read only)
3-0 CPU Revision Identification (read only)
Cyrix Application Note 120: Cyrix III BIOS Writer's Guide 20
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Table 16. describes the range of DIR0 values for the different generations of Cyrix CPU's
Table 16. CPU Generation Values in DIR0
DIR0 V ALUES D ESCRIPT ION
80h - 8Fh Cyrix III
Table 17. Cyrix III CPU DIR
Values
CORE CL OCK T O
DIR0
B US CL OCK RAT IO
84h 2.5 x
81h 3.0 x
85h 3.5 x
82h 4.0 x
86h 4.5 x
83h 5.0 x
87h 5.5 x
88h 6.0 x
8Ah 6.5 x
89h 7.0 x
8Bh 7.5 x
21 Cyrix Application Note 120 - Cyrix III BIOS Writer's Guide
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3. Cyrix III Configuration Register Index Assignments
On-chip configuration registers are used to control the on-chip cache, system management mode and other
Cyrix III unique features.
3.1 Accessing a Configuration Register
Access to the configuration registers is achieved by writing the index of the register to I/O port 22h. I/O port
23h is then used for data transfer. Each I/O port 23h data transfer must be preceded by an I/O port 22h regis-
ter index selection, otherwise the second and later I/O port 23h operations are directed off-chip and produce
external I/O cycles. Reads of I/O port 22h are always directed off-chip. Appendix D contains example code
for accessing the Cyrix III configuration registers.
3.2 Cyrix III Configuration Register Index
Assignments
The table on the following page lists the Cyrix III configuration register index assignments. After reset, con-
figuration registers with indexes C0-CFh and FC-FFh are accessible. In order to prevent potential conflicts
with other devices which may use ports 22 and 23h to access their registers, the remaining registers (indexes
00-BFh, D0-FBh) are accessible only if the MAPEN(3-0) bits in CCR3 are set to 1h. With MAPEN(3-0) set
to 1h, any access to an index in the 00-FFh range does not create external I/O bus cycles. Registers with
indexes C0-CFh, FC-FFh are accessible regardless of the state of the MAPEN bits. If the register index num-
ber is outside the C0-CFh or FE-FFh ranges, and MAPEN is set to 0h, external I/O bus cycles occur. The
table on the next page lists the MAPEN values required to access each Cyrix III configuration register. The
configuration registers are described in more detail in the following sections.
Cyrix Application Note 120: Cyrix III BIOS Writer's Guide 22
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Table 18. Configuration Register Index Assignments
R EGIST ER W IDTH
REGISTER NA ME ACR ONYM MAPEN(3-0)
INDEX (BITS)
00h-BFh Reserved -- -- --
C0h Configuration Control 0 CCR0 8 Don't care
C1h Configuration Control 1 CCR1 8 Don't care
C2h Configuration Control 2 CCR2 8 Don't care
C3h Configuration Control 3 CCR3 8 Don't care
E8h Configuration Control 4 CCR4 8 1h
E9h Configuration Control 5 CCR5 8 1h
EAh Configuration Control 6 CCR6 8 1h
EBh Configuration Control 7 CCR7 8 1h
C4h-C6h Address Region 0 ARR0 24 Don't care
C7h-C9h Address Region 1 ARR1 24 Don't care
CAh-CCh Address Region 2 ARR2 24 Don't care
CDh-CFh Address Region 3 ARR3 24 Don't care
D0h-D2h Address Region 4 ARR4 24 1h
D3h-D5h Address Region 5 ARR5 24 1h
D6h-D8h Address Region 6 ARR6 24 1h
D9h-DBh Address Region 7 ARR7 24 1h
A4h-A6h Address Region 8 ARR8 24 x01x
A7h-A9h Address Region 9 ARR9 24 x01x
AAh-ACh Address Region A ARRA 24 x01x
ADh-AFh Address Region B ARRB 24 x01x
D0h-D2h Address Region C ARRC 24 x01x
D6h-D8h Address Region D ARRD 24 x01x
DCh Region Configuration 0 RCR0 8 1h
DDh Region Configuration 1 RCR1 8 1h
DEh Region Configuration 2 RCR2 8 1h
DFh Region Configuration 3 RCR3 8 1h
E0h Region Configuration 4 RCR4 8 1h
E1h Region Configuration 5 RCR5 8 1h
E2h Region Configuration 6 RCR6 8 1h
E3h Region Configuration 7 RCR7 8 1h
DCh Region Configuration 8 RCR8 8 x01x
DDh Region Configuration 9 RCR9 8 x01x
DEh Region Configuration A RCRA 8 x01x
23 Cyrix Application Note 120 - Cyrix III BIOS Writer's Guide
Running H/F 2
Table 18. Configuration Register Index Assignments
DFh Region Configuration B RCRB 8 x01x
E0h Region Configuration C RCRC 8 x01x
E1h Region Configuration D RCRD 8 x01x
E4h-E7h Reserved -- -- --
EBh-FAh Reserved -- -- --
FBh Device Identification 2 DIR2 8 1h
FCh Device Identification 3 DIR3 8 1h
FDh Device Identification 4 DIR4 8 1h
FEh Device Identification 0 DIR0 8 Don't care
FFh Device Identification 1 DIR1 8 Don't care
48h Bus Configuration Register 1 BCR1 8 0100
49h Bus Configuration Register 2 BCR2 8 0100
41h L2 Configuration Register 1 LCR1 8 0100
20h Table Walk Register 0 TWR0 8 0001
Cyrix Application Note 120: Cyrix III BIOS Writer's Guide 24
Running H/F 2
The Cyrix III configuration registers can be grouped into five areas: