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A B C D E
DVA620 REV-A2 ES60X8 + 8051 + PT2320
Layout---------RUTHERFORD REV-A1B1
4 4
Background Revision History
This DVD design is based on ESS third generation ES60X8 single chip DVD processor. The ES60X8 is built upon ESS proven Rev-A1
Programmable Multimedia Processor architecture with various speed enhancement and optimization. It supported all features we 1.Base on FYEMANN-A1B1,add PT2320,add MCU,add output.
developed from previous generation chip plus new features including DVD-Audio (with built-in CPPM logic), built-in TV-Encoder
(Macrovision compliance) and support Progressive Scan output. With the advance of ES60X8 integration, a complete DVD Rev-A2
design can now be implemented with minimum external components.
[email protected] 1.CHONGHONG DVA620, ADD RDS,AND SPDIF IN, AND
PHONES, CANCLE EQ A/D.
System Clock Requirement
ES60X8 require a 27MHz clock to operate. This 27MHz can either be generated externally and feed into pin 105 or thru a 27MHz
crystal attached to pin 49 and 50. This 27Mhz will be used for all video processing reference. In addition, internal multiplier will
generate a much higher operating frequency for the internal RISC+DSP code to operate. Audio clock is generated from ES60X8
by its internal PLL circuitry.
SDRAM Usage
ES60X8 support the use of higher density 4Mx16 SDRAM. This is the prefered choice for simplier design and lower memory cost.
The current DVD code requires only 2Mx16 memory size to operate. This provide an option to use cheaper half-bank 4Mx16
SDRAM. The design has put into consideration to support this type of half-bank SDRAM.
3 3
System Configuration
CHIP FUNCTION
ES60X8 Single chip processor that handles all system control and DVD
decoding. Built-in TV-Encoder direct drive a TV set.
32/64MBit SDRAM Data storage and frame buffer
4/8Mbit EPROM/FLASH Program storage
24C01 SERIAL EE System setup configuration storage
SST39VF080 FLASH
PCM1606 6-Channel AudioDAC
WM8739 2-Channel AudioADC
SERVO PART ATAPI INTERFACE
LCSx# FUNCTION
LCS0# SPARE
LCS1# SPDIF IN CONTROL
LCS2# SPDIF IN CONTROL
LCS3# ROM/FLASH
2 2
AUXx FUNCTION
AUX0 I2C DATA
AUX1 I2C CLOCK
AUX2 ESS COMMUNICATION PROTOCOL WITH MCU
AUX3 AUDIODAC ML
AUX4 INTERRUPT
AUX5 AUDIODAC MC
AUX6 ESS COMMUNICATION PROTOCOL WITH MCU
AUX7 ESS COMMUNICATION PROTOCOL WITH MCU
EAUXx FUNCTION
EAUX30 HSYNC
EAUX31 VSYNC
EAUX32 COMPACT FLASH DETECT SIGNAL
EAUX40 AUDIODAC MD
EAUX41 AUDIOADC CSB
1
OTHER FOR ATAPI INTERFACE 1
MCU part,please view 6/6 page.
ESS TECHNOLOGY, INC.
Title
INDEX
Size Document Number Rev
DVA620 A2
Date: Tuesday, February 19, 2002 Sheet 1 of 7
A B C D E
A B C D E
INSTALL REMOVE CLK SOURCE CHIP FREQ SOURCE R52 DCLKINPUT MULTI FREQ CRYSTALOSC VCCV VCC CVBS and CVBS and COLOR R,G,B MODE 8
R3 R10 DCLK INPUT ES6008 DCLKINPUT OR CRYSTALOSC INSTALL NA X4 108.0MHz 27MHZ FB1 S-VIDEO DIFFERENCE
R10 R3 CRSTAL OSC ES6018 DCLKINPUT OR CRYSTALOSC INSTALL NA X4 108.0MHz 27MHZ FERB VDAC CV CV C
ES6028 DCLKINPUT OR CRYSTALOSC INSTALL NA X4 108.0MHz 27MHZ YDAC Y Y G Y
Pull high ES60X8 pin 41 to use ES6038 DCLKINPUT AND CRYSTALOSC REMOVE 33.3MHz X3.5 116.7MHz 27MHZ CDAC C PB R PB
DCLK for clock source, no need INSTALL REMOVE MULTI UDAC PR B PR
VCC for XIN/XOUT crystal circuitry R11,R12 R4,R5 X4.5
R4,R12 R11,R5 X3
27/33M R11,R5 R4,R12 X3.5 VCC33 VCC33 VCC33 VCC33
R4,R5 R11,R12 X4
VIDEO OUT
R2
1 4 OPEN(33)
N V U1.105 VDAC
2 3 CVBS
G Q R3 R4 R5 R6 L1 2.4UH
N1 OPEN(27/33M) C1 OPEN(4.7K) 4.7K 4.7K 4.7K R7 YDAC
CDAC LUMA
OPEN 75 OHM C2 C3
UDAC CHROMA
(22PF) 470PF 470PF U
R9
VCC VCC
4 MCLK TBCK 4
N8
1 Pull high TDMDX TDM-CLK R10 R11 R12 33 OHM VCCV VCCV
GND TDM-CLK 4.7K OPEN OPEN C4 C5
2 to select 8-bit
RES R13 TDM-FS (4.7K) (4.7K)
3 ROM boot, pull OPEN OPEN
VDD 4.7K TDM-FS
low to select (15PF) (22PF)
809 16-bit ROM boot TDM-DATA TDM-DATA VCC33 Q1
VCC33E VCC33P VCC33 8050
VCC VCC FB2
EM-MARIN FERB 3 1
1
1
D2 D3
RESET IC TWS
1
R14 FB3 VCC27 L2 2.4UH
FERB TSD0
2
N2 D1 R8 OPEN R15 1N6263 1N6263
1 OPEN OPEN 75 OHM C7 C8
2
2
NC TSD1
2 (10K) 470PF 470PF
GND (1N4148)
3 TSD2
2
1
1
NC RST# N3 D4 D5
4
RES
111
104
130
148
157
159
164
183
193
201
121
139
172
ES60X8
31
25
28
30
29
51
18
27
59
68
75
92
99
35
44
83
5
VDD
1
9
C6
V6300 OPEN 1N6263 1N6263
TDMDX/RSEL
VC33
VC33
VC33
VC33
VC33
VC33
VC33
VC33
VC33
VC33
VC33
VC33
VC33
VC33
VC33
VC33
VC33
VC25
VC25
VC25
VC25
VC25
VC25
VC25
TDMTSC
TDMDR
AVCC(VDAC)
AVCC(PLL)
TDMFS
TDMCLK
Package: SOT-23 5L (47UF) 105 39
2
2
CLK MCLK
24 40 L3 2.4UH
RST# RESET TBCK
32 R18
TWS/SEL_PLL2 75 OHM C9 C10
173 33
LCS1# LCS0 TSD0/SEL_PLL0 VCCV VCCV
174 36 SPDIF1 470PF 470PF
LCS1# LCS2# LCS1 TSD1/SEL_PLL1
175 37 EAUX32
LCS2# LCS3# LCS2 TSD2
176 38 HSYNC
LA[0..19] LCS3# LCS3 TSD3
1
1
D6 D7
VSYNC
N4 WRLL# 198 47
LD0 LA0 WRLL# LWRLL RBCK
13 12 199 46
LD1 D0 A0 LA1 LWRHL RWS VCC33E 1N6263 1N6263
14 11 45
LD2 D1 A1 LA2 LOE# RSD
15 10 170
2
2
LD3 D2 A2 LA3 LOE# LOE SPDIF R19 33 OHM
17 9 41
LD4 D3 A3 LA4 LA0 SPDIF/SEL_PLL3 R20 33 OHM
18 8 204
D4 A4 LA0
1
1
LD5 19 7 LA5 LA1 205 116 R21 33 OHM L4 2.4UH D8 D9
LD6 D5 A5 LA6 LA[0..19] LA2 LA1 PCLK2XSCN/CAMYUV4