LG KE500.pdf part of LG KE500 LG KE500.pdf, LG Mobile Phone LG KE500 LG KE500.pdf text manual preview

........................... 151
4.14 Ear-Mic Hook Detection 12.3 Accessory ......................................... 166
Trouble Shooting................................. 94

-3-
1. General Description

1. General Description

The information in this manual is subject to change without notice and should not be construed as a
commitment by LGE Inc. Furthermore, LGE Inc.
reserves the right, without notice, to make changes to equipment design as advances in engineering
and manufacturing methods warrant.

This manual provides the information necessary to install, program, operate and maintain the
ME550c.

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2. Performance

2. Performance

2.1 Product Name
ME550c : GPRS Class 10 / EDGE Class 10

2.2 Supporting Standard
Item Feature Comment
Supporting Standard EGSM/DCS1800/PCS1900
with seamless handover
Phase 2+(include AMR)
SIM Toolkit : Class 1,2,3,E
Frequency Range EGSM TX : 880 - 915 MHz
EGSM RX : 925 - 960 MHz
DCS1800 TX : 1710 - 1785 MHz
DCS1800 RX : 1805 - 1880 MHz
PCS1900 TX : 1850 - 1910 MHz
PCS1900 RX : 1930 - 1990 MHz
Application Standard WAP 2.0, JAVA 2.0

2.3 Main Parts : GSM Solution

Item Part Name Comment

Digital Baseband Neptune (D761811BZVL): TI

Analog Baseband Triton (TWL3029): TI

RF Chip B6PLD: RENESAS

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2. Performance

2.4 HW Feature

Item Feature Comment
Form Factor Slide
1) Capacity
Battery Standard : Li-Polymer, 800mAh
2) Packing Type : Hard Pack
Standard :
Size
97.0 X 47.0 X 14.9 mm
Weight 90g With Battery
Volume 75cc
PCB Staggered 10Layers , 0.8t
Stand by time 250 hrs @ Paging Period 5
Charging time 3 hrs @ Power Off / 800mAh
Talk time Min : 3.0 hrs @ Power Level 7 @ EGSM / 800mAh
EGSM : -105 dBm
RX sensitivity DCS 1800 : -105 dBm
PCS 1900 : -105 dBm
GSM/ EGSM : 33 dBm Class4 (EGSM)
GPRS DCS 1800 : 30 dBm Class1 (PCS)
PCS 1900 : 30 dBm Class1 (DCS)
TX output power
EGSM : 27 dBm E2 (EGSM)
EDGE DCS 1800 : 26 dBm E2 (PCS)
PCS 1900 : 26 dBm E2 (DCS)
GPRS compatibility GPRS Class 10
EDGE compatibility EDGE Class 10
Plug-In SIM
SIM card type
3V /1.8V
Main LCD
Display 262K Color TFT (176 x 220)
Backlight : White LED
Built-in Camera 2M CMOS Camera One button access

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2. Performance

Item Feature Comment

Status Indicator None

Alphanumeric Key : 12 Function Key:
Function Key : 9 4 Key Navigation, OK, F1,
Side Key : 4 F2, CLR, SND
Keypad Total No of Keys :25 Side Key :
Volume up/down, CAM,
PWR/END

Main : Internal Fixed Type
ANT
Blue tooth : Internal Fixed Type

System connector 18 Pin

Ear Phone Jack 18pin, 4 Pole, Stereo

PC synchronization Yes

NAND Flash : 1Gbit
Memory
SDRAM : 512Mbit

Speech coding FR, EFR, HR,AMR

Data & Fax Built in Data & Fax support

Vibrator Built in Vibrator

V2.0, HSP, HFP, OPP, FTP(server),
Blue Tooth
BPP, A2DP, AVRCP

MIDI (for Buzzer Function) SW Decoded 64Poly

Music Player MP3/ AAC/AAC+ With Graphic EQ

Camcorder MPEG4, H.263, H.264

Voice Recording Yes

Speaker Phone mode
Yes
Support

Travel Adapter Yes

CDROM Yes

Stereo Headset Yes Optional

Data Cable Yes Optional

T-Flash (External Memory) Yes Optional

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2. Performance

Item Feature Comment

RSSI 0 ~ 5 Levels

Battery Charging 0 ~ 4 Levels

Key Volume 0 ~ 5 Level

Audio Volume 1 ~ 5 Level

Time / Date Display Yes NITZ

Multi-Language Yes English / French

Phone Book / Message / Camera
Quick Access Mode
/ My Stuff / Favorite

PC Sync Schedule / Phonebook / MEMO /
SMS / Download(Photo, file)

Speed Dial Yes (2~9) Voice mail center -> 1 key

Profile Yes

CLIP / CLIR Yes (different melody)

Phone Book 4 Numbers + 1 Memo + 1 e-mail + Total 1000 Member
Group Select + Picture

Last Dial Number Yes (40)

Last Received Number Yes (40)

Last Missed Number Yes (40)

Search by Number/Name Name only

Group 7 Possible Rename

Fixed Dial Number Yes

Service Dial Number Yes

Own Number Yes

Voice Memo Yes

Call Reminder Yes

Network Selection Automatic

Mute Yes

Call Divert Yes

Call Barring Yes

Call Charge (AoC) No No for Cingular

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2. Performance

Item Feature Comment

Call Duration Yes

SMS (EMS) 100 (10) EMS : Release4
(Except Text align)

SMS Over GPRS Yes

EMS Melody / Picture Yes
Send / Receive / Save

MMS MPEG4 / Send / Yes
Receive / Save

Long Message MAX 925 Characters

Cell Broadcast Yes

Download Over the WAP

Game YES

Calendar Yes

Memo 50

Unit Convert Currency/Area/Length/Volume/Weigh
t/Temperature/Velocity

Tip Calculator No

Wall Paper Yes Default 5ea

WAP Browser Over WAP 2.0 Up Brower Obigo Q-line

Download Melody / Yes Over WAP
Wallpaper

SIM Lock Yes Operator Dependent

SIM Toolkit Class 1, 2, 3, A-E

MMS Yes Openwave MMS Client

EONS Yes

CPHS Yes V4.2

ENS Yes

Camera Yes 2M F/F / Digital Zoom : x4

JAVA Yes CLDC V1.1 / MIDP V2.0
Download Over WAP

Voice Dial No

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2. Performance

Item Feature Comment

IrDa No

V2.0
HSP, HFP, OPP,
Blue tooth Yes
FTP(server),
BPP, A2DP, AVRCP

GPRS Yes Class 10

EDGE Yes Class 10

Hold / Retrieve No

Conference Call Yes Max. 6

DTMF Yes

Memo pad Yes

TTY No

AMR Yes

Sync ML No

IM No

Email No

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2. Performance

2.6 Technical Specification
Item Description Specification

GSM850
TX: 824 + n x 0.2 MHz (n=1 ~ 124)
RX: TX + 45 MHz
GSM900
TX: 890 + n x 0.2 MHz (n=1 ~ 124)
890 + (n-1024) x 0.2 MHz (n=975 ~ 1023)
RX: TX + 45 MHz
1 Frequency Band
DCS1800
TX: 1710 + ( n-511 ) x 0.2 MHz (n = 512 ~ 885)
RX: TX + 95 MHz
PCS1900
TX: 1850 + ( n-511 ) x 0.2 MHz
RX: 1930 + ( n-511 ) x 0.2 MHz (n = 512 ~ 810)
RMS < 5 degrees
2 Phase Error Peak < 20 degrees
3 Frequency Error < 0.1ppm
GSM850/GSM900
Level Power Toler. Level Power Toler.
5 33 dBm 2dB 13 17 dBm 3dB
6 31 dBm 3dB 14 15 dBm 3dB
7 29 dBm 3dB 15 13 dBm 3dB
8 27 dBm 3dB 16 11 dBm 5dB
9 25 dBm 3dB 17 9 dBm 5dB
10 23 dBm 3dB 18 7 dBm 5dB
11 21 dBm 3dB 19 5 dBm 5dB
4 Power Level 12 19 dBm 3dB
DCS1800/PCS1900
Level Power Toler. Level Power Toler.
0 30 dBm 2dB 8 14 dBm 3dB
1 28 dBm 3dB 9 12 dBm 4dB
2 26 dBm 3dB 10 10 dBm 4dB
3 24 dBm 3dB 11 8 dBm 4dB
4 22 dBm 3dB 12 6 dBm 4dB
5 20 dBm 3dB 13 4 dBm 4dB
6 18 dBm 3dB 14 2 dBm 5dB
7 16 dBm 3dB 15 0 dBm 5dB

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2. Performance

Item Description Specification

GSM900
Offset from Carrier (kHz). Max. dBc
100 0.5
200 -30
250 -33
400 -60
600~ <1,200 -60
1,200~ <1,800 -60
1,800~ <3,000 -63
3,000~ <6,000 -65
Output RF Spectrum 6,000 -71
5
(due to modulation) DCS1800/PCS1900
Offset from Carrier (kHz). Max. dBc
100 0.5
200 -30
250 -33
400 -60
600~ <1,200 -60
1,200~ <1,800 -60
1,800~ <3,000 -65
3,000~ <6,000 -65
6,000 -73
GSM900
Offset from Carrier (kHz) Max. (dBm)
Output RF Spectrum 400 -19
6
(due to switching transient) 600 -21
1,200 -21
1,800 -24

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2. Performance

Item Description Specification
DCS1800/PCS1900
Offset from Carrier (kHz). Max. (dBm)
Output RF Spectrum 400 -22
6
(due to switching transient) 600 -24
1,200 -24
1,800 -27
7 Spurious Emissions Conduction, Emission Status
8 Bit Error Ratio BER (Class II) < 2.439% @-102dBm
9 Rx Level Report accuracy 3 dB
10 SLR 8 3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 -12 -
200 0 -
300 0 -12
11 Sending Response 1,000 0 -6
2,000 4 -6
3,000 4 -6
3,400 4 -9
4,000 0 -
12 RLR 2 3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 -12 -
200 0 -
300 2 -7
500 * -5
13 Receiving Response 1,000 0 -5
3,000 2 -5
3,400 2 -10
4,000 2
* Mean that Adopt a straight line in between 300 Hz and
1,000 Hz to be Max. level in the range.

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2. Performance

Item Description Specification

14 STMR 13 5 dB
15 Stability Margin > 6 dB
dB to ARL (dB) Level Ratio (dB)
-35 17.5
-30 22.5
-20 30.7
16 Distortion
-10 33.3
0 33.7
7 31.7
10 25.5
17 Side Tone Distortion Three stage distortion < 10%
System frequency
18 2.5ppm
(13 MHz) tolerance
19 32.768KHz tolerance 30ppm
Full power
- 340mA(GSM900), < 260mA(DCS/PCS)
20 Power consumption Standby
- Normal mode ? 4.0mA(Max.power)
- Using Test mode on DSP Sleep function ? 6mA
GSM900/Lvl 7 (Battery Capacity 800mA) : 180 min
20 Talk Time
GSM900/Lvl 12 (Battery Capacity 800mA) : 300 min
PCS1900/Level5 (Battery 800mA) : 310 Min
PCS1900/Level10(Battery 800mA) : 390 Min
Under conditions, at least 200 hours:
1. Brand new and full 800mAh battery
2. Full charge, no receive/send and keep GSM in idle mode.
21 Standby Time
3. Broadcast set off.
4. Signal strength display set at 3 level above.
5. Backlight of phone set off.
At least 70 dB under below conditions:
22 Ringer Volume 1. Ringer set as ringer.
2. Test distance set as 50 cm
Fast Charge : < 550 mA
23 Charge Voltage
Slow Charge: < 60 mA

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2. Performance

Item Description Specification
Antenna Bar Number Power
5 -85 dBm ~
4 -90 dBm ~ -86 dBm
24 Antenna Display 3 -95 dBm ~ -91 dBm
2 -100 dBm ~ -96 dBm
1 -105 dBm ~ -101 dBm
0 ~ -105 dBm
Barttey Bar Voltage
0(included Blinking) 3.65V~3.35V
1 3.71V ~ 3.66V
25 Battery Indicator
2 3.78V ~ 3.72V
3 3.91V ~ 3.79V
4 4.20V ~ 3.92V
3.60V 0.03V (Standby)
26 Low Voltage Warning
3.50V 0.03V (Call)
27 Forced shut down Voltage 3.35 0.03 V
1 Li-polymer Battery, Hardpack
Standard Voltage = 3.7 V
28 Battery Type
Battery full charge voltage = 4.2 V
Capacity: 800mAh
Switching-mode charger
27 Travel Charger Input: 100 ~ 240 V, 50/60Hz
Out put: 4.8V, 900mA

- 16 -
3. Circuit Description

3. Circuit Description

3.1 General Description
The RF part consists of a transmitter, a receiver, a synthesizer, a voltage supply and a DCXO part.
The main RF Chipset B6PLD is a highly integrated RF tranceiver IC FOR Digital Interface of GSM 850,
GSM900, DCS1800 and PCS1900 quad-band cellualr systems. The B6PLD incorporates EDGE
tranceiver apability, quad R low-noise amplifiers(LNSa). Direct conversion mixers, a programmable
gain amplifier(PGA) with DC offset and frequency response correction, ADC, Digital filiter, Digital
Interface, fully integrated VCOs, an RF fractiona-N synthesiser, a low-noise offset PLL transmitter,
Digital modulator, TXDAC, RAMPDAC, and AFCDAC. The B6PLD includes state machine control
through serial programming. All functions operate down to 2.67V and are housed in a 72-pin BGA
package. Hence the B6PLD can form a small size transceiver handset for quad band EDGE
tranceiver.

3.2 RF Part
3.2.1 Receiver Part
The B6PLD receiver supports quad band, so the front-end incorporates four LNAs and two mixers.
The incoming RF signals are mixed directly down to I/Q baseband by the front-end bolck. This
incorporates four LNAs/four buffers and two Gillbert Cell mixer blocks optimised for operation at
850MHz, 900MHz, 1800MHz and 1900MHz respectively. The front-end block is followed by two
closely matched baseband amplifier chains. These include distributed low pass filtering, one switched
gain stage and one fixed gain stage. In addition, the baseband section integrates A/D and D/A
converters which provide automatic on-chip correction of DC offsets.

Receiver Part Block Diagram

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3. Circuit Description

3.2.1.1 Baseband PGA/Low pass Filter Specifications
The baseband programmable amplifier comprises one stage with variable gain followed by a fixed
gain amplifier. The overall gain control range is 36dB with 6dB Steps. The filtering is provided by a
single R/C low pass filter with an on-chip capacitor followed by on-chip Chebychev low pass filters.
The filters have been specified to achieve maximal group delay flatness in the pass-band combined
with the required levels of suppression of interfering signals. The distribution of the gain and filtering
has been designed to ensure that the receiver does not compress under blocking conditions. The
final fixed gain amplifier is included to match the on-chip levels to the input dynamic range of the
ADC.

3.2.1.2 DC offset auto-calibration system
B6PLD implements a system for cancelling the DC offsets in the baseband programmable gain
amplifiers(PGA). This prevents a small DC offset at the input giving a large DC offset at the output,
even at high gain settings. When the B6PLD receiver is performing an auto-calibration, the
sequencer cancels the offsets locally around the PGA, then the Digital filter. The system includes
switches to short out the signal path whilst the cancellation is occurring. The switches are opened in
sequence as the calibration progresses. For PGA the A/D converter system employs a successive
approximation technique and achieves 6 bit resolution. The PGA stage has an associated 6 bit
current DAC which cancels the DC offset at the output. The sequencer ensures that on-chip filters
have sufficient time to settle before applying correction in the next digital offset cancellation stage.

- 18 -
3. Circuit Description

3.2.2 Transmitter part
The B6PLD transmitter is capable of both GMSK and 8-PSK modulation, to support for conventional
GSM and EDGE. B6PLD integrates all loop filters to configure both PM loop and AM loop. See block
diagram below.

Fig. Simplified Block diagram for Tx part

3.2.2.1 Polar Loop Structure
Three main functions are identified in the transmitter architecture; I/Q vector modulation at IF
frequency, amplitude and phase loop at IF/RF frequencies and power amplification.

- 19 -
3. Circuit Description

3.2.3 RF Systhesiser

3.2.4 Front End Module Specification

3.2.4.1 Block Diagram and Internal Matching Condition

HWXR693

- 20 -
3. Circuit Description

3.2.4.2 Logic Table for Selction

Select Mode Vc(GSM850/EGSM) Vc(DCS/PCS)
GSM850_Rx Low Low
EGSM_Rx Low Low
GSM850/EGSM_Tx High Low
DCS_Rx Low Low
PCS_Rx Low Low
DCS/PCS_Tx Low High

Band SW Logic Table

3.2.5 Power Amplifier Module
for Quad-band GSM/GPRS/EDGE

3.2.5.1 PAM Specification
-. Quad band GSM, GPRS & Ploar Loop EDGE Amplifier
-. For 3.5V nominal operation
-. Bulit-in LDO circuit
-. GPRS Class 12 operation compatible
-. Integrated directional coupler

3.2.5.2 Circuit Diagram and peripheral components

RPF09036B

- 21 -
3. Circuit Description

3.2.6 Digital Core

3.2.6.1 Digital Interface Block Diagram

Fig. 1-1 Digital Interface Block Digram

- 22 -
3. Circuit Description

3.2.6.2 Control system and digital interface

The B6PLD is a RF transceiver IC for GSM850, GSM900, DCS1800 and PCS1900 quad band
cellular system, and incorporates EDGE transceiver capability. The B6PLD has a digital interface
connection to the baseband processor. This interface complies with the digital interface specification
DigRF standard v112.
The digital interface consists of two separate interface connections; (1) the control interface, (2) the
data interface, and a system clock on/off control signal and a precise timing singal. These are
realized by eight signal lines in B6PLD(Look at Fig1.1 above)

- The control interfce is used to configure the B6PLD for RX and TX operation, transfers of control
data for several built-in circuits, and for triggering the events. The control interface comprise a bi-
directional 3-wire serial interface with the three signal lines CtrlData, CtrlEn and CtrlClk accessing
the control registers in B6PLD by transferring the control words.

- The data interface is used to transfer transmit modulation symbols and receive IQ-sampling data.
The data interface comprises a single serial bus with the three signal lines RxTxData, RxTxEn and
SysClk. The SysClk is used for system clock to baseband.

- The SsClkEn signal enables the SysClk output and powers the 26MHz oscillator on. When the
SysClkEn is negated, the SysClk is held low, and if the TEST1 pin is low by the default settings, the
logic power supply by typical 1.8 volts to the internal core logic circuits is also switched off.

- 23 -
3. Circuit Description

3.3 Digital Baseband

OMAPV1030 Block Diagram

3.3.1 General description
The OMAPV1030 E-GPRS multimedia device belongs to the Texas Instruments OMAP-Vox_
processors family. It combines both a modem engine and an application engine. Memory and CPU
resources are shared between modem and application processing.
The OMAPV1030 chip is based on the OMAP3.4 architecture and integrates two processor
subsystems:
- An MPU subsystem based on an ARM926EJ-S
- A DSP subsystem based on a UMA 2.6 architecture integrating a C55x DSP core The
OMAPV1030's silicon process technology is a c027.0 90-nm digital CMOS.

- 24 -
3. Circuit Description

3.3.2 Block Description
The OMAPV1030 E-GPRS multimedia device is based on an OMAP3.4 platform that integrates:
- The MPU subsystem
- The DSP subsystem
- A system DMA
- A traffic controller providing:
- External memory interfaces with:
- A slow interface (EMIFS) to ROM, SRAM, FLASH memories
- A fast interface (EMIFF) to SDRAM memories
- Layer 3 (L3) interconnect made of two OCP target ports (OCP-T1 and OCP-T2) and one OCP
initiator port (OCP-I)
- Layer 4 (L4) interconnect made of two DSP peripheral busses (private DSP TIPB and shared DSP
TIPB) and two MPU peripheral busses (public MPU TIPB and private MPU TIPB)
- Clock management
- A set of processor peripherals:
- Three 32-bit timers, a 16-bit Watchdog timer, and an interrupt handler for the MPU
- Three 32-bit timers, a 16-bit Watchdog timer, and a 2nd-level interrupt handler for the DSP
- Test and debug interfaces (JTAG, Window Tracer)
- Trace capabilities: ETM9 and Ctools
The other OMAPV1030 modules or subsystems are connected to the OMAP3.4 platform through the
L3 and L4 interconnects.

OMAPV1030 Top-Level Architecture Overview

- 25 -
3. Circuit Description

The OMAP3.4 platform is the computing core of the device. The other OMAPV1030 components are
organized as follows:
- The internal memory subsystem is made of a single-port 256K-bit shared internal SRAM.
- The security subsystem is a set of several components, including dedicated a secure mode to run
secure applications.
- A master-slave USB module provides an external interface supporting high data transfer rates
between the OMAPV1030 and external application
- The memory interfaces provide access to external memories. There are two types of memory
controllers:
- SDRAM controller supporting SDR and DDR modes
- General-purpose controller supporting asynchronous and synchronous
- The system components are used to manage system interactions such as interrupts, clock control,
reset control, and idle management.
- The peripheral subsystem refers to all the peripherals accessible by the MPU and/or the DSP. They
are all OCP- or TIPB-compliant and are connected to the OMAP3.4 platform through the traffic
controller or the TIPB busses.

3.3.3 RF Interface (Digital RF Interface)
The OMAPV1030 radio interface module of OMAPV1030 device is an interface that carries the
following information:
- Transmit symbols from DBB to RF IC
- Receive samples from RF IC to DBB
- Bidirectional information control
- Real-time and activation signals from DBB to RF IC
- System clock
The OMAPV1030 radio interface module of OMAPV1030 device supports two types of radio
interfaces.
They differ mainly in the type of data interface:
- The first interface is based on a standard six-wire scheme: three wires for transmit and three for
receive.
- The second one is based on a two-wire bidirectional scheme: one wire for data in/out, and one for
control receive/transmit.

- 26 -
3. Circuit Description

OMAPV1030 Radio Interface

This implementation is based on the following:
- The time processing unit (TPU) module is a real-time sequencer dedicated to monitoring GSM
baseband processing.
- The serial port of the time serial port (TSP) module controls both interfaces.
- The real-time TSPACT signal of the TSP module
- The McBSP digital RF module is used for the six-wire data interface.
- The serial radio interface module is used for the two-wire data interface.
- A system clock interface receives a squared 26-MHz clock from the RF IC.

- 27 -
3. Circuit Description

3.3.4 SIM interface
SIM interface scheme is shown in below.
SIM_IO, SIM_CLK, SIM_RST, SIM_PWRCTRL ports are used to communicate DBB via ABB with
plugged sim card and the LDO (VRSIM) in ABB enables operate 1.8V to 2.5V to search SIM card

SIM Interface

SIM_CLK : SIM Card reference clock SIM_PWCTRL : SIM Card power activation
SIM_RST : SIM Card async/sync reset SIM_IO : SIM Card bi-directional data line
VRUSIM(Power supply VCC) : 3 V 10% (class B) or 1.8 V 10% (class C)
Misc_ext_irq : USIM card presence detection (USIM_CD) purposes.

- 28 -
3. Circuit Description

3.3.5 UART Interface
ME550c has Three UART Drivers as follow :
- UART1 : USB - UART2 : ETM, Calibration - UART3 : AT command, Fax_modem, Bluetooth

UART1(USB)

Resource Name Description

USB_DP DP Data

USB_DM DM Data

USB_PWR POWER USB_POWER

VBUS VBUS USB_Detect
UART2 (ETM)
DEBUG_RX RX Receive Data(UART2)

DEBUG_TX TX Transmit Data(UART2)
UART3 (Bluetooth)
UART3_RXD UART3_RXD Receive Data

UART3_TXD UART3_TXD Transmit Data

UART3_RTS UART3_RTS Request To Send

UART3_CTS UART3_CTS Clear To Send

UART Interface Spec

- 29 -
3. Circuit Description

3.3.6 GPIO Map
In total 22 allowable resources, ME550c is using 9 resources except 3 resources dedicated to SIM
and Memory. ME550c GPIO(General Purpose Input/Output) Map, describing application, I/O state,
and enable level, is shown in below table 3.

Resource Inactive Active
I/O # Net Name I/O
State State State
I/O (1) Not used
I/O (2) I Sysboot HIGH LOW
I/O (4) USB_BOOT_SEL I Sysboot LOW (Giant Plus) HIGH (Nanya)
I/O (6) I Sysboot HIGH LOW
I/O (7) DIF_VSCNC I GPIO LOW HIGH
I/O (8) BT_NRST O GPIO LOW (LCD B/L Of f ) HIGH (LCD B/L On)
I/O (9) CHG_EN O GPIO LOW HIGH
I/O (10) VCAM28_EN O GPIO LOW HIGH
I/O (12) CAM_RST O GPIO HIGH LOW
I/O (13) FM_INT I GPIO HIGH LOW
I/O (16) MAIN_KEY_BL_EN I Sysboot LOW HIGH
I/O (17) BOOT_SEL I GPIO HIGH HIGH
I/O (18) DP_PWON O GPIO LOW HIGH
I/O(27) SLIDE I GPIO LOW HIGH
I/O(32) SPK_EN O GPIO HIGH LOW
I/O (33) Not used O GPIO LOW HIGH
I/O (42) VCAM18_EN I GPIO LOW HIGH
I/O(43) CHG_STAT O GPIO HIGH LOW
I/O (46) CIF_PD I GPIO LOW HIGH
I/O (47) JACK_DETECT O GPIO HIGH LOW
I/O (55) HOOK_DETECT O GPIO HIGH LOW
I/O (63) SPK_EN O GPIO LOW HIGH

GPIO Map

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3. Circuit Description

3.3.7 Camera interface
ME550c have a 8-bit parallel camera interface(NOBT Mode) .
This is a general parallel interface with vertical and horizontal synchronization signals.(See. Figure
12) The maximum clock is 96 MHz for 8-bit data data, or 48 MHz for 10- or 12-bit data.

Generic Parallel Camera Interface

Table7. describes the I/O signals of the generic parallel camera interface.
Figure13, Figure14 show the frame and data timing according to synchronization signals in the
parallel NOBT configuration.

Generic Parallel Camera Interface

- 31 -
3. Circuit Description

3.4 Analog Baseband

3.4.1 General Description
The TRITON chip is the analog and power management part of the Texas Instruments next
generation wireless terminal. These GSM/GPRS/E-GPRS, 3G W-CDMA, CDMA2000 platforms are
composed of a digital baseband processor, a RF chip, an application processor OMAP and of
different peripheral devices like a LCD panel, a Multi-Media Card, a Bluetooth modem, a GPS
modem.
The purpose of the Triton device is to provide to platforms the following resources:
- A power management system - Three White-LEDs drivers
- Power supply resources - A vibrator driver
- A voice and audio interface - A SIM-Card detection
- A battery charger - A thermal shutdown
- A monitoring system - An I2C interface
- A real time clock resource - A JTAG and boundary scan
- A USB 2.0 OTG transceiver with a carkit
interface

TWL3029 Architecture

- 32 -
3. Circuit Description

3.4.2 Audio Signal Processing & Interface
The Audio module consists of a Voice Codec dedicated to mobile telephone terminal application and
a Stereo path.
- The Voice Codec circuit processes analog audio components in the uplink path and transmits the
converted data to the DSP speech coder through the voice serial port (VSP). In the downlink path,
the Voice Codec converts the digital samples of speech data received from the DSP via the VSP
port into analog audio signals.
The Voice Codec supports a 8kHz (default narrowband mode) to a 16kHz(wideband mode) sampling
frequency.
- The Stereo path converts audio digital samples received from the I2S serial interface into analog
audio. It supports all standard frequencies from 8kHz to 48kHz (8, 11.025, 12, 22.05, 24, 32, 44.1
and 48kHz).
- Two included PLLs provide the suitable system clocks to the Voice and Stereo circuitry (ADC,
DACS, Digital Filters, Digital interfaces). The Audio module supports 3 possible input master clocks
: 12MHz, 13MHz and 19.2MHz.

3.4.3 Power Resources
The power supply module of Triton generates the different power supplies required by Triton, the
processors and the external peripherals.

- 33 -
3. Circuit Description

Power Supply Scheme

- 34 -
3. Circuit Description

3.4.4 Monitoring ADC
The monitoring ADC (MADC) consists of a 10-bit analog-to-digital converter (ADC) combined with an
11- input analog multiplexer. The ADC implementation consists of a successive approximation
conversion.
Five of the eleven inputs are available externally (ADIN1..5), and the remaining six inputs are
dedicated to die temperature measurement, main battery voltage, backup battery voltage, charger
voltage, charger current monitoring and USB Vbus voltage. Three external inputs (ADIN1..3) are
standard inputs. The two others (ADIN4..5) which are associated with current sources, are intended
for battery temperature and battery type measurements.

ADC 8 channels

Resource Name Description

VCHG VCHG
Charging Management
VBAT VBAT

ICTL ICTL

ADIN1 TEMP_SENSE Temperature Sensing

ADIN2 JACK_TYPE Remote control's Detect- Now No Use

ADIN3

ADIN4 REMOTE_ADC Remote control's function

(play, stop,etc..)- Now No Use

ADIN5 BATT_TEMPS Battery Detect

ADC Channel Spec

3.4.5 Switch ON/OFF
ME550c Power State : Defined 4cases as follow
- Power-ON : mobile is powered by main battery or backup battery.
- Power-OFF : mobile isn't any battery.
- Switch-ON : mobile is powered and waken up from switch-off state.
- Switch-OFF : mobile is powered to maintain only the permanent function(ULPD).
To enter into Switch-ON state, one of following 4 condition is satisfied.
- PWR-ON pushed after a debouncing time of 30ms.
- ON_REMOTE : After debouncing, when a falling edgeis detected on RPWON pin.
- IT_WAKE_UP : When a rising edge is detected on RTC_ALARM pin.
- CHARGER_IC :When a charger voltage is above VBAT+0.4V on VCHG.

- 35 -
3. Circuit Description

3.4.6 Memories
- 512Mbit NAND Flash + 512Mbit DDR RAM

3.4.7 LCD Module
The NM200CND module is a Color Active Matrix Liquid Crystal Display with an Light Emission Diode
(LED) Back Light system. The matrix employs a-Si Thin Film Transistor as a active element.
It is a transmissive type display operating in the normally white mode. This TFT-LCD has a 2.0 inch
diagonally measured active display area with QCIF+ resolution(176 x RGB x 220 pixels).
Each pixel is divided into Red, Green, Blue sub-pixels or dots which are arranged in vertical stripes.
Gray scale or the brightness of the dots color is determined with a 6 bit gray scale signal for each dot,
thus, presenting a palette of more than 262,144 colors.

3.4.7.1 General Description

Properties Spec. of Main LCD Unit

Active screen size 31.68(H)*39.6(V) mm

Viewing area size 33.08(H)*41.0(V) mm

Color depth 262,000 colors -

Resolution 176 x RGB x 220 -

Pixel format RGB Vertical Stripe -

Dot pitch 0.06(H)*0.18(V) mm

Display operating mode Transmissive type -

User viewing angle 6 O' clock

- 36 -
3. Circuit Description

3.4.7.2 LCD module pin map description

- 37 -
3. Circuit Description

3.4.8 Keypad Map description

1 4 7 AST
200 201 202 AST KEYPAD
R200
KBR(0)
150
2 5 8 0
203 204 205 206
VA200
EVLC5S02100
R201
KBR(1)
150
3 6 9 SHP
207 208 209 SHP
VA201
EVLC5S02100
R202
KBR(2)
150

VA202
EVLC5S02100

R203 150
KBC(0)
R204 150
KBC(1)
R205 150
KBC(2)
R206 150
KBC(3)
VA203

VA204

VA205

VA206

SIDE_KEY_VOL
CN202
1 R207 150
EVLC5S02100EVLC5S02100 KBC(1)
2 R208 150
EVLC5S02100EVLC5S02100 KBC(0)
3
4
VA208

VA207 EVLC5S02100
R209 150
KBR(3)
SIDE_KEY_CAM+PWON
CN203
1
2 R211 150
KBC(2)
3
4 R210 150
PWON
VA209

VA210 VA211
EVLC5S02100

KEYPAD
S_UP S_DOWN S_OK S_LEFT S_RIGHT

R122
KBR(4)
150

S_MENU100 S_MENU101 SEND CLR

VA100
EVLC5S02100
R123
KBR(5)
150

VA101
EVLC5S02100

R124 150
KBC(0)
R125 150
KBC(1)
R127 150
KBC(2)
R128 150
KBC(3)
R129 150
KBC(4)
VA102

VA103

VA104

VA105

VA106

EVLC5S02100 EVLC5S02100
EVLC5S02100 EVLC5S02100 EVLC5S02100

Keypad schematic

KBC0 KBC1 KBC2 KBC3 KBC4
KBR0 1 4 7 *
KBR1 2 5 8 0
KBR2 3 6 9 3
KBR3 VOL_UP VOL_DOWN CAMERA #
KBR4 HOT_UP HOT_DOWN O.K HOT_LEFT HOT_RIGHT
KBR5 SOFT_LEFT SOFT_RIGHT SEND CLR

- 38 -
3. Circuit Description

3.4.9 Bottom System Connector

Pin # ME550c Description

18Pin

1 FM_ANT FM_RADIO ANTENNA

2 HSMICIP/HOOK DETECT HEAD SET

3 JACK_TYPE HAED SET

4 HSO_L CHARGING (VCHG)

5 HSO_R CHARGING (VCHG)

6 UART3_TX/USB_DP USB/UART3 (Transmit Data)

7 UART3_RX/USB_DM USB/UART3 (Receive Data)

8 JACK_DETECT HEAD SET

9 VBAT BAT T ERY(+4.2V)

10 VBAT BATTERY(+4.2V)

11 RPWON REMOT E POWER ON

12 VCHG_IN CHARGING (VCHG)

13 VGHG_IN CHARGING (VCHG)

14 UART3_DSR UART3 (Transmit Data)

15 VBUS USB POWER( +5.0 V)

16 UART2_TX TEST : UART2 (Transmit Data)

17 UART2_RX TEST : UART2 (Receive Data)

18 GND GND

- 39 -
3. Circuit Description

3.5 Bluetooth Interface

3.5.1 Bluetooth Circuit

BT_NRST
BLUETOOTH (Shielding Block)
VRIO
VBAT

KA_OUT

VLDO_OUT
10K R102

C103
C105
1u VLDO_OUT C106
0.1u
4.7u

C108
CLK_32K
47p
G7

G6
G5
D6
H6
D8

H8

H3
C2
A3

B3

E3
F1

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