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VBAT VPWR VCCD VRF VUHF VTIC VBAT VCCD
TAPRESNT
SIM and Power
Management ALAM
(5) PWRON0
SRLDATA
SRLCLK
BOOSTEN
SIMEN
SIMDATA
SIMCLK
SIMRST
POR
VBAT VUHF VRF VTIC VCCD VBAT VPWR VCCD
PCONT
RESETB
F RT
PACOUT2
HDSTDET
TXEN1
RXEN1 BPDET
VC4 GSM Processor
VC1 (4)
CTLRT
CTLCLK
SYNDAT CTLDATA
SYNLE RPNSDAT
SYNCLK
Radio SYNEN
Interface TXEN0 Baseband SYSCLK
Block Audio Interface
(2) (3) RXCLK
SYNREF RXDAT
RXRT
CDCCLK
CDCRT
TXIP ENCDATA
TXIN DECDATA
TXQP
TXQN
AVCONT
RXIP SDIN
RXIN SYNC
RXQP SCLK
RXQN IRQ
Title
MX-5010 System Block Diagram
System HW Rev. Drawn by Chk'd by Approved by
MX-5010 2.50 K.Tsuchida S.Ohmomo K.Sakayori
FCC ID Date Page Maxon Telecom Co., Ltd.
AWWMX5010 2002/05/08 1 of 5
PROPRIETARY INFORMATION
Any part of this document must not be disclosed to third parties without prior written permission.
VRF
VRF
Q101 F_tx_if VCCD
CONT2
LPF TXIFP FILTP
VC1 TXIFN
TXCPO FILTN
VC4
IC101 V-BAT TXVCO Tx Path
T/R SW IC201 PA CX77304 TUNE
CP LPF TXIP
F_tx TXDCS/PCS
TXIN
APC /
PSN LPF
Band D2
Sel. PFD TXQP
MP101 F_tx TXGSM TXQN
ANTENNA D1
F201
Coupler IC203 TXINP
VTIC PAC AMP
P101 X2
RF
Connector D201 - VUHF
RF Detector + -
+ SYNDAT
Sx (Synthesizer) Rx/Tx Control
K SYNLE
X2 Aux Control SYNCLK
PACOUT2 F_lo SYNEN
PACOUT2 Control
1/3 IP2 Calibration TXEN1
Registers
TXEN0 DC Offset Timing RXEN1
Fractional-N
LPF Sx Register 1/2
PLL
F_rx
PCO2 SYNREF
F101 Band Aux Control
PCO1 Select
GSM Rx SAW
Rx Path
X2
F102
DCS Rx SAW
[ARFCN Allocation]
EGSM: 975-1023, 0-124 RXIP
PSN LPF LPF LPF RXIN
DCS: 512-885
PCS: 512-810 F103
PCS Rx SAW DC offset DC offset DC offset
[Frequency Calculation] Canceller Canceller Canceller
F_Tx = K/3 * (2-D2/D1) * F_lo
F_Rx = 2 / 3 * F_lo
(EGSM band)
F_Rx = 4 / 3 * F_lo
(DCS/PCS band)
RXQP
PSN LPF LPF
LPF LPF RXQN
Table A. T/R Switch Control
DC offset DC offset DC offset
Symbol EGSM DCS PCS Canceller Canceller Canceller
Tx Rx Tx Rx Tx Rx
VC1Mo L L H L H L IC301 DCR CX74017
CONT2 L L L L L H
VC4 H L L L L L
Table B. Frequency Plan
Mode Symbol Frequency Plan [MHz]
EGSM DCS PCS Title
Transmit F_Tx 880.2 - 914.8 1710.2 - 1784.8 1850.2 - 1909.8 Radio Interface Block Diagram
System HW Rev. Drawn by Chk'd by Approved by
F_lo 1473.0 - 1543.7 1344.0 - 1414.5 1449.7 - 1516.6
MX-5010 2.50 K.Tsuchida S.Ohmomo K.Sakayori
F_tx_if 90.5 - 114.4 74.8 - 104.8 80.5 - 112.3
FCC ID Date Page Maxon Telecom Co., Ltd.
Receive F_Rx 925.2 - 959.8 1805.2 - 1879.8 1930.2 - 1989.8 AWWMX5010 2002/05/08 2 of 5
F lo 1387.8 - 1439.7 1359.9 - 1409.9 1447.7 - 1492.4
PROPRIETARY INFORMATION
Any part of this document must not be disclosed to third parties without prior written permission.
V-C10
VCCD VPWR V-C10
IC401 Integrated Analog Processor
CX20505
LDO Regulators Internal ref.
Bandgap
Bias generator
System Reset
Q705 Reset POR
PCONT Internal supplies
Q704 Voltage Logic RESETB
generator
TXIP
TXIN LPF 10bit DAC
Transmit
I / Q Signals Offset GMSK
Modulator
TXQP LPF
TXQN 10bit DAC
Power Ramp Phase / Gain
Control PACOUT2 Balance 148-bits
Burst Store
SYNDAT
Synthesizer / DCR SYNLE 16-Bit 32 x16-Bit
Control SYNCLK RAMP DAC Ramp Store
SYNEN Tx Data and
GPO Radio Control I/O
Mapping Tune Store CTLRT
TXEN0 Control
TXEN1 Logic Serial CTLCLK
Tx / Rx VC1 Interface CTLDATA
Control VC4 Intra-Frame RPNSDAT
RXEN1 Sequencer
Status &
Temp. Monitor
GSM Frame Sensor
Timing F RT
8-Bit
Aux-ADC Clock F401
BPDET Gen CCXO 19.5MHz
Trap Tune X'tal
Synth. Reference SYNREF
19.5MHz 3.9MHz Master Clock
R419, C410, C411, L401 SYSCLK
RXIP Decimator FIR Rx Data to Baseband
RXIN ADC Filter Receiver RXCLK
Receive (Receive I / Q Signal) Serial RXDAT
I / Q Signals RXQP FIR Interface RXRT
ADC Decimator
RXQN Filter
MIC+
MP401 Bias
MIC MIC- LPF
ADC
FIR Digital Audio Data
HDSTDET Filter
LPF CODEC CDCCLK
P401 AUXIN Bias CDCRT
Headset Jack AUXOUT Serial
HDSTDET Interface
Tx Digital Audio
ENCDA
FIR Rx Digital Audio
LPF DAC DECDA
VBAT Filter
MP402
IC704 EP receiver
AVDD Reg.
VCCD
AVCONT V.Reg.
(AVDD)
SDIN Timbre Data IC402
Melody IC Timbre Melody IC YMU757B
Control SYNC Serial I/F Register
SCLK Tempo
Start/Stop
Score Timbre
Data Allotment
Title
IRQ FIFO FM DAC & MP403 Baseband / Audio Interface Block Diagram
Sequencer
32 words Synthesizer Volume Audio Speaker System HW Rev. Drawn by Chk'd by Approved by
MX-5010 2.50 K.Tsuchida S.Ohmomo K.Sakayori
RESETB CR Reset FCC ID Date Page Maxon Telecom Co., Ltd.
AWWMX5010 2002/05/08 3 of 5
R417, R418
C447 PROPRIETARY INFORMATION
Any part of this document must not be disclosed to third parties without prior written permission.
VCCD VBAT
IC601 Baseband Processor CX805
3.9MHz Master Clock Reg.
SYSCLK IC703
CLKRQST Clock Generation Internal
and PLL Core LDO RTC Reg.
Supply F601 BT701
ARM RTC Backup Battery
32kHz X'tal
RESETB Interrupt
IROM IRAM CACHE RTC 32kHz
IC702 (1/2) Controller
AND
Power Control
ALAM
Clock System
enables Reset RESETB System Reset
VCCD F_RP
(Flash Reset)
Serial SRLDATA Power
FLASH ROM External ARM7 Thumb Bus SRLCLK Management
Block Control
8MB (x8bits) Bus
CPU Core IrDA
Pulse
Layer2/3 Processing
Shaper IRDAEN IC603
SRAM CRC MMI/Browser etc.
IrDA Module
1MB (x8bits) Escape
Timers Sequence
IC602 /Flow
Control
FLASH/SRAM Dual-port RAM
DMA
Controller Serial
SDSTX
Port SDSRX PJ601 (1/2)
(SDS) System Connector
DAITX
CTLRT DSP Core DAIRX
CTLCLK Control Speech Viterbi Debug DAIRST / HDSTDET DAIRST
CTLDATA Port CODEC Port
RPNSDAT (DBG) DAICLK
Ciphering Layer1
RXCLK
Receive Auto
RXDAT
RXRT Port Baud
AVCONT
CDCCLK
CDCRT CODEC
SDIN Melody IC
ENCDATA Port GPIO SYNC Control
VBAT SCLK
DECDATA IRQ
Keypad
/LCD SIM I/F
LEDCTL I/F F RT GSM FrameTiming
DC/DC
IC706 PCONT Power Control
DC/DC Conv.
LM2750. TAPRESNT
VBAT
VCCD ESES
Accessory Detect /
Power Control
P501
Backlight BtoB
LEDs MEN Vibrating Alert
H801
Connector
LCD
BOOSTEN
SIMEN
SIMDATA SIM I/O
SIMCLK
SIMRST
SEND END
(POWER)
1 2 3 Q802
PWRON0
4 5 6
7 8 9
Title
* 0 #
MMI GSM Processor Block Diagram
PCB System HW Rev. Drawn by Chk'd by Approved by
MX-5010 2.50 K.Tsuchida S.Ohmomo K.Sakayori
FCC ID Date Page Maxon Telecom Co., Ltd.
AWWMX5010 2002/05/08 4 of 5
PROPRIETARY INFORMATION
Any part of this document must not be disclosed to third parties without prior written permission.
VCHRG
V-BAT
D703 Q701 R704
IC701
Power Management IC
VBAT
CX20460
P701 +
Battery ID Charger LDO Reg. VCCD
Contact - Control For
Current Digital
Sens
Amp Reference
BPDET LDO Reg. VUHF
For
UHF VCO
ALAM
PWRON0 LDO Reg. VRF
For
VCHRG
RF circuit
VTIC
PJ601 (2/2) VCHRG1/2 EXPWROUT LDO Reg.
System EXTPWRSW IC702 (2/2) For
Connector EXPWROUT AND PMICINT Tx circuit
SHUTDOWN
LDO Reg.
PMICRST V3
SRLDATA
SRLCLK Control
Logic Regulator
SYNEN V7
TXEN1
RXEN1
Reg.
V8
TAPRESNT
Q702
Power
SIM card External
POR Regulator
On Booster
Reset
BOOSTEN
SIMEN SIM Card P601
SIMDATA Interface SIM Contact
SIMCLK
SIMRST
SIM
IC705
VBAT Regulator
EXPWROUT
VIN OUT
ESES ON
VBAT Q601 D603
MP801
V Vibrating Title
MEN
Motor
SIM and Power Management Block Diagram
System HW Rev. Drawn by Chk'd by Approved by
D604 MX-5010 2.50 K.Tsuchida S.Ohmomo K.Sakayori
FCC ID Date Page Maxon Telecom Co., Ltd.
AWWMX5010 2002/05/08 5 of 5
PROPRIETARY INFORMATION
Any part of this document must not be disclosed to third parties without prior written permission.