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5 4 3 2 1
BOM MARK
I@: INT VGA
ZK2 SYSTEM BLOCK DIAGRAM DDR PWR
TPS5116 P36
CHARGER
ISL6251 P32
E@: STUFF FOR EXT VGA THERMAL 3/5V SYS PWR
ND@: STUFF FOR NON-DOCK X'TAL PROTECTION P37 ISL6237 P33
14.318MHz
D@: DOCK
SP@: SPECIAL FOR EXT/INT VGA
Penryn 479 Thermal Sensor Fan Driver 2.5V/ 1.5V PWR CPU CORE PWR
D
CLOCK GENERATOR uFCPGA (NS LM95245) (G991) DISCHARGER P38 ISL6262A P34
D
P3, P4 P3 P30
ICS: ICS9LPRS365BGLFT
SELGO: SLG8SP512K05
POWER TREE +1.05V
P2 P39 RT8202 P35
FSB
667/800/1067 Mhz
MXM (n-Vidia) EXT_LVDS
NB9M-GS EXT_CRT CRT
PCIE P18
VRAM 512MB EXT_DVI SWITCH
DDRII NB P17 LVDS
P18
SO-DIMM 0 Dual Channel DDR2 CIRCUIT
Cantiga LVDS INT_LVDS
SO-DIMM 1 667/800 MHz
P16 (GM45/ PM45/ GL40) RGB INT_CRT P18
C
P5, P6, P7, P8, P9, P10, P11 HDMI C
P19
HDMI switch
(PS8122)
MP-Stage DOCKING/DVI
X4 DMI interface P19 P19
31ZK2MB0000: ZK2 MB ASSY(GM/UMA)ASSY W/O CPU HDD (SATA) *2
31ZK2MB0010: ZK2 MB ASSY(PM/MXM)ASSY W/O CPU
P23
USB6
31ZK2MB0020: ZK2 MB ASSY(PM/MXM) W/O CPU/E-SATA
SATA0
PCI-Express PCIE-1 New Card
eSATA Conn. eSATA Buffer ODD (SATA) SATA4
(PI2EQX3021) P29 USB6 P26
USB1 P29
P23
SATA1 SB
PCIE-2&4 Mini Card
SATA5
ICH9M USB8
USB Port x 3 WLAN / TV
USB0, 4, 7 P29 USB 2.0 X'TAL
USB2 & 3 P22
B PCIE-6 X'TAL B
32.768KHz
Azalia 25MHz
Bluetooth P12,P13,P14,P15 USB2 & 3
USB5 P21
Media ATHEROS
SPI LPC Cardreader Giga-LAN
CCD (RTS5158E) (AR8121)
USB11 P18
USB2 P27 P20
FingerPrint Audio CODEC HDCP ROM EC (WPC775LDG)
(Option)
USB9 P30 (ALC888S) P24 P13 P31
X'TAL
32.768KHz
Wire Docking RJ11 Card Reader DOCK/LAN
USB10 P30 LAN SWITCH
MDC 1.5 WIRE CONN.
Connector
P24
SPI ROM P27 (PI3L500) P21 P30
P31
DA0ZK2MB6D0
Sub-Amplifier DA0ZK2MB6C0
A
Audio Amplifier Transformer P21 DA0ZK2MB6B0
A
(MAX9736B) Touch Pad MMB
P24,P25 P25
P30 P28
DA0ZK2MB6A0
RJ45 Quanta Computer Inc.
P21
Speaker S/PDIF SUBWOOFER Line in MIC Jack Int. D-MIC K/B COON. CIR PROJECT : ZK2
P25 P25 P25 P25 P25 P18, P24 P30 P31 Size Document Number Rev
3B
Block Diagram
Date: Friday, June 27, 2008 Sheet 1 of 39
5 4 3 2 1
5 4 3 2 1
Clock Generator
+3V L39 BKP1608HS181-T +3V_CLK U30 CLK VDD power range 1.05V~3.3V
C474 C475 C472 C492 C498 C496 C491 2 12 +1V05_CLK L38 BKP1608HS181-T +1.05V
VDD_PCI VDD_I/O
9 VDD_48 VDD_PLL3_I/O 20
.1u_4 *.1u_4 .1u_4 *.1u_4 .1u_4 .1u_4 10u_6 16 26 C486 C470 C499 C471 C469 C497 C500
VDD_PLL3 VDD_SRC_I/O_1
39 VDD_SRC VDD_SRC_I/O_2 36
55 45 10u_6 .1u_4 .1u_4 *.1u_4 .1u_4 .1u_4 .1u_4
C484 33p/50V_4 VDD_CPU VDD_SRC_I/O_3
D 61 VDD_REF VDD_CPU_I/O 49 D
CG_XIN 60 37 PM_STPCPU# (14)
XTAL_IN CPU_STOP#
Y5
CG_XOUT PCI_STOP# 38 PM_STPPCI# (14) Pin 56 : It acts as a
14.318MHz 59 56 CK_PWRGD (14)
XTAL_OUT CKPWRGD/PD# level sensitive strobe
C488 33p/50V_4
CPU_0 54 CLK_CPU_BCLK (3) to latch the FS pins
53
(14) SATACLKREQ# R489 475/F_4 SATACLKREQ#_R 1 CPU_0#
51
CLK_CPU_BCLK# (3)
CLK_MCH_BCLK (5)
and other multiplexed
NEW_CLKREQ#_R 3 PCI_0/CLKREQ_A# CPU_1_MCH
(26) NEW_CLKREQ# R496 475/F_4
PCLK_MINI_R PCI_1/CLKREQ_B# CPU_1_MCH# 50 CLK_MCH_BCLK# (5) inputs.
4 PCI_2 SRC_8/CPU_ITP 47
R511 33_4 PCLK_MINI_R PCLK_591_R 5 46
(22) PCLK_DEBUG PCI_3 SRC_8#/CPU_ITP#
R523 33_4 PCLK_591_R T85 PCLK_PCM_R 6
(31) PCLK_591 ^PCI_4/LCDCLK_SEL
R519 33_4 PCLK_ICH_R PCLK_ICH_R 7
(13) PCLK_ICH PCIF_5/ITP_EN
CPU_BSEL0 R521 2.2K_4 48
R520 22_4 NC
C501 C504 C505 (14) CLKUSB_48 R522 22_4 FSA 10
*10p_4 *10p_4 *10p_4 (27) CLK_Card48 MCH_BSEL1 57
USB_48MHz/FS_A
FS_B/TEST_MODE
LCDCLK/27M 17 CLK_DREFSSCLK (6)
CPU_BSEL2 R478 10K_4 18
LCDCLK#/27M_SS CLK_DREFSSCLK# (6)
R479 33_4 FSC 62
(14) 14M_ICH REF/FS_C/TEST_SEL
C473 *30p/50V_4
(6) CLK_DREFCLK 13 SRC_0/DOT_96 SRC_2 21 CLK_PCIE_SATA (12)
(6) CLK_DREFCLK# 14 SRC_0#/DOT_96# SRC_2# 22 CLK_PCIE_SATA# (12)
SRC_3/CLKREQ_C# 24 CLK_PCIE_LAN (20)
+3V CGCLK_SMB 64 25
C SCL SRC_3#/CLKREQ_D# CLK_PCIE_LAN# (20) C
CGDAT_SMB 63 27
SDA SRC_4 CLK_PCIE_NEW_C (26)
SRC_4# 28 CLK_PCIE_NEW_C# (26)
SRC_6 41 CLK_PCIE_ICH (13)
SRC_6# 40 CLK_PCIE_ICH# (13)
Q35 R483 R484 44
SRC_7/CLKREQ_F# CLK_MXM (17)
RHU002N06 8 43
VSS_PCI SRC_7#/CLKREQ_E# CLK_MXM# (17)
2
10K_4 10K_4 11 30
VSS_48 SRC_9 CLK_PCIE_MINI1 (22)
15 VSS_I/O SRC_9# 31 CLK_PCIE_MINI1# (22)
3 1 CGDAT_SMB 19 34
(14,16,19,20,22,26) PDAT_SMB VSS_PLL3 SRC_10 CLK_PCIE_3GPLL (6)
23 VSS_SRC_1 SRC_10# 35 CLK_PCIE_3GPLL# (6)
29 VSS_SRC_2 SRC_11/CLKREQ_H# 33 CLK_PCIE_TV (22)
42 VSS_SRC_3 SRC_11#/CLKREQ_G# 32 CLK_PCIE_TV# (22)
+3V 52 VSS_CPU
58 VSS_REF
Q33
RHU002N06
2
SLG8SP512
3 1 CGCLK_SMB
(14,16,19,20,22,26) PCLK_SMB
B CPU Clock select Strap table B
+3V
BSEL Frequency Select Table Control CPU_0 & SRC_2
R490 10K_4 SATACLKREQ#_R
FSC FSB FSA Frequency Control CPU_1 & SRC_4
Pin 10/57/62 : For Pin CPU frequency selection R497 10K_4 NEW_CLKREQ#_R
0 0 0 266Mhz R512 10K_4 PCLK_MINI_R R513 *10K_4 Reserve overclocking
CPU_BSEL0 R524 0_4
(3) CPU_BSEL0 MCH_BSEL0 (6)
0 0 1 133Mhz
PCLK_PCM_R R508 10K_4
0 1 1 166Mhz
CPU_BSEL1 R480 0_4
(3) CPU_BSEL1 MCH_BSEL1 (6)
0 1 0 200Mhz Pin 6 : For Pin 13/14 and 17/18 selection
0 = LCDCLK & DOT96 for internal graphic controller support
1 1 0 400Mhz 1 = 27M & 27M_SS &SRC_0 for external graphic controller support
CPU_BSEL2 R476 0_4
(3) CPU_BSEL2 MCH_BSEL2 (6)
1 1 1 Reserved
PCLK_ICH_R R518 10K_4
A A
1 0 1 100Mhz
1 0 0 333Mhz Pin 7 : For Pin 46/47 selection
1 = CPU_ITP
Quanta Computer Inc.
0 = SRC_8 PROJECT : ZK2
CLOCK GENERATOR Size
Date:
Document Number
CLOCK GENERATOR
Wednesday, July 09, 2008 Sheet 2 of 39
Rev
3B
5 4 3 2 1
5 4 3 2 1
(5) H_A#[3..16]
U25A
H_A#3 J4 H1
A[3]# ADS# H_ADS# (5) H_D#[0..15] H_D#[32..47]
H_A#4
ADDR GROUP_0
L5 E2 U25B
A[4]# BNR# H_BNR# (5) (5) H_D#[0..15] H_D#[32..47] (5)
H_A#5 L4 G5 H_D#0 E22 Y22 H_D#32
A[5]# BPRI# H_BPRI# (5) D[0]# D[32]#
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 A[6]# H_D#2 D[1]# D[33]# H_D#34
M3 A[7]# DEFER# H5 H_DEFER# (5) E26 D[2]# D[34]# V24
H_A#8 H_D#3 H_D#35
DATA GRP 0
N2 A[8]# DRDY# F21 H_DRDY# (5) G22 D[3]# D[35]# V26
DATA GRP 2
H_A#9 J1 E1 H_D#4 F23 V23 H_D#36
A[9]# DBSY# H_DBSY# (5) D[4]# D[36]#
H_A#10 N3 H_D#5 G25 T22 H_D#37
H_A#11 A[10]# H_D#6 D[5]# D[37]# H_D#38
P5 A[11]# BR0# F1 H_BREQ# (5) E25 D[6]# D[38]# U25
H_A#12 P2 H_D#7 E23 U23 H_D#39
D
H_A#13 A[12]# H_IERR# R180 56_4 H_D#8 D[7]# D[39]# H_D#40 D
CONTROL
L2 A[13]# IERR# D20 +1.05V K24 D[8]# D[40]# Y25
H_A#14 P4 B3 H_D#9 G24 W22 H_D#41
A[14]# INIT# H_INIT# (12) D[9]# D[41]#
H_A#15 P1 H_D#10 J24 Y23 H_D#42
H_A#16 A[15]# H_D#11 D[10]# D[42]# H_D#43
R1 A[16]# LOCK# H4 H_LOCK# (5) J23 D[11]# D[43]# W24
M1 H_D#12 H22 W25 H_D#44
(5) H_ADSTB#0 ADSTB[0]# D[12]# D[44]#
C1 H_D#13 F26 AA23 H_D#45
(5) H_REQ#[0..4] RESET# H_CPURST# (5) D[13]# D[45]#
H_REQ#0 K3 F3 H_D#14 K22 AA24 H_D#46
REQ[0]# RS[0]# H_RS#0 (5) D[14]# D[46]#
H_REQ#1 H2 F4 H_D#15 H23 AB25 H_D#47
REQ[1]# RS[1]# H_RS#1 (5) D[15]# D[47]#
H_REQ#2 K2 G3 J26 Y26
REQ[2]# RS[2]# H_RS#2 (5) (5) H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 (5)
H_REQ#3 J3 G2 H26 AA26
REQ[3]# TRDY# H_TRDY# (5) (5) H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 (5)
H_REQ#4 L1 H25 U22
REQ[4]# (5) H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 (5)
(5) H_A#[17..35] HIT# G6 H_HIT# (5)
H_A#17 Y2 E4 H_D#[16..31] H_D#[48..63]
A[17]# HITM# H_HITM# (5) (5) H_D#[16..31] H_D#[48..63] (5)
H_A#18 U5 H_D#16 N22 AE24 H_D#48
H_A#19 A[18]# XDP_BPM#0 H_D#17 D[16]# D[48]# H_D#49
R3 A[19]# BPM[0]# AD4 T11 K25 D[17]# D[49]# AD24
H_A#20 XDP_BPM#1 H_D#18 H_D#50
ADDR GROUP_1
W6 A[20]# BPM[1]# AD3 T14 P26 D[18]# D[50]# AA21
H_A#21 U4 A[21]# BPM[2]# AD1 XDP_BPM#2 T13 H_D#19 R23 D[19]# D[51]# AB22 H_D#51 Layout note:
H_A#22 Y5 AC4 XDP_BPM#3 T10 H_D#20 L23 AB21 H_D#52
H_A#23 A[22]# BPM[3]# XDP_BPM#4 H_D#21 D[20]# D[52]# comp0,2: Zo=27.4ohm, L<0.5"
DATA GRP 1
U1 AC2 M24 AC26 H_D#53
XDP/ITP SIGNALS
A[23]# PRDY# T12 D[21]# D[53]#
DATA GRP 3
H_A#24 R4 A[24]# PREQ# AC1 XDP_BPM#5 H_D#22 L22 D[22]# D[54]# AD20 H_D#54 comp1,3: Zo=55ohm, L<0.5"
H_A#25 T5 AC5 XDP_TCK Connect it to CPU DBR# is for ITP debug port H_D#23 M23 AE22 H_D#55
H_A#26