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THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D TABLE OF CONTENTS D
1. COVER PAGE 38. AC97 AUDIO CODEC
2. BLOCK DIAGRAM 39. AUDIO AMP
3. POWER DIAGRAM 40. HDD / ODD / MDC CONNECTOR
4. BOARD INFORMATION 41. MICOM
FIRENZE 5. CLOCK DIAGRAM
6. RESET DIAGRAM
7. CLOCK GENERATOR
42. LAN CONTROLLER
43. KBD/TOUCHPAD/HP/MIC
44. USB PORTS / LED / ON-TOP
8. CPU (1/3) 45. CHARGER
9. CPU (2/3) 46. 3.3V / 5V GENERATION
10. CPU (3/3) 47. 1.5V_AUX / VTT
CPU :Dothan533 11. THERMAL SENSOR / FAN CONTROL 48. DDR2 POWER
12. NORTH BRIDGE (1/5) 49. GRAPHIC CORE POWER
C Chip Set :ALVISO & ICH6-M 13. NORTH BRIDGE (2/5) 50. CPU POWER C
14. NORTH BRIDGE (3/5) 51. 1.2V / 2.5V POWER
Remarks :EXTERNAL GFX 15. NORTH BRIDGE (4/5) 52. MICOM & SWITCHED POWER
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16. NORTH BRIDGE (5/5) 53. 5-IN-1 SUB B'D
17. DDR2 - SODIMM 54. AIR BAG
18. DDR2- TERMINATION 55. TESTPOINTS-1
19. SOUTH BRIDGE (1/4)
Model Name : FIRENZE 20. SOUTH BRIDGE (2/4)
21. SOUTH BRIDGE (3/4)
PBA Name : MAIN 22. SOUTH BRIDGE (4/4)
23. FWH
PCB Code : BA41-00509A 24. GRAPHICS CONTROLLER (1/4)
25. GRAPHICS CONTROLLER (2/4)
Dev. Step : MP 26. GRAPHICS CONTROLLER (3/4)
B 27. GRAPHICS CONTROLLER (4/4) B
Revision : 1.0 28. GRAPHICS MEMORY TERMINATION (1/2)
29. GRAPHICS MEMORY TERMINATION (2/2)
T.R. Date : 2005.06.07 30. GRAPHICS MEMORY (1/2)
31. GRAPHICS MEMORY (2/2)
32. CRT PORT
33. LCD / TV-OUT
34. CARDBUS CONTROLLER (1/2)
DRAW CHECK APPROVAL 35. CARDBUS CONTROLLER (2/2)
36. CARDBUS CONNECTOR / MEDIA CARD
37. MINI PCI
A A
SON,C.W YUN,C.Y LIM,J.G SAMSUNG
ELECTRONICS
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SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
FAN CPU
Clocking DC/DC System DC/DC
CK-410M
PG 11 Mobile Processor IMVP-IV
D D
R 1.3
PG 5 CPU Dothan(w/533MHz) PG 50
PG 46
Thermistor
MAX6656
PG 11 L2 Cache : 2 MB
PG 8,9,10 478pin
PCIE Graphics Module
FSB
100P X 2 533 MHZ
Ext. AGP PEG x16 External Graphics PG 17
Channel A (Standard) DDR II
CRT/TV ATI M22-P
PG 24,25,26,27
SODIMM 0
MCH-M Dual channel DDR II 533/400
PG 17
DDR II
ALVISO Channel B (Reverse)
SODIMM 1
1257 FCBGA
PG 12,13,14,15,16
30P LVDS Internal Graphics
LCD CRT/TV
5-IN-1 PG 36
C PG 33 Direct Media Interface C
x4/x2, 1.5V
CARDBUS CardBus PG 36
R5C841
PG 32 CRT R5532V002 EEPROM PG 34
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PG 34,35
1394
TV 33MHz, 3.3V PCI
CARDBUS Module 6pin
PG 33
PG 35
SVHS PG 44
USB
USB 0,1,2,3 ICH6-M BROADCOM
RJ45
609 BGA BCM4401
PG 42 PG 42
Azalia/AC97 Primary PG 19,20,21,22 Mini PCI CONN.
PG 37
AUDIO 30P
Audio MDC
Azalia/AC97 Secondary
RJ11 Modem
AMP AD1981B
B PG 39 PG 42 (TBD) B
PG 38 PG 40 3.3V LPC, 33MHz
HP & SPDIF
MIC-IN
PG 43 4P
PG 39 FWH
PG 23
Pri. IDE master PATA
HDD
Pri. IDE slave
PG 40
U-ATA 100
SPKR R
Touch
60x2P MICOM PAD
PG 43
Hitachi H8S
HD64F2169/2160
KBD PG 43
SPKR L PG 41
PG 40
CD-ROM
A A
CD / DVD
SAMSUNG
ELECTRONICS
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SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
Power Diagram
D KBC3_PWRON D
ALWAYS KBC3_SUSPWR KBC3_VRON
VDC P1.5V
CPU
NORTH BRIDGE
SOUTH BRIDGE
P1.5V_AUX
SOUTH BRIDGE GRAPHICS CTRL
P1.2V
CLOCK GENERATOR GRAPHICS CTRL ODD
P3.3V_AUX P3.3V THERMAL SENSOR CARDBUS CTRL MICOM
DDR II-SODIMM MINI PCI LED
SOUTH BRIDGE AUDIO CODEC TPM
SOUTH BRIDGE FWH HDD AIRBAG
MICOM_P3V MINI PCI
MDC
MICOM
C LAN NORTH BRIDGE C
MICOM BLUE TOOTH
P2.5V SOUTH BRIDGE
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SOUTH BRIDGE MICOM
P5V_AUX P5V MINI PCI TOUCH PAD
CRT USB
HDD
SOUTH BRIDGE
ODD
GRAPHICS CTRL
P1.8V_AUX P1.8V GRAPHICS MEMORY
NORTH BRIDGE
DDR II-SODIMM
DDR II-TERMINATION
B
P0.9V B
GRAPHICS CTRL : P1.0V - P1.2V
GFX_
CORE
NORTH BRIDGE
VTT SOUTH BRIDGE
VCC_CORE
Rail
+V*Always +V*AUX +V SUSPWR PWRON VRON
State
DOTHAN533 / YONAH
A Full On ON ON ON ON ON ON A
S3 ON ON OFF ON OFF OFF
S4 ON OFF OFF OFF OFF OFF SAMSUNG
ELECTRONICS
S5 ON OFF OFF OFF OFF OFF
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PROPRIETARY INFORMATION THAT IS
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DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION D
PCI Devices Voltage Rails
DEVICES IDSEL# REQ/GNT# INTERRUPTS
CARDBUS CONTROLLER AD25 0 A,B,C VDC Primary DC system power supply (9 to 20V)
MINIPCI AD23 1 E,F VCC_CORE Core voltage for DOTHAN (0.7~1.708V)
LAN CONTROLLER AD21 2 G VTT DOTHAN/ALVISO Processor System Bus(PSB) Termination (1.05V)
MCH-M Core Voltage (off in S3-S5)
GFX_CORE ATI M24-P Core Voltage (1.0~1.2V) (off in S3-S5)
P0.9V 0.9V power rail (off in S3-S5)
P1.2V 1.2V power rail (off in S3-S5)
P1.5V 1.5V switched power rail (off in S3-S5)
P1.5V_AUX 1.5V power rail (off in S4-S5)
P1.8V 1.8V switched power rail (off in S3-S5)
P1.8V_AUX 1.8V power rail(off in S4-S5)
P2.5V 2.5V power rail (off in S3-S5)
MICOM_P3V 3.3V always on power rail for MICOM
P3.3V 3.3V switched power rail (off in S3-S5)
P3.3V_AUX 3.3V power rail (off in S4-S5)
C C
P5V 5.0V switched power rail (off in S3-S5)
P5V_AUX 5.0V power rail (off in S4-S5)
CPU Core Voltage Table
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2
VID5 VID4 VID3 VID2 VID1 VID0 Voltage VID5 VID4 VID3 VID2 VID1 VID0 Voltage
0 0 0 0 0 0 1.708 V 1 0 0 0 0 0 1.196 V Northwood-B
I C / SMB Address
0 0 0 0 0 1 1.692 V 1 0 0 0 0 1 1.180 V (Interposer B'd) Devices Address Hex Bus
0 0 0 0 1 0 1.676 V 1 0 0 0 1 0 1.164 V
0 0 0 0 1 1 1.660 V 1 0 0 0 1 1 1.148 V SOUTH BRIDGE Master - SMBUS Master
0 0 0 1 0 0 1.644 V 1 0 0 1 0 0 1.132 V ADM1032(CPU Thermal Sensor) 1001 110X 9Ch Thermal Sensor
0 0 0 1 0 1 1.628 V 1 0 0 1 0 1 1.116 V SODIMM0 1010 0000 A0h -
0 0 0 1 1 0 1.612 V 1 0 0 1 1 0 1.100 V SODIMM1 1010 001X A2h -
0
- 0
- 0 1 1 1 1.596 V 1 -
0 0 1 1 1 1.084 V CK-408 (Clock Generator) 1101 001x D2h Clock, Unused Clock Output Disable
0 0 1 0 0 0 1.580 V 1 0 1 0 0 0 1.068 V
0 0 1 0 0 1 1.564 V 1 0 1 0 0 1 1.052 V
0 0 1 0 1 0 1.548 V 1 0 1 0 1 0 1.036 V
0 0 1 0 1 1 1.532 V 1 0 1 0 1 1 1.020 V
0 0 1 1 0 0 1.516 V 1 0 1 1 0 0 1.004 V
0
0
0
0
1
1
1
1
0
1
1
0
1.500 V
1.484 V
1
1
0
0
1
1
1
1
0
1
1
0
0.988 V
0.972 V USB PORT Assign
0 0 1 1 1 1 1.468 V 1 0 1 1 1 1 0.956 V
0 1 0 0 0 0 1.452 V 1 1 0 0 0 0 0.940 V PORT NUMBER ASSIGNED TO
0 1 0 0 0 1 1.436 V 1 1 0 0 0 1 0.924 V
0 1 0 0 1 0 1.420 V 1 1 0 0 1 0 0.908 V 1,3 SYSTEM PORT A
0 1 0 0 1 1 1.404 V 1 1 0 0 1 1 0.892 V 0,2 SYSTEM PORT B
B 0 1 0 1 0 0 1.388 V 1 1 0 1 0 0 0.876 V B
0 1 0 1 0 1 1.372 V 1 1 0 1 0 1 0.860 V
Highest Freq. 0 1 0 1 1 0 1.356 V 1 1 0 1 1 0 0.844 V Lowest Freq.
0
- 1 0 1 1 1 1.340 V 1 1 0 1 1 1 0.828 V
0 1 1 0 0 0 1.324 V 1 1 1 0 0 0 0.812 V
0 1 1 0 0 1 1.308 V 1 1 1 0 0 1 0.796 V
0 1 1 0 1 0 1.292 V 1 1 1 0 1 0 0.780 V
0
0
1
1
1
1
0
1
1
0
1
0
1.276 V
1.260 V
1
1
1
1
1
1
0
1
1
0
1
0
0.764 V
0.748 V Deeper Sleep System Power States
0 1 1 1 0 1 1.244 V 1 1 1 1 0 1 0.732 V CHP3_SLPS1* S1, Powered-On-Suspend(POS) : In this state, all clocks(except the 32.768KHz clock) are stopped.
0 1 1 1 1 0 1.228 V 1 1 1 1 1 0 0.716 V The system context is maintained in system DRAM. Power is maintained to PCI, the CPU, memory controller, memory, and all other criticial subsystems.
0 1 1 1 1 1 1.212 V 1 1 1 1 1 1 0.700 V Note that this state does not preclude power being removed from non-essential devices, such as disk drives. During this state, CPU can be selected
for either Deep Sleep or Deeper Sleep.
In Deeper Sleep, CPU voltage reduced in this state to reduce the leakage power.
CHP3_SLPS3* S3, Suspend-To-RAM(STR) : The system context is maintained in system DRAM, but power is shut off to non-critical circuits.
Memory is retained, and refreshes continue. All clocks stop except RTC clock.
CHP3_SLP4S* S4, Suspend-To-Disk(STD) : The Context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume.
Externally appears same as S5, but may have different wake events.
CHP3_SLPS5* S5, Soft Off(SOFF) : System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking.
REVISION HISTORY
A A
See rev notes in the changes file for more information.
SAMSUNG
ELECTRONICS
MiniPCI SLOT1
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PROPRIETARY INFORMATION THAT IS
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DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D 133MHZ D
CPU
133MHZ #
100MHZ
GRAPHICS
100MHZ#
CONTROLLER
27 MHZ
GENERATOR
100MHZ
100MHZ#
SOUTH BRIDGE
CLOCK 48MHZ
33MHZ
C C
ACZ_BIT_CLK
AUDIO CODEC
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14.318MHZ 24.576MHZ
32.768KHZ
133MHZ NORTH BRIDGE 200/267MHZ
133MHZ#
200/267MHZ#
100MHZ
200/267MHZ DDR II SODIMM A
200/267MHZ#
100MHZ#
200/267MHZ
B B
200/267MHZ#
200/267MHZ DDR II SODIMM B
200/267MHZ#
33MHZ
MINIPCI
33MHZ
FWH
33MHZ
MICOM 10MHZ
33MHZ
CARDBUS
33MHZ
LAN 25MHZ
14.318MHZ
A A
SAMSUNG
ELECTRONICS
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PROPRIETARY INFORMATION THAT IS
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RESET DIAGRAM
D D
CPU1_CPURST*
PCI3_RST*
CPU1_PWRGDCPU
KBC3_IMVP4_PWRGD
IMVP4_PWRGD
C C
VCC_CORE
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VTTPWRGD
P3.3V
P5V
KBC3_PWRON
B
CHP3_SLPS3* B
KBC3_RSMRST*
P3.3V_AUX
KBC3_SUSPWR
KBC3_PWRSW#
A A
SAMSUNG
ELECTRONICS
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PROPRIETARY INFORMATION THAT IS
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D D
P3.3V
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
16V
16V
16V
16V
16V
16V
16V
16V
16V
BLM18PG181SN1
B18
C190
100nF
C186
C230
C231
C934
C920
C921
C184
C234
C233
FSA FSB FSC 16V
HOST CLK
BSEL2 BSEL1 BSEL0 NO_STUFF
1 0 0 133 MHz U616
1 0 1 100 MHz ICS954201BGLF
100nF
100nF
16V
16V
16V
R232 21