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TABLE OF CONTENTS
INPUT IMAGE SIGNAL SAMPLING AREA .........................................................................................................4
OUTPUT IMAGE SIGNAL AND DISPLAY AREA................................................................................................6
OUTPUT MODE 800X600@60HZ ...............................................................................................................................7
OUTPUT MODE 1024X768@60HZ .............................................................................................................................7
OUTPUT MODE 1280X1024@60HZ ...........................................................................................................................8
DE-INTERLACE MODES........................................................................................................................................9
CALCULATION OF SCALING DOWN/UP FACTOR.........................................................................................13
SCALING DOWN FACTOR ........................................................................................................................................13
SCALING UP FACTOR..............................................................................................................................................15
Horizontal Scaling up factor Examples..............................................................................................................15
Vertical Scaling up factor Examples..................................................................................................................16
BUS TYPES .............................................................................................................................................................18
DIRECT BUS ...........................................................................................................................................................18
SERIAL BUS ...........................................................................................................................................................18
NOTICE OF USING OF SERIAL BUS ..................................................................................................................20
FLUSH FUNCTION ................................................................................................................................................21
LINE WRITE...........................................................................................................................................................22
LINE READ.............................................................................................................................................................24
GAMMA FUNCTION .............................................................................................................................................26
PROCEDURE OF MEMORY CLOCK AND OUTPUT DOT CLOCK PROGRAMMING. ...............................27
MEMORY CLOCK REQUIREMENTS AND MEMORY AND OUTPUT VIDEO CLOCK CALCULATION.28
MEMORY CLOCK REQUIREMENTS -- MINIMUM MCLK (MHZ) ................................................................................28
MEMORY CLOCK CALCULATION: ............................................................................................................................28
OUTPUT VIDEO CLOCK CALCULATION:....................................................................................................................29
PROCEDURE OF AUTO TRACKING..................................................................................................................30
AUTO POSITION PROCEDURE ..........................................................................................................................32
MX88L284-V
Revision: 1.0
PROCEDURE OF DRAM SELF-TEST..................................................................................................................34
HOW TO USE EDGE FILTER...............................................................................................................................35
EXTERNAL OSD CLOCK REGISTERS CONTROL PATH ...............................................................................39
CLAMPING SIGNAL POSITION AND BLOCK DIAGRAM ..............................................................................40
MEMORY CLOCK BLOCK DIAGRAM ..............................................................................................................41
SDRAM/SGRAM CONNECTION DIAGRAM......................................................................................................42
4M BYTE SDRAM (2 X 2M BYTE).........................................................................................................................42
32 bit mode for 1280 x 1024 @65Hz(with compression) and 1024 x 768 @85Hz modes.....................................42
2M BYTE SDRAM (1 X 2M BYTE).........................................................................................................................42
16 bit mode for 800x600 @85Hz mode..............................................................................................................42
4M BYTE SGRAM (2 X 2M BYTE).........................................................................................................................43
32 bit mode for 1280x1024 @60Hz(with compression) and 1024x768 @85Hz modes.........................................43
2M BYTE SGRAM (1 X 2M BYTE).........................................................................................................................43
32 bit mode for 800x600 @85Hz mode..............................................................................................................43
VIDEO DECODERS CONNECTION DIAGRAM ................................................................................................44
DOUBLE BUFFER REGISTER .............................................................................................................................45
MX88L284 DOUBLE BUFFER REGISTER LIST ................................................................................................46
INTERRUPT CONTROL .......................................................................................................................................50
SYSTEM NOTES ....................................................................................................................................................51
3
MX88L284-V
Revision: 1.0
Input Image Signal Sampling Area
HSYNC VSYNC
ISSPV
Register
08h/09h
ISSPH
Register
0Ah/0Bh
(Reg. 11h D4=0) ISDCV
Sampled image area Register
0Ch/0Dh
ISSPH
Register
0Ah/0Bh
(Reg. 11h D4=1)
ISDCH
Register
0Eh/0Fh
Fig. 1 Input image signal sampling area
INPUT MODE ISSPV REG. ISDCV REG. ISSPH REG. ISDCH REG.
Register 0x08 0x09 0x0C 0x0D 0x0A 0x0B 0x0E 0x0F
720x400@70Hz 0x22 0x00 0x90 0x01 0x38 0x00 0xD0 0x02
640x350@85Hz 0x3B 0x00 0x5E 0x01 0x33 0x00 0x80 0x02
720x400@85Hz 0x2A 0x00 0x90 0x01 0x6C 0x00 0xD0 0x02
640x350@85Hz 0x3C 0x00 0x5E 0x01 0x60 0x00 0x80 0x02
640x480@85Hz 0x19 0x00 0xE0 0x01 0x50 0x00 0x80 0x02
640x480@75Hz 0x10 0x00 0xE0 0x01 0x78 0x00 0x80 0x02
640x480@72Hz 0x1C 0x00 0xE0 0x01 0x80 0x00 0x80 0x02
640x480@60Hz 0x21 0x00 0xE0 0x01 0x30 0x00 0x80 0x02
800x600@85Hz 0x1B 0x00 0x58 0x02 0x98 0x00 0x20 0x03
800x600@75Hz 0x15 0x00 0x58 0x02 0xA0 0x00 0x20 0x03
800x600@72Hz 0x17 0x00 0x58 0x02 0x40 0x00 0x20 0x03
800x600@60Hz 0x17 0x00 0x58 0x02 0x58 0x00 0x20 0x03
4
MX88L284-V
Revision: 1.0
INPUT MODE ISSPV REG. ISDCV REG. ISSPH REG. ISDCH REG.
Register 0x08 0x09 0x0C 0x0D 0x0A 0x0B 0x0E 0x0F
800x600@56Hz 0x16 0x00 0x58 0x02 0x80 0x00 0x20 0x03
1024x768@85Hz 0x24 0x00 0x00 0x03 0xD0 0x00 0x00 0x04
1024x768@75Hz 0x1C 0x00 0x00 0x03 0xB0 0x00 0x00 0x04
1024x768@70Hz 0x1D 0x00 0x00 0x03 0x90 0x00 0x00 0x04
1024x768@60Hz 0x1D 0x00 0x00 0x03 0xA0 0x00 0x00 0x04
1024x768@43i 0x14 0x00 0x00 0x03 0x38 0x00 0x00 0x04
1152x864@85Hz 0x2B 0x00 0x60 0x03 0xE0 0x00 0x80 0x04
1152x864@75Hz 0x20 0x00 0x60 0x03 0x00 0x01 0x80 0x04
1152x864@70Hz 0x2C 0x00 0x60 0x03 0xC8 0x00 0x80 0x04
1152x864@60Hz 0x25 0x00 0x60 0x03 0xC0 0x00 0x80 0x04
1280x960@60Hz 0x24 0x00 0xC0 0x03 0x38 0x01 0x00 0x05
1280x1024@85Hz 0x2C 0x00 0x00 0x04 0xE0 0x00 0x00 0x05
1280x1024@75Hz 0x26 0x00 0x00 0x04 0xF8 0x00 0x00 0x05
1280x1024@60Hz 0x26 0x00 0x00 0x04 0xF8 0x00 0x00 0x05
1280x1024@43i 0x12 0x00 0x00 0x04 0xB0 0x00 0x00 0x05
Remark: This table bases on VESA standard modes.
5
MX88L284-V
Revision: 1.0
Output Image Signal And Display Area
HDTOT
Register
2E h/2F h
HSEND
Register
32 h/33 h
HSYNC
HFEND
Register
2Ah/2Bh
HFST
Register
FHDE 26 h/27 h
HDEND MVDE FVDE VSYNC
Register
3A h/3Bh
HDST
Register
36 h/37 h VFST
MHDE VDST Register
Register 24 h/25 h
34 h/35 h
VSEND
Register
30 h/31 h
VDEND VDTOT
Register Register
38 h/39 h VFEND 2Ch/2Dh
Register
Display Area 28 h/29 h
Frame Window
The below figure shows the timing diagram of output signal:
Fig. 2 Output image signal and display area
6
MX88L284-V
Revision: 1.0
Output mode 640x480@60Hz
Timing name Value Register = Value -1
VDTOT 525(20Dh) 2Ch=0Ch 2Dh=02h
HDTOT 800(320h) 2Eh=1Fh 2Fh=03h
VSEND 2 30h=01h 31h=00h
HSEND 96(60h) 32h=5Fh 33h=00h
VFST/VDST 35(23h) 24h/34h=22h 25h/35h=00h
HFST/HDST 144(90h) 26h/36h=8Fh 27h/37h=00h
VFEND/VDEND 515(203h) 28h/38h=02h 29h/39h=02h
HFEND/HDEND 784(310h) 2Ah/3Ah=0Fh 2Bh/3Bh=03h
DCLK 25.175 B0h=BCh B1h=32h
H Sync Polarity NEGATIVE E4h bit 0 = 0
V Sync Polarity NEGATIVE E4h bit 1 = 0
Output mode 800x600@60Hz
Timing name Value Register = Value -1
VDTOT 628(274h) 2Ch=73h 2Dh=02h
HDTOT 1056(420h) 2Eh=1Fh 2Fh=04h
VSEND 4 30h=03h 31h=00h
HSEND 128(80h) 32h=7Fh 33h=00h
VFST/VDST 27(1Bh) 24h/34h=1Ah 25h/35h=00h
HFST/HDST 216(D8h) 26h/36h=D7h 27h/37h=00h
VFEND/VDEND 627(273h) 28h/38h=72h 29h/39h=02h
HFEND/HDEND 1016(3F8h) 2Ah/3Ah=F7h 2Bh/3Bh=03h
DCLK 40 B0h=B2h B1h=34h
H Sync Polarity POSITIVE E4h bit 0 = 1
V Sync Polarity POSITIVE E4h bit 1 = 1
Output mode 1024x768@60Hz
Timing name Value Register = Value -1
VDTOT 806(326h) 2Ch=25h 2Dh=03h
HDTOT 1344(540h) 2Eh=3Fh 2Fh=05h
VSEND 6 30h=05h 31h=00h
HSEND 136(88h) 32h=87h 33h=00h
VFST/VDST 35(23h) 24h/34h=22h 25h/35h=00h
7
MX88L284-V
Revision: 1.0
HFST/HDST 296(128h) 26h/36h=27h 27h/37h=01h
VFEND/VDEND 803(323h) 28h/38h=22h 29h/39h=03h
HFEND/HDEND 1320(528h) 2Ah/3Ah=27h 2Bh/3Bh=05h
DCLK 65 B0h=ACh B1h=BAh
H Sync Polarity NEGATIVE E4h bit 0 = 0
V Sync Polarity NEGATIVE E4h bit 1 = 0
Output mode 1280x1024@60Hz
Timing name Value Register = Value -1
VDTOT 1066(42Ah) 2Ch=29h 2Dh=04h
HDTOT 1688(698h) 2Eh=97h 2Fh=06h
VSEND 3 30h=02h 31h=00h
HSEND 112(70h) 32h=6Fh 33h=00h
VFST/VDST 41(29h) 24h/34h=28h 25h/35h=00h
HFST/HDST 360(168h) 26h/36h=67h 27h/37h=01h
VFEND/VDEND 1065(429h) 28h/38h=28h 29h/39h=04h
HFEND/HDEND 1640(668h) 2Ah/3Ah=67h 2Bh/3Bh=06h
DCLK 108 B0h=0Ch B1h=B0h
H Sync Polarity POSITIVE E4h bit 0 = 1
V Sync Polarity POSITIVE E4h bit 1 = 1
8
MX88L284-V
Revision: 1.0
De-Interlace Modes
Register 0x13/D[2:0] defines de-interlace mode when input image data is interlace. If input data is non-
interlace, all fields are written to frame memory and ignore these bits.
When odd de-interlace mode, only odd fields are written to frame memory.
When even de-interlace mode, only even fields are written to frame memory.
When odd/even de-interlace mode, odd and even fields are written to frame memory and composes to a
complete frame.
When toggle de-interlace mode, each fields are written to different frame memory. When reading from
frame memory, the source of display frame is toggled between two fields data which are in frame
memory.
When Motion-Adaptive de-interlace mode(0x13 D2=1), it only support YCbCr422 format data. The
maximum horizontal dot count of input is 768 dots, and please set register 0x14 as 10h. The VOP vertical
scaling factor is same as write frame model. And it doesn't support horizontal mirror.
Fig. 3