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TSC130BEF0
September
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2
2. Specifications
PIN Signal Designation Matching Value
1 Audio Out (linked with 3) 0.5Vrms, Imp < 1 k (RF 60% MOD)
2 Audio In (linked with 6) 0.5Vrms, Imp < 10 k
3 Audio Out (linked with 1) 0.5Vrms, Imp < 1 k (RF 60% MOD)
4 Audio Earth
5 Blue Earth
6 Audio in (linked with 2) 0.5Vrms, Imp < 10 k (RF 60% MOD)
7 Blue in 0.7Vpp + 2dB, Imp 75
-
8 Slow (Function) Switching TV : 0-2V, PERI : 9.5 - 12V, Imp > 10 k
9 Green Earth
10 NC
11 Green In 0.7Vpp + 2dB, Imp 75
-
12 NC
13 Red Earth
14 Rapid(Blanking) Switching Earth
15 Red In, C In 0.7Vpp + 2dB, Imp 75
-
16 Rapid(Blanking) switching Logic 0 : 0 - 0.4V, Logic 1 : 1 - 3V, Imp 75
17 Video Earth
18 Rapid Blanking Earth
19 Video Out 1Vpp + 2dB, Imp 75
-
20 Video In, Y In 1Vpp + 2dB, Imp 75
-
21 Common Earth
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3. Circuit Block Diagram
4
5. Alignment Instructions
4-1. User Remocon
RV-22D
TV..........................TXT TV..............................TXT
PR UP...............PAGE UP
VOLUME........VOLUME
DOWN DOWN VOLUME UP....VOLUME UP
(CURSOR (CURSOR
LEFT)
RIGHT)
MENU.................MENU
POWER...........POWER
NORMAL.................Not used
PR.......................PAGE
NUMBER NUMBER AV............................Not used
0-9 0-9
TXT...................................TV
SLEEP............Not used SOUND MODE.......Not used
MUTE..........................MUTE
Not used.........CANCEL Not used........................SIZE
Not used.............HOLD Not used........................SIZE
RECALL.......SUBPAGE ZOOM.....................Not used
STILL..............REVEAL EFFECT..................Not used
Not used.....................R Not used..............................C
Not used....................G Not used..............................Y
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6
7
Alignment Instructions
4-6-3 VERTICAL SIZE
* The VERTICAL CENTER adjustment has to be done in advance.
1) Apply a RETMA PATTERN Signal.
2) Set the TV to Normal I mode.
3) Adjust the VERTICAL SIZE of the picture with the select V.size by
volume UP/DOWN keys.
4-6-4 VERTICAL S-CORRECTION ( Fixed : Adjust if need be )
1) Apply a CROSSHATCH PATTERN Signal.
2) Adjust the S-CORRECTION to obtain the same distance between
horizontal lines with the S.Curve by volume UP/DOWN keys.
4-6-5 HORIZONTAL CENTER
1) Apply a RETMA PATTERN Signal.
2) Adjust picture centering with the select H.Center by volume UP/DOWN keys.
4-7. EW
4-7-1 WIDTH
1) Apply a RETMA PATTERN Signal.
2) Adjust the horizontal width to make a perfect circle with the select H.Width
by volume UP/DOWN keys.
4-7-2 PARA
1) Apply a CROSSHATCH PATTERN Signal.
2) Adjust the vertical line to straight with the select E.W Para by volume
UP/DOWN keys.
4-7-3 CORNER ( Fixed : Adjust if need be )
1) Apply a CROSSHATCH PATTERN Signal.
2) Adjust the vertical line to straight with the select EW.Cor T by volume
UP/DOWN keys.
4-7-4 SYMMETRY ( Fixed : Adjust if need be )
1) Apply a CROSSHATCH PATTERN Signal.
2) Turn R451 to the maximum left.
3) Adjust the symmetrical balance to be suitable with the select EW Sym by
volume UP/DOWN keys.
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Alignment Instructions
4-8. WHITE BALANCE
4-8-1 RGB Reference R
2
4-8-2 Beam Reference LOW ( 288, 301 : 10Cd/ m )
2
HIGH ( 288, 301 : 10Cd/ m )
4-8-3 Adjust G, B Gain with select Menu G,B of BIAS, DRIVE of select Menu so that R, G, B Bars
are on the center position of the analog meter. If R Analog meter is not on center, control
the Brightness +/- of user Remocon so as R Analog meter to be on the center position.
4-9. SUB BRIGHT
4-9-1 Pattern : Retma
4-9-2 Adjust the SUB BRIGHT with the select Sub Bri by volume UP/DOWN keys.
so that only H-Center parts of picture can be seen.
4-10. DOUBLE TEXT CENTER
4-10-1 Pattern : Pattern RED
4-10-2 Select Menu
4-10-3 Select DT in SVC menu time to see the Double Text Picture.
( Left : RF Picture, Right : Text Picture )
4-10-4 Change the Double Text control keys volume UP/DOWN keys so that the left edge of text
picture concur with the right edge of RF picture.
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5. IC description
5-1. ST92195
(1) General Description
1.1 INTRODUCTION ports enter high impedance mode. A reset is necessary to
The ST92195 microcnontoller is developed and manufac- exit from Halt mode.
tured by STMicroelecrtonics using a proprietary n-well 1.1.3 I/O Ports
HCMOS process. Its performance derives from the use of Up to 28 I/O lines are dedicated to digital Input/Output.
a flexible 256-register programming model for ultra-fast These lines are grouped into up to five I/O Ports and can
context switching and real-time event response. The intel- be configureed on a bit basis under software control to pro-
ligent onchip peripherals offload the ST9 core from I/O vide timing, status signals, timer and output, analog inputs,
and data management processing tasks allowing critical external interrupts and serial or parallel I/O.
application tasks to get the maximum use off core 1.1.4 TV Peripherals
resources. The ST92195 MCU supports low power con- A set of on-chip peripherals form a complete system for TV
sumption and low voltage operation for power-efficient set and VCR applications:
and low-cost embedded systems. - Voltage Synthesis
1.1.1 ST9+Core - VPS/WSS Slicer
The advanced Core consists of the Central Processing - Teletext Slicer
Unit (CPU), the Register File and the Interrupt controller. - Teletext Display RAM
The general-purpose registers can be used as accumula- - OSD
tor, Index register, or address pointers. Adjacent register 1.1.5 On Screen Display
pairs make up 16-bit registers for addressing or 16-bit The human interface is provided by the On Screen Display
processing. Although the ST9 has an 8-bit ALU, the chip module, this can produce up to 26 lines of up to 80 charac-
handles 16-bit operations, including arithmetic, loads/ ters from a ROM defined 512 character set. The character
stores, and memory/register and memory/memory resolution is 10x10 dot. Four character sizes are sup-
exchanges. Two basic memory spaces are available : ported. Serial attributes allow the user to select foreground
Program Memory and the Register File, Which includes and background. Parallel attributes can be used to select
the control and status registers of the on-chip peripherals. additional foreground and background colors and underline
1.1.2 Power Saving Modes on a character by character basis.
To optimize performance versus power consumption, a 1.1.6 Teletext and Display RAM
range of operating modes can be dynamically selected. The internal 8k Teletext and Display storage RAM can be
Run Mode. This is the full speed execution mode with used to store Teletext pages as well as Display parame-
CPU and peripherals running at the maximum clock ters.
speed delivered by the phase Locked Loop(PLL) of the 1.1.7 Teletext, VPS and WSS Data Slicers
Clock Control Unit(CCU). The three on-board data slicers using a single external
Wait For Interrupt Mode. The Wait For Inter- crystal are used to extract the Teletext, VPS and WSS
rupt(WFI) instruction suspends program execution until information from the video signal. Hardware Hamming
an interrupt request is acknowledged. During WFI, the decoding is provided.
CPU clock is halted while the peripheral and interrupt 1.1.8 Voltage Synthesis Tuning Control
controller keep running at a frequency programmable via 14-bit Voltage Synthesis using the PWM (Pulse Width
the CCU. In this mode, the power consumption of the Modulation)/BRM (Bit Rate Modulation) technique can be
device can be reduced by more than 95%(LP WFI). used to genetate tuning voltages for TV set applications.
The tuning voltage is output on one of two separate output
Wait For Interrupt Mode. The Wait For Inter-
pins.
rupt(WFI) instruction, and if the Watchdog is not enable,
the CPU and its peripherals stop operation and the I/O
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IC description
1.1.9 PWM Output - Rounding, fringe, double width, double height,
Control of TV settings is able to be made with up to eight scrolling, cursor, full background colour,
8-bit PWM outputs, with a frequency maximum of semitransparent mode and reduced intensity colour
23,437Hz at 8-bit resolution(INTCLK=12 MHz). Low reso- supported
lutions with higher frequency operation can be pro- Teletext unit, including Data slicer, Acquisition Unit and
grammed. up to 8K Bytes RAM for Data Storage
1.1.10 Serial Peripheral Interface (SPI) VPS and Wode Screen Signalling slicer
The SPI bus is used to communicate with external Integrated Sync Extractor and Sync Controller
2
devices via the SPI, or I C bus communication stan- 14-bit Voltage Synthesis for tuning reference voltage
dards. The SPI uses one or two lines for serial data and a Up to 6 external interrupts plus 1 non-maskable inter-
synchronous clock signal. rupt
1.1.11 Standard Timer (STIM) 8x8-bit programmable PWM outputs with 5V open-
The Standard Timer includes a programmable 16-bit drain or push-pull capability
down counter and an associated 8-bit prescaler with Sin- 16-bit Watchdog timer with 8-bit prescale
gle and Continuous counting modes. 16-bit standard timer with 8-bit prescaler usable as a
1.1.12 Analog/Digital Converter (ADC) Watchdog timer
In addition there is a 3 channel Analog to Digital Con- 3-channel Analog-to-Digital converter ; 6-bit guaran-
verter with integral sample and hold, fast 5.7us conver- teed
sion timer and 6-bit guaranteed resolution. Rich instruction set and 14-Addressing modes
Versatile Development Tools, including Assembler,
(2) Feature Linker, C-compiler, Archiver, Source Level Debugger
Register File based 8/16 bit Core Architecture with and Hardware Emulators with Real-Time Operating
RUN, WFI, SLOW and HALT modes System available from third parties
O
0 C to 70O Coperating temperature range Piggyback board available for prototyping
Up to 24 MHz Operation @5V + 10% _
Minimum instruction cycle time : 375ns at 16MHz inter-
nal clock
64K Bytes ROM
256 Bytes RAM of Register file(accumulator or index
registers)
256 Bytes of on-chip static RAM
8K Bytes of TDSRAM(Teletext and Display RAM)
56-lead Shrink DIP package
28 fully programmable I/O pins
Serial Peripheral Interface
Flexible Clock controller for OSD, Data Slicer and Core
clocks running from one single low frequency external
crystal.
Enhanced Display Controller with 26 rows of 40/80
characters
- Serial and Parallel attributes
- 10x10 dot Matrix, 512 ROM characters, definable by
user
- 4/3 and 16/9 supported
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IC description
(3) Block Diagram
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IC description
(4) PIN DESCRIPTION
RESET Reset (input, active low). The ST9+ is initialised HYNC/CSYNC Horizontal/Composite sync. Horizontal
by the Reset signal. With the deactivation of RESET, or composite video synchronisation input to OSD. Posi-
program execution begins from the Program memory tive or negativety.
location pointed to by the vector contained in program PXFM Analog pin for the Display Pixel Frequency Multi-
memory locations 00h and 01h. plier
R/G/B Red/Green/Blue. Video color analog DAC out- AVDD Analog VDD of PLL. This pin must be tied to
puts VDD externally to the ST92195.
FB Fast Blanking. Video analog DAC output. GND Digital circuit ground.
VOD Main power supply voltage(5V 10%, digital) AGND Analog circuit ground(must be tied externally to
WSCF, WSCR Analog pins for the VPS/WPP slicer line digital GND).
PLL. CVBS1 Composite video input signal for the Teletext
MCFM Analog pin for the display pixel frequency multi- slicer and sync extraction.
plier. CVBS2 Composite video input signal for the VPS/WSS
OSCIN, OSCOUT Oscillator (input and output). slicer. Pin AC coupled.
These pins connect a parallel-resonant crystal(24MHz AVDD1, AVDD2 Analog power supplies(must be tied
maximum), or an external source to the on-chip clock externally to AVDD).
oscillator and buffer. OSCIN is the input of the oscilltor TXCF Analog pin for the VPS/WSS line PLL.
inverter and internal clock generator; OSCOUT is the CVBSO, JTDO, JTCK Test pins : leave floating.
output of the oscillator inverter. JTMS, TEST0 Test pins : must be tied to AVDD2.
VSYNC Vertical Sync. Vertical video synchronisation JTRST0 Test pin : must be tied to GND.
input to OSD. Positive or negative polarity.
Figure 2. Pin Description
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IC description
5-2. VPS 3215C(Video Processor)
(1) Description including all substandards
The VPC 3215C is a high-quality, single-chip video front- - 1 composite, 1 S-VHS input, 1 composite output
end, which is targeted for 4:3 and 16:9, 100/120Hz TV - integrated high-quality A/D converters and associated
sets. clamp and AGC circuits
It can be conbined with other members of the DIGIT3000 - multi-standard sync processing
IC family (such as CIP 3250A, DDP 3300A, TPU 3040) - linear horizontal scaling (0.25 ... 4), as well as non-linear
and/or it can be used with 3rd-party products. horizontal scaling panorama vision
- PAL + preprocessing (VPC 3215)
(2) Features
- all-digital video processing - submicron CMOS technology
- high-performance adaptive 4H comb filter Y/C separator
with adjustable vertical peaking
- multi-standard color decoder PAL/NTSC/SECAM
(3) Block Diagram
(4) Pin Descriptions
Pin 1 - Ground, Analog Front-End GND F
These pins are connected to an 20.25MHz crystal oscilla-
Pin 2 - Ground, Analog Front-End GND F tor which is digitally tuned by integrated shunt capaci-
Pin 3 - CCU 5 MHz Clock Output CLK5 tances. The CLK20 and CLK5 clock signals are derived
This pin provides a clock frequency for the TV microcon- from this oscillator. An external clock can be fed into
troller, e.g. a CCU 3000 controller, It is also used by the XTAL1. In this case, clock frequency adjustment must be
DDP 3300A display controller as a standby clock. switched off.
Pin 4 - Standby Supply Voltage V STDBY Pin 7 - Ground, Analog Front-End GND F
In standby mode, only the clock oscillator is active, GND F Pin 9 - Ground, Output Pad Circuitry GND P
should be ground reference. Please activate RESQ before Pin 10 - Interlace Output, INTLC
powering-up other supplies Pins 6 and 5-XTAL1 Crystal This pin supplies the interlace information, 0 indicates first
Input field, 1 indicates second field.
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IC description
Pin 12 - Vertical Sync Pulse, VS Pin 52 - VGAV-Input.
This pin supplies the vertical sync signal. This pin is connected to the vertical sync signal of a VGA
Pin 13 - Front Sync Pulse, FSY signal.
This pin supplies the front sync information. Pin 53 - Front-End/Back-End Data FPDAT
Pin 14 - Main Sync/Horizontal Sync Pulse MSY/HS This pin interfaces to the DDP 3300A back-end processor.
This pin supplies the horizontal sync pulse information in The information for the deflection drives and for the white
line-locked mode. In DIGIT3000 mode, this pin is the main drive control, i.e. the beam current limiter, is transmitted by
sync input. this pin.
Pin 15 - Helper Line Output, Helper Pin 54 - Reset Input RESQ
This signal indicated a helper line in PAL + mode. A low level on this pin resets the VPC 32xx.
2
Pin 16 - Horizontal Clamp Pulse, HC Pin 55 - I C Bus Data SDA
2
This signal can be used to clamp an external video signal, The pin connects to the I C bus data line.
that is synchronous to the input signal. The timing is pro- Pin 57 - Test Input TEST
grammable. This pin enables factory test modes. For normal operation,
Pin 17 - Active Video Output, AVO it must be connected to ground.
This pin indicates the active video output data. The signal Pin 59 - Ground, Analog Front-End GND
is clocked with the LLC1 clock. Pins 62,61,60,58 - Video 1-4
Pin 18 - Double Output Clock, LLC2 These are the analog video inputs. A CVBS or S-VHS
Pin 19 - Output Clock, LLC1 luma signal is converted using the luma (Video 1) AD con-
This is the clock reference for the luma, chroma, and sta- verter. The VIN1 input can also be switched to the chroma
tus outputs. (Video 2) ADC. The input signal must be AC-coupled.
Pin 26 - Ground, Output Pad Circuitry GND P Pin 63 - Chroma Input CIN
Pin 20 to 25,28,29 - Luma Output Y0-Y7 This pin is connected to the S-VHS chroma signal. A resis-
These output pins carry the digital luminance data. The tive divider is used to bias the input signal to the middle of
data are clocked with the LLC1 clock. the converter input range. CIN can only be connected to
Pin 30 - Main Clock Output CLK20 the chroma (Video 2) A/D converter. The signal must be
This is the 20.25MHz main clock output. AC-coupled.
Pin 31 - Supply Voltage, Digital Circuitry V SUPD Pin 64 - Analog Video Output, VOUT
Pin 34 - Ground, Digital Circuitry GND D The analog video signal that is selected for the main
Pin 35 - Ground, Output Pad Circuitry GND P (luma, CVBS) ADC is output at this pin. An emitter follower
Pin 36 - Supply Voltage, Output Pad Supply V SUPP is required at this pin.
Pin 38 to 43,46,47 - Chroma Outputs C0-C7 Pin 65 - Ground, Analog Shield Front-End GND
These outputs carry the digital CrCb chrominance data. Pin 66 - Supply Voltage, Analog Front-End V
The data are clocked with the LL1 clock. The data are Pin 67 - Signal GND for Analog Input ISGND
sampled at half the clock rate and multiplexed. The CrCb This is the high quality ground reference for the video
multiplex is reset for each TV line. input signals.
Pin 48 to 50 - Picture Bus Priority PR0-PR2 Pin 68 - Reference Voltage Top VRT
The Picture Bus Priority lines carry the digital priority Via this pin, the reference voltage for the A/D converters is
selection signals. The priority interface allows digital decoupled. The pin is connected with 10uF/47nF to the
switching of up to 8 sources to the back-end processor. Signal Ground Pin.
Switching for different sources is prioritized and can be on
a per pixel basis.
Pin 51 - Ground, Output Pad Circuitry GND P
15
IC description
5-3. CIP3250A (Component Interface Processor)
(1) Description - digital matrix RGB => YUV (Y, B-Y, R-Y)
The CIP 3250A is a new CMOS IC that contains on a sin- - luma contrast and brightness correction for signals from
gle chip the entire circuitry to interface analog YUV/RGB/ analog input
Fast Blank to a digital YUV system. The Fast Blank signal - color saturation and hue correction for signals from
is used to control a soft mixer between the digitized RGB analog input
and an external digital YUV source. The CIP supports var- - digital input for DIGIT 2000 or DIGIT 3000 formats
ious output formats such as YUV 4:1:1/4:2:2 or RGB 4:4:4. - digital interpolation to 4:4:4 format
- high quality soft mixer controlled by Fast Blank signal
Together with the DIGIT 3000 (e.g. VPC 32xxA) or DIGIT - programmable delays to match digital YUV in and analog
2000 (e.g. DTI 2250), an interface to a TV-scanrate con- RGB/YUV
version circuit and/or multi-media frame buffer can be - variable low pass filters for YUV output
obtained. - digital output in DIGIT 2000 and DIGIT 3000 formats, as
well as RGB 4:4:4
2
(2) Feature - I C bus interface
- analog input for RGB or YUV and Fast Blank - clock frequency 13.5...20.25 MHz
- triple 8 bit analog to digital converters for RGB/YUV with
internal programmable clamping
- single 6 bit analog to digital converter for Fast Blank
singnal
(3) Block Diagram
16
IC description
(4) Pin Description nal(pure binary) or the digital chroma V signal (2 s compo-
Pin 1 - STANDBY Input nent). Leave vacant if not used.
Via this input pin, the standby mode of the CIP 3250A is
enabled. A high level voltage switches all outputs to Pin 29 - AVI Active Video Input
tristate mode, and power consumption is signigicantly In a DIGIT 2000 application, this input can be connected
reduced. When the IC IS returned to active mode, a reset to ground. In a DIGIT 3000 application, this input expects
is generated internally. Connect to VSS if not used. the DIGIT 3000 AVI signal. In a stand alone application,
this input expects the VSYNC vertical sync pulse. Connect
Pins 2 to 9 - B7 to B0 Blue Output ground if not used.
In a stand alone application, where the CIP 3250A serces
as an A/D-converter, these are the output for the digital Pin 30 - FSY Front Sync Input
Blue signal (pure binary) or the digital U signal (2s com- In a DIGIT 2000 application, this input pin expects the
plement). Leave vacant if not used. DIGIT 2000 SKEW protocol. In a DIGIT 3000 application,
this input expects the DIGIT 3000 FSY protocol. In a stand
Pin 10 to 17 - GL7 to GL0 Green/Luma Output alone application, this unput expects the HSYNC horizon-
At these outputs, the digital luminance signal is received in tal sync pulse. Connect to ground if not used.
pure binary cided format for DIGIT 2000 and DIGIT 3000
2
applications. In a stand alone application, where the CIP Pin 31 to 32 - SDA and SCL of I C-Bus
2
3250A serves as an A/D-converter, these are the outputs These pins connect to the I Cbus, which takes over the
for the digital Green signal(pure binary) or the digital luma control of the CIP 3250A via the internal registers. The
signal(pure binary). Leave vacant if not used. SDA pin is the data input/output, and the SCL pin is the
2
clock input/output of I Cbus control interface. All registers
Pin 18 - PVSS Output Pin Ground are writerable(except address hex27) and readable.
This is the common ground connection of all output stages
and must be connected to ground. Pin 33 to 35 - PRIO0 to PRIO2 Priority Bus
Note : All ground pins of the chip (i.e. These pins connect to the Priority Bus of a DIGIT 3000
18,52,58,60,62,64,66 and 68) must be connected together application. The Picture Bus Priority lines carry the digital
low resistive. The layout of the PCB must take into consid- priority selection signals. The priority interface allows digi-
eration the need for a low-noise ground. tal switching of up to 8 sources to the backend processor.
Switching for different sources is prioritized and can be on
Pin 19 - PVDD Output Pin Supply + 5V/+3.3V a per pixel basis. In all other applications, they must not be
This pin supplies all output stages and must be connected connected.
to a positive supply voltage.
Note : The layout of the PCB must take into consideration Pin 36 to 43 - C0 to C7 Chroma Input
the need for a low-noise supply. A bypass capacitor has to These are the inputs for the digital chroma signal which
be connected between ground and PVDD can be received in binary offset or 2 s complement coded
format. In a DIGIT 2000(4:1:1) system, C3 to C0 take the
Pins 20 to 27 - RC7 to RC0 Red/Chroma Output halfbyte (nibble) multiplex format. C7 to C4 have to be
These are the outputs for the digital chroma signal in the connected to ground. Within the DIGIT 3000(4:2:2) sys-
DIGIT 3000 system, where U and V are multiplexed byte- tem, U and V are multiplexed bytewise. Connect to ground
wise. In a DIGIT 2000 system, RC3 to RC0 and RC7 to if not used.
RC4 carry the halfbyte(nibble) multiplex format. In a stand
alone application, where the CIP 3250A serces as an AD-
converter, these are the outputs for the digital Red sig-
17
IC description
Pin 44 to 51 - L0 to L7 Luma Input 66, and 68) must be connected together low resistive. The
These are the inputs for the digital luma signal which must layout of the PCB must take into consideration the need
be in pure binary coded format. Connect to ground if not for a low-noise ground.
used.
Pin 59 - ADREF Connect External Capacitor
Pin 52 - DVSS Digital Ground This pin should be connected to ground over a 10uF and a
This is the common ground connection of all digital stages 100nF capacitor in parallel.
and must be connected to ground.
Note : All ground pins of the chip(i.e. 18, 52, 58, 60, 62, Pin 60 - SUBSTRATE
64, 66, and 68) must be connected together low resistive. This is connected to the platform which carries the die
The layout of the PCB must take into consideration the and must be cvonnected to the ground.
need for a low-noise ground. Note : All ground pins of the chip(i.e.
18,52,58,60,62,64,66, and 68) must be connected
Pin 53 - DVDD Digital Supply +5V together low resistive. The layout of the PCB must take
This pin supplies all digital stages and must be connected into consideration the need for a low-noise ground.
to a positive supply voltage.
Note : The layout of the PCB must take into consideration Pin 61 - FB Analog Fast Blank Input
the need for a low-noise supply. A bypass capacitor has to This input takes the DC-coupled analog Fast Blank signal.
be connected between ground and DVDD. The amplitude is 1.0V maximum at 75 Ohms. Connect to
ground if not used.
Pin 54 - CLK Main Clock Input
This is the input for the clock signal. The frequency and Pin 62 - GNDFB Analod Ground
vary in the range from 13.5MHz to 20.25MHz. This is the ground pin for the AD converter of the Fast
Blank signal and has to be connected to ground.
Pin 55 - RESQ Input Note : All ground pins of the chip (i.e. 18,52,58,60,62,64,
A low signal at this input pin generates a reset. The low-to- 62,64,66 and 68) must be connected together low resis-
high transition of this signal should occur when the supply tive. The layout of the PCB must take into consideration
voltage is stable(power-on reset). the need for a low-noise ground.
Pin 56 - TMODE Input Pin 63 - BU Analog Blue/U Chroma Input
This pin is for test purposes only and must be connected The input pin takes the AC-coupled analog compont signal
to ground in normal operation. Blue or U Chroma. The amplitude is 1.0V maximum at 75
Ohms and a coupling capacitor of 220 nF. Internally, the
Pin 57 - AVDD Analog Supply +5V DC-offset of the input signal is adjusted via the program-
This is the supply voltage pin for the A/D converters and mable internal clamping circuit. Connect to ground if not
must be connected to a positive supply voltage. used.
Note : The layout of the PCB must take into consideration
the need for a low-noise supply. A bypass capacitor has to Pin 64 - GNDBU Analog Ground
be connected between ground and AVDD. This is the ground pin for the A/D converter of the Blue or
U Chroma signal and must be connected to ground.
Pin 58 - AVSS Analog Ground Note : All ground pins of the chip(i.e.
This is the ground pin for the A/D converters and must be 18,52,58,60,62,64,66, and 68) must be connected
connected to ground. together low resistive. The layout of the PCB must take
Note : All ground pins of the chip (i.e. 18,52,58,60,62,64, into consideration the need for a low-noise ground.
18
IC description
Pin 65 - GY Analog Green/Luma Input
This input pin takes the AC-coupled analog compinent sig-
nal Green or Luma. The amplitude is 1.0V maximum at 75
Ohms and a couplign capacitor of 220nF. Internally, the
DC-offset of the input signal is adjusted via the program-
mable internal clamping circuit. Connect to ground if not
used.
Pin 66 - GNDGY Analog Ground
This is the ground pin for the A/D converter of the Green
or Luma signal and must be connected to ground.
Note : All ground pins of the chip(i.e. 18,52,58,60,62,64,
66, and 68) must be connected together low rresistive.
The layout of the PCB must take into consideration the
need for a low-noise ground.
Pin 67 - RV Analog Red/V Chroma Input
This input pin takes the AC-coupled analog component
signal Red or V Chroma. The amplitude is 1.0V maximum
at 75ohms and a coupling capacitor of 220nF. Internally,
the DC-offset of the input signal is adjusted via the pro-
grammable internal clamping circuit. Connect to ground if
not used.
Pin 68 - GNDRY Analog Ground
This is the ground pin for the A/D converter of the Red or V
Chroma signal and must be connected to ground.
Note : All ground pins of the chip (i.e. 18,52,58,62,64,66,
and 68) must be connected together low resistive. The lay-
out of the PCB must take into consideration the need for a
low-noise ground.
19
IC description
5-4. MSM5412222 ( 262, 214-Word X 12-Bit Field Memory )
(1) DESCRIPTION
The OKI MSM541222 is a high performance 3-Mbit, 256K x 12-bit, Field Memory. It is especially designed for
high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and
Multi-media systems. MSM541222 is a FRAM for wide or low or low end use in general commodity TVs and
VTRs exclusively. MSM5412222 is not designed for high end use in medical systems, professional graphics
systems which require long term picture storage, data storage systems and others. Two or more MSM541222s
can be cascaded directly without any delay devices between them. ( Cascading provides larger storage depth
or a longer delay ).
Each of the 12-bit planes has separate serial write and read ports. These employ independent control clocks to
support asynchronous read and write operations. Different clock rates are also supported, which allow alternate
data rates between write and read data streams.
The MSM5412222 provides high speed FIFO, First-In First-Out, operation without external refreshing:
MSM5412222 refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access
operation, so that serial read and / or write control clock can be halted high or low for any duration as long as
the power is on. Internal conflicts of memory access and refreshing operations are prevented by special
arbitration logic.
The MSM5412222s function is simple, and similar to a digital delay device whose delay-bit-length is easily
set by reset timing. The delay length, and the number of read delay clocks between write and read, is
determined by externally controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256 x 12-bit enable high speed first-bit-
access with no clock delay just after the write of read reset timings.
Additionally, the MSM5412222 has a write mask function or input enable function (IE), and read-data skipping
function or output enable function (OE). The differences between write enable (WE) and input enable (IE), and
between read enable (RE) and output enable (OE) are that WE and RE can stop serial write / read address
increments, but IE and OE cannot stop the increment, when write / read clocking is continuously applied to
MSM5412222. The input enable (IE) function allows the user to write into selected locations of the memeory
only, leaving the reset of the memory contents unchanged. This facilitates data processing to display a
picture in picture on a TV screen.
The MSM5412222 is similar in operation and functionality to OKI 1-Mbit Field Memory MSM514222B and
2-Mbit Field Memory MSM518222. Three MSM514222Bs or one MSM514222B plus one MSM518222 can
be replaced simply by one MSM5412222.
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IC description
(2) FEATURES
Single power supply : 5V 10%
512 Rows x 512 Columns x 12 bits
Fast FIFO (First-In First-Out) operation
High speed asynchronous serial access
Read / write cycle time 25 ns / 30 ns
Access time 23 ns / 25 ns
Direct cascading capability
Write mask function (Input enable control)
Data skipping function (Output enable control)
Self refresh (No refresh control is required)
(3) BLOCK DIAGRAM
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IC description
(4) Pin Description
Pin No. Pin Name Function
17 SWCK Serial Write Clock
28 SRCK Serial Read Clock
20 WE Write Enable
25 RE Read Enable
21 IE Input Enable
24 OE Output Enable
18 RSTW Write Resert Clock
27 RSTR Read Reset Clock
2,3,5,6,7,8,10,11,12,13,15,16 D IN0 ~ D IN11 Data Input
29,30,32,33,34,35,37,38,39,40,42,43 D OUT 0 ~ D OUT11 Data Output
22,23 Vcc Power Supply (5V)
1,31,44 Vss Ground (0V)
4,9,14,19,26,36,41 NC No Connection
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IC description
5-5. DDP 3310B (Display and Deflection Processor)
(1) Description Deflection processing
The DDP 3310B is a single-chip digital Display and Deflec- - scan velocity modulation output
tion Processor designed for high-quality backend applica- - high-performance H/V deflection
tions in 100/120MHz TV sets with 4:3- or 16:9 picture - EHT compensation for vertical / East/West
tubes. The IC can be combined with members of the - soft start/stop of H-Drive
DIGIT 3000 IC family (VPC 32xx, TPU 3040), or it can be - vertical angle and bow
used with third-party products. The IC contains the entire - differential vertical output
digital video component and deflection processing and all - horizontal and vertical protection circuit
analog interface components. - adjustable horizontal frequency for VGA/SVGA dislay
(2) Feature Miscellaneous
Video processing - selectable 4:1:1/4:2:2 YC rC b input
- linear horizontal scaling (0.25 ... 4) - selectable 27/32-MHz line-locked clock input
- non-linear horizontal scaling panoramavision - crystal oscillator for horizontal protection
- dynamic peaking - automatic picture tube adjustment(cutoff, whitedrive)
- soft limiter (gamma correction) - single 5-V power supply
- color transient improvement - hardware for simple 50/60-Hz to 100/120-Hz conversion
- programmable RGB matrix (display frequency doubling)
2
- picture frame generator - two I C -controlled PWM outputs
- two analog RGB/Fast-Blank inputs - beam current limiter
(3) Block Diagram
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IC description
(4) Pin Description The vertical protection circuitry prevents the picture tube
from burn-in in the event of a malfunction of the vertical
Pin 1 - Supply Voltage, Output Pin Driver VSUPP* deflection stage. If the peak-to-peak value of the vertical
This pin is used as supply for the following digital output sawtooth signal is too small, the RGB output signals are
pins : FIFORRD, FIFORD, FIFOWR, FIFORWR. blanked.
Pin 2 - Ground, Output Pin Driver GNDP* Pin 12 - H-Drive Frequency Range Select FREQSEL
Output Pin Driver Reference This pin selects the frequency range for the horizontal
drive signal.
Pin 3 - Sync Signal Input VS2
2
Additional pin for the vertical sync information. Via I C Pin 13 - Clock Select 40.5 or 27/32 MHzCM1
Register the used vertical sync can be switched between Low level selects 27/32 MHz, High level selects 40.5 MHz
the inputs VS2 and VS(Pin 64)
Pin 14 - Clock Select 40.5 or 27/32 MHzCM0
Pin 4 - Reset for FIFO Read Counter FIFORRD Low level selects 27 MHz, High level selects 32 MHz
This signal is active-High and resets the read counter in
Pin 15 - Range Switch2 for Measuring ADC RSW2
the display frequency doubling FIFO.
This pin is an open-drain pull-down output. During cutoff
measurement the switch is off. During white drive mea-
Pin 5 - Read Enable for FIFO FIFORD
surement the switch is on. Also during the rest of time it is
This signal is active-High and enabels the read counter in
on.
the display frequency doubling FIFO.
Pin 16 - Range Switch 1 or Second Input for Measuring
Pin 6 - Write Enable for FIFO FIFOWR ADC RSW1
This signal is active-High and enables the write counter in This pin is an open-drain pull-down output. During cutoff
the display frequency doubling FIFO. and white-drive measurement, the switch is off. During
the rest of time it is on. The RSW1 pin can be used as
second measurement ADC input.
Pin 7 - Reset for FIFO Write Counter FIFOWR
This signal is active-High and enables the write counter in
Pin 17 - Measurement ADC Input SENSE
the display frequency doubling FIFO.
This is the input of the analog to digital converter for the
picture and tube measurement. Three measurement
Pin 8 - Horizontal Drive HOUT ranges are selectable with RSW1 and RSW2
This open-drain output supplies the drive pulse for the hor-
izontal output stage. A pull-up resistor has to be used. Pin 18 - Measurement ADC Reference Input MGND
This is the ground reference for the measurement A/D
converter.
Pin 9 - Horizontal Flyback Input HFLB
Via this pin, the horizontal flyback pulse is supplied to the
Pin 19 - Vertical Sawtooth Output VERT+(19)
DDP 3310B.
This pin supplies the drive signal for the vertical output
stage. The drive signal is generated with 15-bit precision.
Pin 10 - Safety Input SAFETY
The analog voltage is generated by a 4-bit current DAC
This input has two thresholds. A signal between the lower
with external resistor (6 k for proper operation) and
and upper threshold means normal function. Other signals uses digital noise-shaping.
are detected as malfunction.
Pin 20 - Vertical Sawtooth Output inverted VERT-
Pin 11 - Vertical Protection Input VPROT This pin supplies the inverted signal of VERT+.
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IC description
Together with this pin, it can be used to drive symmetrical These pins are used to switch the RGB outputs to the
deflection amplifiers. external analog RGB inputs. FBLIN1 switches the RIN1,
GIN1 and BIN1 inputs, FBLIN2 switches the RIN2, GIN2
Pin 21 - East/West Parabola Output EW and BIN2 inputs. The active level (Low or High) can be
This pin supplies the parabola signal for the East/West selected by software.
correction. The drive signal is generated with 15-bit preci-
sion. The analog voltage is generated by a 4-bit current Pin 31, 32, 33 - Analog RGB Input1 RIN1, GIN1, BIN1
DAC with external resistor and uses digital noise-shaping. These pin are used to insert an external analog RGB sig-
nal, e.g. from a SCART connector which can by switched
Pin 22 - DAC Current Reference XREF to the analog RGB outputs with the Fast-Blank signal.
External reference resistor for DAC output currents, typical The analog back-end provides separate brightness and
10 k