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RXQB
RXQA Pages 16-18 WSTR
WSTR_15
RXIB WDAT
WDAT
RXIA VDIG WCLK
WCLK
IDATA VDDE18 TXQB
TXQB
QDATA TXQA
TXQA
DCLK TXIA
TXIA
TESTOUT RXQB TXIB
TXIB
VCAM18 VCAM12 RXQA RADSTR
RADSTR
RXIB RADDAT
Pages 19-23 RADDAT
RXIA RADCLK
VBATI RADCLK
IDATA TXON
VDIG TXON
QDATA MODA
VCAM27 MODA
DCLK MODB
VCAM12 MODB
TESTOUT MODC
VCAM18 MODC
MODD
VDDE18 MODD
ANTSW0
Pages 10-15 ANTSW0
VBATI ANTSW1
ANTSW1
ANTSW2
ANTSW2
ANTSW3
VBATI ANTSW3_1V8
VDIG
UMTS Access
VDDE18
MPX1_OFF PCMDATA
VMSPICO MPX1_OFF MPX1_OFF PCMDATA
VGA_OFF PCMDATB
VBACKUP VGA_OFF VGA_OFF PCMDATB
KBDIM PCMSYN
KBDIM KBDIM PCMSYN
NAVDIM PCMCLK
NAVDIM NAVDIM PCMCLK
DCDC_PA DCDC_PA AMPCTRL AMPCTRL
DCDC_PA
WPAVDC WPAVDC VAD
WPAVDC MICN/AUXinR
MICN/AUXinR
FLASH_STROBE
MICP/AUXinL MICP/AUXinL
VLOOP
VLOOP I2CDAT1
RTEMP I2CDAT1 I2CDAT1
RTEMP I2CCLK1
WRFLOOP I2CCLK1 I2CCLK1
WRFLOOP SPL
CAMSYSCLK
BTCLKREQ SPR
BTCLKREQ BTTX
BTRX MIDREF
BTRX BTRTS
BTCTS DCIOint ONSWA
BTCTS WPABIAS
VCXOCONT MMI
MEMRESn
BTTX
VPP
BTRTS
VAD VBUS
WPABIAS
FLASH_STROBE DCIO
VCXOCONT
DCIO_ON
SPL VBT_EN
SPR CAM_27_EN
VccB VccA VAPC
MIDREF SERVICEn
ANTSW3
ANTSW3_1V8 ANTSW3
WSTR VBATI
WSTR_15 WSTR
VDIG
Operation & Services VRTC13
WSTR_15
VBT27
ANTSW3_1V8
VDDE18
VAPC
VccA
VccB
BTRESn
RTCCLK
VCAM18 VccA
VCAM12 VccB
Pages 5-9
VBATI
VDIG
XTLDO XTLDO
VBT27
VAPC VAPC
VDDE18
VBACKUP
Pages 2-4 VCAM27
VDDE18 VCAM12
VCORE15 VCAM18
Confidential
VPP
VMSPICO
Approved according to 00021-LXE 107 42/1 SCHEMA DIAGRAM
MEMRESn VBUS
VccA
CLKREQ
CLKREQ BTRESn DCIO Sony Ericsson SEMCJ/ Kensuke Katsuta
MCLK VccB
MCLK DCIO_ON
DCIOint
SERVICEn RTCCLK VBT_EN BASEBAND SEMCJ/ Ken Ikuno 2006/12/14 E
VRTC13
ONSWAn CAMSYSCLK CAM_27_EN
VCORE15 Logic Top Ai Main Board
System Control XTLDO
VAPC
2/1911-ROA 128 2071/2 01 of 23
Power
VDDE18 VCORE15 VCORE15 VDDE18
Page 3
RTCCLK
VDDE18 VDDE18 RTCCLK RTCCLK
VCORE15 VCORE15
CAMSYSCLK
CAMSYSCLK CAMSYSCLK
CLKREQ
CLKREQ CLKREQ
MCLK
MCLK MCLK
SERVICEn MEMRESn
SERVICEn SERVICEn MEMRESn MEMRESn
ONSWAn BTRESn
ONSWAn ONSWAn BTRESn BTRESn
Clocks & Resets
Page 4
Test
Confidential
Approved according to 00021-LXE 107 42/1 SCHEMA DIAGRAM
Sony Ericsson SEMCJ/ Zhang Zongyao
SEMCJ/ Ken Ikuno 2006/12/14 E
BASEBAND
System Control Ai Main Board
Top
2/1911-ROA 128 2071/2 02 of 23
B2100
RTM501911/2
R1A
C1 C2
C2102 32768k C2103
22pF
27pF
Connect to ground plane in one single point
D2000 Use for
dumping resister
RTC 47ohm
V2 T2 R2100 R2105
RTCIN RTCOUT
0ohms 10Kohms
RTCCLK W4 RTCCLK
RTCCLK
C2104 & C2106 mounted close to D2000 V3 Y4
RTCBDIS_N RTCDCON
C2104 Resets
W3 RESPOW_N RESOUT0_N E16 MEMRESn
1nF MEMRESn
RESOUT1_N Y6
RESOUT2_N D16 BTRESn
BTRESn
C2100
1nF Clocks
T8 MCLK_M SYSCLK0 AB6
C2106
NM SYSCLK1 AC6 CAMSYSCLK
CAMSYSCLK
10pF Y7
SYSCLK2 R2104
VDDE18
47ohms
Control
E15 IRQ0_N R2104 mounted
PWRREQ0_N AC5
close to D2000
Actual net on system D15 IRQ1_N PWRREQ1 AB5
connector page...
SERVICEn C16 SERVICE_N
SERVICEn
CLKREQ_1 AA6 CLKREQ
CLKREQ
R2102
100ohms DB2030
ROP1013112/1 R1A (REQ3234U)
PWR_IRQ
PWRRST
D2000
V21 CLK32
MCLK_WANDA U9 MCLK_W
U3 HCLK
C2101
VCORE15
1nF
DB2030
ROP1013112/1
RTCCLK_1
R2101
100Kohms
N2000
ERICSSON AB 2010
SYSTEM CONTROL
POWER ON/RESET
ONSWAn ONSWAn C4 B8
ONSWAn ONSWA PWRRST
C5 C1
ONSWB IRQ
RTCDCON A7
ONSWC
CONTROL
PWRREQn C10
SLEEP
CLKREQ_1 K3
CLKREQ
MCLK K9
MCLK MCLK
RTCCLK_1 M1
XTAL1
ERICSSON_AB2012
ROP1013066/6 R1A
Confidential
Approved according to 00021-LXE 107 42/1 SCHEMA DIAGRAM
VDDE18 VCORE15
Sony Ericsson SEMCJ/ Zhang Zongyao
SEMCJ/ Ken Ikuno 2006/12/14 E
BASEBAND
VDDE18
VCORE15
System Control Ai Main Board
Clocks & Resets
2/1911-ROA 128 2071/2 03 of 23
D2000
D2000 D2000
JTAG_IF
GPO0 T10 J16 EMIF_D0 EMIF_AWE T4
AC7 TDI_M TDO_M Y8
GPO1 U4 H16 EMIF_D1 EMIF_ARE M9
AB7 TMS_M RTCK_M AB8
GPO2 P12 K15 EMIF_D2 EMIF_ARE_ADY K8
AA7 TCK_M TEMU0_N_M AD8
GPO3 R12 J15 EMIF_D3 EMIF_A1 R16
AA8 TRST_N_M TEMU1_N_M Y9
GPO4 T12 M14 EMIF_D4 EMIF_A2 R15
ETM_IF
GPO5 P11 L14 EMIF_D5 EMIF_A3 R14
ETMPSTAT0 AB11
GPO6 U14 K14 EMIF_D6 EMIF_A4 R13
ETMPSTAT1 AC10
GPO7 T13 J14 EMIF_D7 EMIF_A5 R17
ETMPSTAT2 Y12
D22 UART_RX UART_TX E22 H14 EMIF_D8 EMIF_A6 P16
ETMSYNC AA12
DSPINTERRUPT M13 EMIF_D9 EMIF_A7 P15
ETMCLK AB12
CPU_IACK N10 L13 EMIF_D10 EMIF_A8 P14
ETMPKT0 AC12
CPU_XF P9 K13 EMIF_D11 EMIF_A9 P13
ETMPKT1 AA13
CPU_IRQ1 H4 J13 EMIF_D12 EMIF_A10 N17
ETMPKT2 AB13
CPU_IRQ0 H3 M12 EMIF_D13 EMIF_A11 N16
ETMPKT3 AC13
CPU_CLKOUT T11 L12 EMIF_D14 EMIF_A12 N15
ETMPKT4 Y14
K12 EMIF_D15 EMIF_A13 N14
ETMPKT5 AA14 DB2030
ROP1013112/1 J12 EMIF_D16 EMIF_A14 N13
ETMPKT6 AB14
H12 EMIF_D17 EMIF_A15 M16
ETMPKT7 AC14
M11 EMIF_D18 EMIF_A16 M15
DB2030 L11 EMIF_D19 EMIF_A17 L17
ROP1013112/1
D2000 K11 EMIF_D20 EMIF_A18 L16
L20 TDI_W TDO_W K20 J11 EMIF_D21 EMIF_A19 L15
M20 TMS_W N12 EMIF_D22 EMIF_A20 A23
P21 TRST_N_W EMU0_W G20 M10 EMIF_D23 EMIF_A21 K17
N20 TCK_W EMU1_W H20 L10 EMIF_D24 EMIF_A22 B24
K10 EMIF_D25 EMIF_A23 K16
DB2030
ROP1013112/1 J10 EMIF_D26
H10 EMIF_D27
N11 EMIF_D28
L9 EMIF_D29
D2000 K9 EMIF_D30
U12 BOOTMODE0 J9 EMIF_D31
R11 BOOTMODE1
U15 BOOTMODE2 EXT_MEM_UBUS10 P10
F20 BOOTMODE3 EXT_MEM_UBUS11 R10
AD23 TESTMODE EXT_MEM_UBUS12 R9
T14 ANALOG_ENABLE EXT_FRZME_STOROBE J20
T15 APLL_BYPASS
DB2030
T16 CS_BYPASS ROP1013112/1
APLL_ATEST1 N9
DB2030
ROP1013112/1
Confidential
Approved according to 00021-LXE 107 42/1 SCHEMA DIAGRAM
Sony Ericsson SEMCJ/ Zhang Zongyao
BASEBAND SEMCJ/ Ken Ikuno 2006/12/14 E
System Control Ai Main Board
Test
2/1911-ROA 128 2071/2 04 of 23
Page 7
VAPC
VAPC VAPC
XTLDO
XTLDO XTLDO
VccA
VBATI VccA VccA
VccB
VDIG VccB VccB
RF Power
Page 9
VPP VPP
VPP VPP
VBATI
VBATI
VCORE18
VCORE18
VDDE18
VDDE18
Memories
Page 8
VDDF13
VDDF13
VDDE18
VDDE18
VRTC13
VRTC13
VCORE13
Page 6 VCORE13
VCORE15
VCORE15
VDDF13
VDDE18 Power Asics
VRTC13
VBUS
VBUS VBUS VCORE13
DCIO DCIO
DCIO VCORE15 VRTC13
DCIO_ON VDDE18
DCIO_ON DCIO_ON VCORE18 VDDE18
VBT27
VBT27 VBT27
VBACKUP
VBACKUP VBACKUP
VBATI
VBATI VBATI
VDIG
VDIG VDIG
VCAM27
VCAM27 VCAM27
VCAM12
VCAM12 VCAM12
CAM_27_EN VCAM18
CAM_27_EN CAM_27_EN VCAM18 VCAM18
VMSPICO
VMSPICO VMSPICO
VBT_EN
VBT_EN VBT_EN
DCIOint
DCIOint DCIOint
VCORE15
Regulators & Charging
Confidential
Approved according to 00021-LXE 107 42/1 SCHEMA DIAGRAM
Sony Ericsson SEMCJ/ Kensuke katsuta
SEMCJ/ Ken Ikuno 2006/12/14 E
BASEBAND
Power Ai Main Board
Top
2/1911-ROA 128 2071/2 05 of 23
FG sense lines, pin F11 and F12 on N2000,
should be routed together and connected
directly to pads for R2200 (no
current conducting via allowed between
connection point and pad).
C2218 close
C2201 NM 10uF
to N2000
C2289
1uF C2283
1uF C2284
10nF
NC
1uF C2286
C2200 L2201
Mount C2211 and C2212 REG70618/18
NC NM 10uF 1 2
close to battery connector BLM15EG121SN1
1Ghz
This components MUST BE fit
into RF layout side.
(REQ3317U)
(REQ3254U)
Charge sense lines, pin D2 and D3 on
N2000, should be routed together and
connected directly to pads for R2201
(no current conducting via allowed
between connection point and pad). Local ground plane
Connect local ground plane to
main ground plane in one point only
C2237
100nF
NM
VROUT1
NC3
VROUT2
(REQ3312U)