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I405
12 NET CHANGE Assignment to DATA :1 North Decoupling
CPU <--> MCH :1 :1
D[0..15]# 12 12% &
&%
+
" # #*+
D[16..31]#
+
#$%
" # #*+
#$&
#*+
D[32..47]# !
" # &(
&
D[48..63]#
+
#$ " #
#*+%
! FSB ADDR&CNTL
+
#$' " :+
#$(
:+ &1
" % &1 '
''
!
+
#$ " :+
HOST --> VRM %) &1 !
+
#$) ! "
:+%
#$
:+& ( &1
" (
(
+
#$
FSB DATA
+
#$
#$%
HOST --> GTerm ) &1
' &1
&
!
+
#$&
&1
+
#$
HOST_ADDRESS #$'
%& &1 '& /&(
&% &1 %# (
&(
+
#$(
MCH <--> CPU
! ) &1
+
#$
#$)
! )%
2"~10"+/-200mil #$
! !
!
+
#$
REF. TO GND #$
HOST <--> ITP
!
#$%
#$&
#,-./ South Decoupling
$#
#$
$# #,-./ !
'
&
+
#$' $# #,-./
+
#$( $#
#,-./%
#$
#,-./& CPU <--> MCH
$# &
+
#$) !
+
#$%
"
#$%
"
! '
')
+
" ! !
+
# "
#
!
('
()
+
# 012 %
HOST <-- CLOCK !
+
#%
012/ %
#&
# #,/
!
+
#' #,/
#(
#,/ CPU <--> MCH
# !
#)
HOST_ADDRESS_PARITY ->NC -- NOT SUPPORT
! !
# %
#
! HOST --> HTrem
%
#
#%
#& !
#
CPU <--> MCH
#'
HOST ADDRESS Storbe !
#(
#,$*/ REQ[0..4],A[16..3]#
#
#,$*/ A[35..17]#
#)
! D[0..15]#
# # #,*1/
#
#,*1/ D[16..31]# ! !
#
# #
#,*1/ D[32..47]#
#%
#,*1/% D[48..63]#
#
"
#& # #,*/ D[0..15]# "
#
" #,*/ D[16..31]#
# "
#' # #,*/ D[32..47]# "
!
#(
" #,*/% D[48..63]#
#
"%
#
CPU <--> MCH
#)
" + ( HOST_DATA_Strobe !
! " " Wide->7mil,space->10mil,Max Length->12000mil
#%
" 3+ (
#%
4&(*
"#
HOST_DATA #%
#
#%%
4-/ (
Trace Length -- See Figure 1
# :1
MCH <--> CPU #%&
# 150/ (
#%
Wide->7mil,space->10mil,Max Length->12000mil 4<';%:
" "# " 4*
2"~10"+/-100mil
#
+
#%'
" "# #,++/ (
#%(
# #
REF. TO GND #%
# #,*6/
#%)
# #,6/
4<';%:
! # # 4*' # )
+
#& # #,6/
#&
#,$/
# !
#& %# #,50/
wide->7mil, space->13mil
#&%
#,*-./ % ::+
# "
#&& # #,*/
#&
#,#+/ SET 1.2V
"#
#&' "#
#,#+3/
#&(
#,*1+/
"#
#& # #,-4-/
#&)
!
# "
#
P1IN/SAGND need close together and parallel
# # and ground guards.
#%
!
% "
#&
1+
#
" $7 Wide->10mil,Space->10mil,Max Length->8000mil
#' "
#(
!!
#
%%#
Trace Length -- See Figure 1
#)
"" +7-/ ( Wide->7mil,space->10mil,Max Length->12000mil
! " # $ Wide->7mil,space->10mil,Max Length->12000mil
#' "# 83+/ (
#'
0,$3/ ( Wide->7mil,space->10mil,Max Length->12000mil
#
#' # 51/ ( Wide->7mil,space->10mil,Max Length->12000mil
#'%
% 19,7 (
Trace Length -- See Figure 2
:%
%% :1
# #,12/
4&(/
"
/
" PLACE AT ICH END OF ROUTE
&
=1' :1
# &
% *-5 " 0+1 %
0+1/ %
( ' 0,1&
" )
#-$- 8
BSEL1 BSEL0 ' % %
"
"!
100Mhz 0 0
''
"
"
133Mhz 0 1 '
"
0,1&
"
PLACE AT CPU END OF ROUTE &
"
4&($
* !
CAD NOTES: 12MIL TRACE 20MIL SPACE * ! 0,1&
:1 :1 AGTL+Vref & 0
PLACE THESE OUTSIDE
SOCKET CAVITY % '
Trace Space --> 20mil Trace Space --> 20mil Place close to the CPU Pin NA
' Trace Wide --> 12mil ) Trace Wide --> 12mil ) ' !!
&);)* H_GTLREF2 TRACE LENGTH < 1500mil &);)* H_GTLREF3 TRACE LENGTH < 1500mil
:1 %
,1&
GTerm --> HOST GTerm --> HOST
( ) % %& ( :1
* 1 1 1 * 1 1 1
'% /
%& ( !
PLACE INSIDE CPU CAVITY PLACE INSIDE CPU CAVITY
& %);*
PLACE CAP CLOSE THE RES. DIVIDER
1.7V*(100/100+49.9)=1.7V*0.667=1.1339V
PLACE CAP CLOSE THE RES. DIVIDER
1.7V*(100/100+49.9)=1.7V*0.667=1.1339V & '
(
PLACE CLOSE TO CPU SOCKET
!
"
CAD NOTE: 5MIL TRACE 15MIL SPACE
! &;*
:
! & &;*
$! ) &;)*
#! () &;)*
: