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RXQB RXQB

RXQA RXQA Pages 15-17
VCORE15 VDDE18 VDIG WSTR WSTR
WSTR
RXIB RXIB WDAT WDAT
WDAT
RXIA RXIA VDIG WCLK WCLK
WCLK
IDATA IDATA VDDE18 TXQB TXQB
TXQB
QDATA QDATA VCORE15 TXQA TXQA
TXQA
DCLK DCLK TXIA TXIA
TXIA
TESTOUT TESTOUT RXQB TXIB TXIB
TXIB
VDDE18 VBATI RXQA RADSTR RADSTR
RADSTR
RXIB RADDAT RADDAT
Pages 18-22 RADDAT
RXIA RADCLK RADCLK
VBATI RADCLK
IDATA TXON TXON
TXON
QDATA MODA MODA
MODA
DCLK MODB MODB
MODB
TESTOUT MODC MODC
MODC
MODD MODD
VDDE18 MODD
ANTSW0 ANTSW0
Pages 9-14 ANTSW0
VCAM18 VBACKUP VMSPICO VDDE18 VDIG ANTSW1 ANTSW1
ANTSW1
ANTSW2 ANTSW2




SP2114

SP2115


SP2116

SP2117
ANTSW2
ANTSW3 ANTSW3
ANTSW3

VDIG
UMTS Access
VDDE18
PCMDATA PCMDATA
VMSPICO PCMDATA
PCMDATB PCMDATB
VBACKUP PCMDATB
KBDIM PCMSYN PCMSYN
VCAM18 KBDIM KBDIM PCMSYN
NAVDIM PCMCLK PCMCLK
NAVDIM NAVDIM PCMCLK
AMPCTRL
AMPCTRL AMPCTRL

VAD
MICN/AUXinR
BTANT BTANT BTANT MICN/AUXinR MICN/AUXinR
MICP/AUXinL
MICP/AUXinL MICP/AUXinL
VLOOP VLOOP FLIPSENSE
VLOOP
RTEMP RTEMP
RTEMP
WRFLOOP WRFLOOP
WRFLOOP SPL

SPR
BTCLKREQ BTCLKREQ BTTX DCIOint
BTCLKREQ BTTX MIDREF
BTRX BTRX BTRTS
BTRX BTRTS DCIOint ONSWA
BTCTS BTCTS WPAREF
BTCTS WPAREF
VCXOCONT MMI
VCXOCONT

MEMRESn

VPP

VAD VBUS

DCIO
BTTX BTTX
DCIO_ON
FLIPSENSE BTRTS BTRTS
VBT_EN
WPAREF WPAREF
CAM_27_EN
VCXOCONT VCXOCONT
SPL
ONSWA ONSWA
SPR

MIDREF SERVICEn VDDE18 VBT27 VRTC13 VDIG VBATI

Operation & Services MIDREF

SPR
VBATI
SPL
VDIG

VRTC13

FLIPSENSE VBT27



VDDE18
VAD



BTRESn BTRESn



RTCCLK RTCCLK



VBATI VDIG VBT27 VDDE18 VBACKUP VCAM18 VMSPICO DCIOint VRTC13 VCORE15


Pages 5-8
VBATI

VDIG


VCORE15 VDDE18
VBT27
Pages 2-4
VDDE18

VDDE18 VBACKUP Confidential
VPP
VCORE15 VPP VCAM18 Approved according to 00021-LXE 107 42/1 SCHEMA DIAGRAM
VBUS
MEMRESn VBUS
CLKREQ
CLKREQ BTRESn
DCIO
DCIO Sony Ericsson SEMCJ/ Naoki Tada
MCLK DCIO_ON
MCLK DCIO_ON VMSPICO
VBT_EN SEMCJ/ Tomokazu Ishii 2006/07/03 C
SERVICEn RTCCLK VBT_EN BASEBAND
CAM_27_EN
ONSWAn CAM_27_EN DCIOint
Logic Top MIYU
VRTC13
System Control
VCORE15

SERVICEn
Power 2/1911-ROA 128 1893/2 01 of 23
VDDE18 VCORE15 VCORE15 VDDE18
Page 3

RTCCLK
RTCCLK RTCCLK
VDDE18 VDDE18

VCORE15 VCORE15




CLKREQ
CLKREQ CLKREQ
MCLK
MCLK MCLK
SERVICEn MEMRESn
SERVICEn SERVICEn MEMRESn MEMRESn
ONSWAn BTRESn
ONSWAn ONSWAn BTRESn BTRESn


Clocks & Resets




Page 4




Test




Confidential
Approved according to 00021-LXE 107 42/1 SCHEMA DIAGRAM

Sony Ericsson SEMCJ/ Naoki Tada

BASEBAND SEMCJ/ Tomokazu Ishii 2006/07/03 C

System Control MIYU
Top

2/1911-ROA 128 1893/2 02 of 23
B2100


RTM501911/2 R1A
C1 C2


C2102 32.768kHz
C2103
22pF
22pF



Connect to ground plane in one single point

D2000
MARIKA_SYSTEM_CONTROL

RTC
AA17 R2100 R2105
RTCIN RTCOUT W17
0ohms NM 10Kohms
RTCCLK W15 RTCCLK
RTCCLK
C2104 mounted close to D2000 R14 RTCBDIS_N RTCDCON R13

Resets
Y16 RESPOW_N RESOUT0_N J7 MEMRESn
MEMRESn
C2104
1nF RESOUT1_N W21

RESOUT2_N J1 BTRESn
BTRESn
C2100
1nF Clocks
AA15 X2304 RNV403883/60
MCLK SYSCLK0 V21 SP2105

SYSCLK1 T19 CAMSYSCLK
CAMSYSCLK
C2107 27
SYSCLK2 R18 R2104
10pF VDDE18
27ohms
C2105
Control 15pF UPPER_IF_CON





J2 R2104 mounted C2106
IRQ0_N PWRREQ0_N U19
close to D2000 15pF
Actual net on system GND K4 IRQ1_N PWRREQ1 W20 C2106 close to X2304
connector page...
SERVICEn J8 SERVICE_N
SERVICEn
CLKREQ_1 V19 CLKREQ
CLKREQ GND
R2102
100ohms DB2021_MARIKA_SECURITY_EFUSE
ROP1013083/4 R2A SP2102 SP2103




PWR_IRQ

PWRRST

SP2101
D2001
EMP_WANDA_SYSTEM_IF
CLKREQ_1 T15 D4
CLKRQ ID_BALL
WANDARESn N13
RESET
RTCCLK_1 T16
CLK32
MCLK_WANDA U13
MCLK
R15
C2101 HCLK
VCORE15
1nF
ROP1013044/4
LEADFREE
R1A

R2101
100Kohms


N2000
ERICSSON AB 2010
SYSTEM CONTROL

POWER ON/RESET
ONSWAn ONSWAn C4 B8
ONSWAn ONSWA PWRRST
C5 C1
ONSWB IRQ
RTCDCON A7
ONSWC


CONTROL
SP2100
PWRREQn C10
SLEEP
CLKREQ_1 K3
CLKREQ
MCLK MCLK K9
MCLK MCLK
RTCCLK_1 M1
XTAL1


ERICSSON_AB2012
ROP1013066/6 R1A
LEADFREE




Confidential
Approved according to 00021-LXE 107 42/1 SCHEMA DIAGRAM
VDDE18 VCORE15

Sony Ericsson SEMCJ/ Naoki Tada

BASEBAND SEMCJ/ Tomokazu Ishii 2006/07/03 C
VDDE18

VCORE15
System Control MIYU
Clocks & Resets

2/1911-ROA 128 1893/2 03 of 23
D2000 D2001 D2001
MARIKA_TEST_AND_EMULATION EMP_WANDA_SWDEBUG Wanda_External_MEM_IF
L17
GPO0 C2 U3
JTAG_IF K13 EMIF_D0 EMIF_AWE
SP2106 MARIKA_TDI P14 SP2110 GPO1
TDI TDO U20 MARIKA_TDO C1
EMIF_D1 EMIF_ARE
T3
K15
SP2107 MARIKA_TMS R19 SP2111 GPO2
TMS RTCK T21 MARIKA_RTCK F5
EMIF_D2 EMIF_ARE_ADY
U2
K16
SP2108 MARIKA_TCK V20 SP2112 GPO3
TCK TEMU0_N P19 MARIKA_TEMU0n
EMIF_A1
E10
J15 E3
SP2109 MARIKA_TRSTn P18 SP2113 GPO4 EMIF_D3
TRST_N TEMU1_N T20 MARIKA_TEMU1n
EMIF_A2
A10
J13 G5
GPO5 EMIF_D4
ETM_IF H15 E1 C10
GPO6 EMIF_D5 EMIF_A3
ETMPSTAT0 M15
H13
GPO7 B9
ETMPSTAT1 L19 F2
EMIF_D6 EMIF_A4
C13 E12
UART_RX UART_TX
ETMPSTAT2 M14 EMIF_A5
C9
F1
EMIF_D7
ETMTSYNC M20
DSP INTERRUPT G3 E9
EMIF_D8 EMIF_A6
ETMTCLK L18 CPU_IACK
N6
C8
EMIF_A7
ETMTPKT0 L15 CPU_XF
R5 G2
EMIF_D9
ETMTPKT1 L20 CPU_IRQ1
N7 EMIF_A8 E8
H5 EMIF_D10
ETMTPKT2 L14 CPU_IRQ0
R6
EMIF_A9
A8