Text preview for : Mitsubishi_3825 _Group_M38258MCMXXX.pdf part of Mitsubishi M38258MCMXXX Mitsubishi_3825 _Group_M38258MCMXXX



Back to : Mitsubishi_3825 _Group_M3 | Home

To all our customers

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.

Renesas Technology Corp. Customer Support Dept. April 1, 2003

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DESCRIPTION
The 3825 group is the 8-bit microcomputer based on the 740 family core technology. The 3825 group has the LCD drive control circuit, an 8-channel AD converter, and a Serial I/O as additional functions. The various microcomputers in the 3825 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3825 Group, refer the section on group expansion.

· Serial I/O ...................... 8-bit 1 (UART or Clock-synchronized) · A-D converter .................................................. 8-bit 8 channels · LCD drive control circuit
Bias ................................................................................... 1/2, 1/3 Duty ............................................................................ 1/2, 1/3, 1/4 Common output .......................................................................... 4 Segment output ......................................................................... 40 2 Clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator) Power source voltage In high-speed mode ................................................... 4.0 to 5.5 V In middle-speed mode ............................................... 2.5 to 5.5 V (M version: 2.2 to 5.5 V) (Extended operating temperature version: 3.0 to 5.5 V) In low-speed mode ..................................................... 2.5 to 5.5 V (M version: 2.2 to 5.5 V) (Extended operating temperature version: 3.0 to 5.5 V) Power dissipation In high-speed mode ........................................................... 32 mW (at 8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode .............................................................. 45 µW (at 32 kHz oscillation frequency, at 3 V power source voltage) Operating temperature range ................................... ­ 20 to 85°C (Extended operating temperature version: ­40 to 85°C)

· ·

FEATURES

· Basic machine-language instructions ....................................... 71 · The minimum instruction execution time ............................ 0.5 µs · · · · ·
(at 8 MHz oscillation frequency) Memory size ROM .................................................................. 4 K to 60 K bytes RAM ................................................................. 192 to 2048 bytes Programmable input/output ports ............................................. 43 Software pull-up/pull-down resistors (Ports P0­P8) Interrupts .................................................. 17 sources, 16 vectors (includes key input interrupt) Timers ........................................................... 8-bit 3, 16-bit 2

·

·

APPLICATIONS
Camera, household appliances, consumer electronics, etc.

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 P30/SEG18 P31/SEG19 P32/SEG20 P33/SEG21 P34/SEG22 P35/SEG23 P36/SEG24 P37/SEG25 P00/SEG26 P01/SEG27 P02/SEG28 P03/SEG29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 P10/SEG34 P11/SEG35 P12/SEG36 P13/SEG37 P14/SEG38 P15/SEG39

PIN CONFIGURATION (TOP VIEW)

SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 VL2 C2

81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1

M38258MCMXXXFP

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31

P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P80/XCOUT P81/XCIN RESET P70 P71 P72 P73

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Package type : 100P6S-A (100-pin plastic-molded QFP)
Fig. 1 Pin configuration of M38258MCMXXXFP (The pin configuration of 100D0 is same as this.)

C1 VL1 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/ADT P56/TOUT P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/INT3 P50/INT2 P47/SRDY P46/SCLK P45/TXD P44/RXD P43/INT1 P42/INT0 P41 / f(XIN)/5 / f(XIN)/10 P40 /f(XIN) / f(XIN)/2 P77 P76 P75 P74

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PIN CONFIGURATION (TOP VIEW)
SEG13 SEG14 SEG15 SEG16 SEG17 P30/SEG18 P31/SEG19 P32/SEG20 P33/SEG21 P34/SEG22 P35/SEG23 P36/SEG24 P37/SEG25 P00/SEG26 P01/SEG27 P02/SEG28 P03/SEG29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 P10/SEG34 P11/SEG35 P12/SEG36 P13/SEG37
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 VL2 C2 C1 VL1

76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

50 49 48 47 46 45 44 43 42 41

M38258MCMXXXGP M38258MCMXXXHP

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

P14/SEG38 P15/SEG39 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P80/XCOUT P81/XCIN RESET P70 P71 P72 P73 P74 P75 P76

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Package type : GP ........................... 100P6Q-A (100-pin plastic-molded LQFP) Package type : HP ........................... 100PFB-A (100-pin plastic-molded TQFP)
Fig. 2 Pin configuration of M38258MCMXXXGP, M38258MCMXXXHP

2

P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/ADT P56/TOUT P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/INT3 P50/INT2 P47/SRDY P46/SCLK P45/TXD P44/RXD P43/INT1 P42/INT0 P41 / f(XIN)/5 / f(XIN)/10 P40 / f(XIN) / f(XIN)/2 P77

FUNCTIONAL BLOCK DIAGRAM (Package : 100P6S-A)

Clock input XIN Reset input RESET
35 91 40

Clock output XOUT (5 V) VCC (0 V) VSS

38

39

XCOUT XCIN
ADT INT2, INT3 INT0, INT1

P8 (2)

P7 (8)

P6 (8)

P5 (8)

P4 (8)

Real time port function

CNT R0, CNTR1 RTP0, RTP1

P3 (8)

P2 (8)

Key-on wake up

Fig. 3 Functional block diagram
Data bus CPU A X Y S PCH PS Timer X (16) Timer Y (16) Timer 1 (8) Timer 2 (8) Timer 3 (8) PCL
LCD display RAM (20 bytes)
2 1

Clock generating circuit ROM RAM

100

99 98

VL1 C1 C2 VL2 VL3
97 96 95 94

XCIN Subclock input

XCOUT Subclock output

LCD drive control circuit

COM0 COM1 COM2 COM3
90 89 88 87 86 85 84 83 82 81 80

A-D converter (8)

SI/O (8) TOUT

79 78 77 76 75 74 73

SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17

P1 (8)

P0 (8)

36 37 11 12 13 14 15 16 17 18

27 28 29 30 31 32 33 34

3 4 5 6 7 8 9 10 92 93

19 20 21 22 23 24 25 26

65 66 67 68 69 70 71 72

41 42 43 44 45 46 47 48

49 50 51 52 53 54 55 56

57 58 59 60 61 62 63 64

I/O port P8

I/O port P7

I/O port P6

VREF AVSS (0 V) I/O port P5

I/O port P4

Output port P3

I/O port P2

Output port P1

Output port P0

MITSUBISHI MICROCOMPUTERS

3825 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

3

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PIN DESCRIPTION
Table 1. Pin description (1) Pin VCC, VSS VREF Name Power source Analog reference voltage Analog power source Reset input Clock input Function Function except a port function ·Apply voltage of power source to V CC, and 0 V to VSS . (For the limits of VCC, refer to "Recommended operating conditions".) · Reference voltage input pin for A-D converter. · GND input pin for A-D converter. · Connect to VSS. · Reset input pin for active "L" · Input and output pins for the main clock generating circuit. · Feedback resistor is built in between XIN pin and XOUT pin. · Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. · If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. · This clock is used as the oscillating source of system clock. · Input 0 VL1 VL2 VL3 VCC voltage · Input 0 ­ VL3 voltage to LCD · External capacitor pins for a voltage multiplier (3 times) of LCD contorl. · LCD common output pins · COM2 and COM3 are not used at 1/2 duty ratio. · COM3 is not used at 1/3 duty ratio. · LCD segment output pins · · · · · · · · · · · · · · · · · 8-bit output port CMOS 3-state output structure Pull-down control is enabled. Port output control is enabled. 6-bit output port CMOS 3-state output structure Pull-down control is enabled. Port output control is enabled. 2-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. Pull-up control is enabled. · Key input (key-on wake up) interrupt input pins · LCD segment pins

AVSS

RESET XIN

XOUT

Clock output

VL1 ­ VL3 C 1 , C2

LCD power source

Charge-pump capacitor pin Common output

COM0 ­ COM3

SEG0 ­ SEG17 P00/SEG26 ­ P07/SEG33

Segment output Output port P0

P10/SEG34 ­ P15/SEG39

Output port P1

P16, P17

I/O port P1

P20 ­ P27

I/O port P2

8-bit Input port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. · Pull-up control is enabled. · · · · 8-bit output port CMOS 3-state output structure Pull-down control is enabled. Port output control is enabled.

P30/SEG18 ­ P37/SEG25

Output port P3

· LCD segment pins

4

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 2. Pin description (2) Pin P40/f(XIN)/ f(XIN)/2, P41/f(XIN)/5/ f(XIN)/10 P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK, P47/SRDY P50/INT2, P51/INT3 P52/RTP0, P53/RTP1 P54/CNTR0, P55/CNTR1 P56/TOUT P57/ADT P60/AN0­ P67/AN7 I/O port P6 · · · · 8-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. · Pull-up control is enabled. · 1-bit input port · CMOS compatible input level · · · · · · · · · 7-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. Pull-up control is enabled. ·Sub-clock generating circuit I/O pins (Connect a resonator. External clock cannot be used.) I/O port P5 · · · · 8-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. · Pull-up control is enabled. Name I/O port P4 · · · · Function Function except a port function 8-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. · Pull-up control is enabled. · Clock output pins

· Interrupt input pins · Serial I/O function pins

· Interrupt input pins · Real time port function pins · Timers X, Y functions pins · Timer 2 output pin · A-D trigger input pin · A-D conversion input pins

P70 P71­P77

Input port P7 I/O port P7

P80/XCOUT, P81/XCIN

I/O port P8

2-bit I/O port CMOS compatible input level CMOS 3-state output structure I/O direction register allows each pin to be individually programmed as either input or output. · Pull-up control is enabled.

5

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PART NUMBERING
Product M3825 8 M C M XXX HP Package type FP : 100P6S-A package HP : 100PFB-A package GP: 100P6Q-A package FS : 100D0 package ROM number Omitted in One Time PROM version shipped in blank and EPROM version. Normally, using hyphen When electrical characteristic, or division of quality identification code using alphanumeric character ­ : Standard D : Extended operating temperature version M : M version ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes

9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes

The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes
Fig. 4 Part numbering

6

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION (STANDARD, ONE TIME PROM VERSION, EPROM VERSION)
Mitsubishi plans to expand the 3825 group(Standard, One Time PROM version, EPROM version) as follows.

Packages
100PFB-A ................................ 0.4 mm-pitch plastic molded TQFP 100P6Q-A ................................ 0.5 mm-pitch plastic molded LQFP 100P6S-A ................................ 0.65 mm-pitch plastic molded QFP 100D0 ................... 0.65 mm-pitch ceramic LCC (EPROM version)

Memory Type
Support for mask ROM, One Time PROM, and EPROM versions.

Memory Size
ROM size ............................................................ 16 K to 60 Kbytes RAM size ............................................................ 640 to 2048 bytes

Memory Expansion Plan
ROM size (bytes) 60K 56K 52K 48K 44K 40K 36K 32K 28K 24K 20K 16K 12K 8K 4K
256 512 640 768 1,024 1,536 2,048

Mass product M38259EF

Mass product M38257M8/E8 Mass product M38254M6 Mass product M38254M4

RAM size (bytes)
Fig. 5 Memory expansion plan

7

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Currently products are listed below. Table 3. List of products Product M38254M4-XXXFP M38254M4-XXXGP M38254M6-XXXFP M38254M6-XXXGP M38257M8-XXXFP M38257E8FP M38257M8-XXXGP M38257E8GP M38257E8FS M38259EFFP M38259EFHP M38259EFGP M38259EFFS ROM size (bytes) ROM size for User in ( ) 16384 (16254) 24576 (24446) RAM size (bytes) 640 640 Package 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6S-A 100P6Q-A 100P6Q-A 100D0 100P6S-A Remarks As of Dec. 2000

32768 (32638)

1024

61440 (61310)

2048

Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version (blank) Mask ROM version One Time PROM version (blank) EPROM version One Time PROM version (blank) 100PFB-A One Time PROM version (blank) 100P6Q-A One Time PROM version (blank) 100D0 EPROM version

8

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION)
Mitsubishi plans to expand the 3825 group (Extended operating temperature version) as follows.

Memory Size
ROM size ............................................................ 16 K to 60 Kbytes RAM size ............................................................ 640 to 2048 bytes

Packages Memory Type
Support for mask ROM, one time PROM version. 100P6S-A ................................ 0.65 mm-pitch plastic molded QFP

Memory Expansion Plan
ROM size (bytes) 60K 56K 52K 48K 44K 40K 36K 32K 28K 24K 20K 16K 12K 8K 4K
256 512 640 768 1,024 1,536 2,048

Mass product M38259EFD

Mass product M38258MCD

Mass product M38257M8D Mass product M38254M6D Mass product M38254M4D

RAM size (bytes)
Fig. 6 Memory expansion plan for extended operating temperature version

Currently products are listed below. Table 4. List of products for extended operating temperature version Product M38254M4DXXXFP M38254M6DXXXFP M38257M8DXXXFP M38258MCDXXXFP M38259EFDFP ROM size (bytes) ROM size for User in ( ) 16384 (16254) 24576 (24446) 32768 (32638) 49152 (49022) 61440 (61310) RAM size (bytes) 640 640 1024 1536 2048 Package 100P6S-A 100P6S-A 100P6S-A 100P6S-A 100P6S-A Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version (blank) Remarks As of Dec. 2000

9

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION (M VERSION)
Mitsubishi plans to expand the 3825 group (M version) as follows.

Packages
100PFB-A ................................ 0.4 mm-pitch plastic molded TQFP 100P6Q-A ................................ 0.5 mm-pitch plastic molded LQFP 100P6S-A ................................ 0.65 mm-pitch plastic molded QFP

Memory Type
Support for mask ROM version.

Memory Size
ROM size ......................................................................... 48 Kbytes RAM size ....................................................................... 1536 bytes

Memory Expansion Plan
ROM size (bytes) 60K 56K 52K 48K 44K 40K 36K 32K 28K 24K 20K 16K 12K 8K 4K
256 512 768 1,024 1,536 2,048

Mass product M38258MCM

RAM size (bytes)
Fig. 7 Memory expansion plan for M version

Currently products are listed below. Table 5. List of products for low power source version Product M38258MCMXXXFP M38258MCMXXXHP M38258MCMXXXGP 49152 (49022) 1536 ROM size (bytes) ROM size for User in ( ) RAM size (bytes) Package 100P6S-A 100PFB-A 100P6Q-A Remarks Mask ROM version Mask ROM version Mask ROM version As of Dec. 2000

10

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU)
The 3825 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used.

[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is "0" , the high-order 8 bits becomes "0016". If the stack page selection bit is "1", the high-order 8 bits becomes "0116". The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 9. Store registers other than those described in Figure 9 with program when the user needs them during interrupts or subroutine calls.

[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator.

[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address.

[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.

[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address.

b7 A b7 X b7 Y b7 S b15 PCH b7 b7 PCL

b0 Accumulator b0 Index register X b0 Index register Y b0 Stack pointer b0 Program counter b0 Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag

N V T B D I Z C

Fig. 8 740 Family CPU register structure

11

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

On-going Routine

Interrupt request (Note) Execute JSR M (S) Push return address on stack (S) M (S) (S) (PCH) (S) ­ 1 (PCL) (S)­ 1

M (S) (S) M (S) (S) M (S) (S)

(PCH) (S) ­ 1 (PCL) (S) ­ 1 (PS) (S) ­ 1 Push contents of processor status register on stack Push return address on stack

Subroutine Execute RTS POP return address from stack (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S)

Interrupt Service Routine

Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) (S) + 1 M (S)

I Flag is set from "0" to "1" Fetch the jump vector POP contents of processor status register from stack

POP return address from stack

Note: Condition for acceptance of an interrupt

Interrupt enable flag is "1" Interrupt disable flag is "0"

Fig. 9 Register push and pop at interrupt generation and subroutine call Table 6 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP

12

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. ·Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. ·Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". ·Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". ·Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC

·Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". ·Bit 5: Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations. ·Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. ·Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag.

Table 7 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag ­ ­ I flag SEI CLI D flag SED CLD B flag ­ ­ T flag SET CLT V flag ­ CLV N flag ­ ­

13

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and the internal system clock selection bit. The CPU mode register is allocated at address 003B16.

b7

b0 CPU mode register (CPUM (CM) : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Not available 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Not used (returns "1" when read) (Do not write "0" to this bit) Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN­XCOUT oscillating function Main clock (XIN­XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) Internal system clock selection bit 0 : XIN­XOUT selected (middle-/high-speed mode) 1 : XCIN­XCOUT selected (low-speed mode)

Fig. 10 Structure of CPU mode register

14

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MEMORY Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.

Zero Page
The 256 bytes from addresses 000016 to 00FF 16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.

RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.

Special Page ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.

Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.

RAM area RAM size (bytes) 192 256 384 512 640 768 896 1024 1536 2048 ROM area ROM size (bytes) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 Address YYYY16 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 Address ZZZZ16 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 FFFE16 Reserved ROM area FFFF16 Interrupt vector area Special page ROM FF0016 FFDC16 ZZZZ16 YYYY16 Reserved ROM area (128 bytes) Address XXXX16 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 084016 Not used Reserved area XXXX16 RAM 000016 SFR area 004016 005416 010016 LCD display RAM area Zero page

Fig. 11 Memory map diagram

15

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

000016 Port P0 (P0) 000116 000216 Port P1 (P1) 000316 Port P1 output control register (P1C) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 000616 Port P3 (P3) 000716 000816 Port P4 (P4) 000916 Port P4 direction register (P4D) 000A16 Port P5 (P5) 000B16 Port P5 direction register (P5D) 000C16 Port P6 (P6) 000D16 Port P6 direction register (P6D) 000E16 Port P7 (P7) 000F16 Port P7 direction register (P7D) 001016 Port P8 (P8) 001116 Port P8 direction register (P8D) 001216 001316 001416 001516 001616 PULL register A (PULLA) 001716 PULL register B (PULLB) 001816 Transmit/Receive buffer register(TB/RB) 001916 Serial I/O status register (SIOSTS) 001A16 Serial I/O control register (SIO1CON) 001B16 UART control register (UART CON) 001C16 Baud rate generator (BRG) 001D16 001E16 001F16

002016 Timer X (low) (TXL) 002116 Timer X (high) (T XH) 002216 Timer Y (low) (TYL) 002316 Timer Y (high) (T YH) 002416 Timer 1 (T1) 002516 Timer 2 (T2) 002616 Timer 3 (T3) 002716 Timer X mode register (TXM) 002816 Timer Y mode register (TYM) 002916 Timer 123 mode register (T123M) 002A16 Clock output control register (TCON) 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 A-D control register (ADCON) 003516 A-D conversion register (AD) 003616 003716 003816 Segment output enable register (SEG) 003916 LCD mode register (LM) 003A16 Interrupt edge selection register (INTEDGE) 003B16 CPU mode register (CPUM) 003C16 Interrupt request register 1(IREQ1) 003D16 Interrupt request register 2(IREQ2) 003E16 Interrupt control register 1(ICON1) 003F16 Interrupt control register 2(ICON2)

Fig. 12 Memory map of special function register (SFR)

16

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

I/O PORTS Direction Registers
The 3825 group has 43 programmable I/O pins arranged in seven I/O ports (ports P16, P17, P2, P4­P6, P71­P77, P80 and P81). The I/O ports have direction registers which determine the input/output direction of each individual pin. (Ports P1 6 and P1 7 are shared with bits 6 and 7 of the port P1 output control register). Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that bit, that pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.

b7

b0

PULL register A (PULLA : address 001616) P0, P10­P15, P3 pull-down (shared with P0 and P3 output control : refer to the text) P16­P17 pull-up P20­P27 pull-up P80, P81 pull-up P40­P43 pull-up P44­P47 pull-up Not used (return "0" when read)

b7

b0 PULL register B (PULLB : address 001716) P50­P53 pull-up P54­P57 pull-up P60­P63 pull-up P64­P67 pull-up P71­P73 pull-up P74­P77 pull-up Not used (return "0" when read) 0 : Disable 1 : Enable

Port P1 Output Control Register
Bit 0 of the port P1 output control register (address 0003 16) enables control of the output of ports P10 to P15. When the bit is set to "1", the port output function is valid. In this case, setting of the PULL register A to ports P10 to P15 is invalid. When resetting, bit 0 of the port P1 output control register is set to "0" (the port output function is invalid.)

Note: The contents of PULL register A and PULL register B do not affect ports programmed as the output port.

Fig. 13 Structure of PULL register A and PULL register B

Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL register B (address 001716), ports P0 to P8 except P70 can control either pull-down or pull-up (pins that are shared with the segment output pins for LCD are pull-down; all other pins are pull-up) with a program. However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports. (except for ports P0 and P3). Ports P0 and P3 share the port output control function with bit 0 of the PULL register A. When set to "1", the port output function is invalid (Pull-down is valid). When set to "0", the port output function is valid (Pull-down is invalid). The PULL register A setting is invalid for pins set to segment output with the segment output enable register.

17

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 8. I/O ports functions Pin P00/SEG26­ P07/SEG33 Name Port P0 Input/Output Output I/O Format CMOS 3-state output Non-Port Function LCD segment output Related SFRs PULL register A Segment output enable register PULL register A Segment output enable register Port P1 output control register PULL register A Key-on wake up interrupt input PULL register A Interrupt control register 2 PULL register A Segment output enable register Clock output control register PULL register A PULL register A Interrupt edge selection register PULL register A Serial I/O control register Serial I/O status register UART control register PULL register B Interrupt edge selection register PULL register B Timer X mode register PULL register B Timer X mode register PULL register B Timer Y mode register PULL register B Timer 123 mode register PULL register B A-D control register PULL register B A-D control register (3) (4) (5) (6) (2) (7) (8) (9) (8) (9) (10) Diagram No. (1)

P10/SEG34­ P15/SEG39 Port P1 P16 , P17

Output

CMOS 3-state output

LCD segment output

(1)

Input/output, individual bits Port P2 Input/output, individual bits

P20­P27

CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS 3-state output

(2)

(2)

P30/SEG18­ P37/SEG25 P40/f(XIN)/ f(XIN)/2, P41/f(XIN)/5/ f(XIN)/10 P42/INT0, P43/INT1 P44/RXD P54/TXD P46/SCLK P47/SRDY P50/INT2, P51/INT3 P52/RTP0, P53/RTP1 P54/CNTR0 P55/CNTR1 P56/TOUT P57/ADT P60/AN0­ P67/AN7 P70

Port P3

Output

LCD segment output

(1)

Clock output

(2)

Port P4

Input/output, individual bits

CMOS compatible input level CMOS 3-state output

External interrupt input

Serial I/O function I/O

External interrupt input Real time port function output Port P5 Input/output, individual bits CMOS compatible input level CMOS 3-state output Timer X function I/O Timer Y function input Timer 2 output A-D trigger input Port P6 Input/output, individual bits Input Port P7 Input/output, individual bits Input/output, individual bits Output Output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output LCD common output LCD segment output A-D conversion input

(11) PULL register B Sub-clock generating circuit (12) (13) (14) (15) (16)

P71­P77 P80/XCOUT Port P8 P81/XCIN COM0­COM3 SEG0­SEG17 Common Segment

PULL register A CPU mode register LCD mode register

Note 1: When using double-function ports as functional I/O pins, refer the method to the relevant sections. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.

18

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(1) Ports P0, P10­P15, P3 LCD drive timing Segment data Port latch Interface logic level shift circuit VL2/VL3/VCC Segment/Port

Data bus

Segment VL1/VSS Port Pull-down

Port/Segment Port ON/OFF

(2) Ports P16, P17, P2, P40­P43, P50, P51 Pull-up control

(3) Port P44 Pull-up control Serial I/O enable bit Reception enable bit

Direction register Data bus Port latch

Direction register Data bus Port latch

Key-on wake up interrupt input INT0­INT3 interrupt input Except P16, P17, P40, P41

Serial I/O input

(4) Port P45 Pull-up control P45/TXD P-channel output disable bit Serial I/O enable bit Transmission enable bit Direction register Data bus Port latch

(5) Port P46 Serial I/O synchronization clock selection bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Data bus Port latch

Pull-up control

Serial I/O output

Serial I/O clock output Serial I/O clock input

(6) Port P47 Pull-up control

(7) Ports P52, P53 Pull-up control

Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit Direction register Data bus Port latch

Direction register Data bus Port latch

Serial I/O ready output

Real time control bit Real time port data

Fig. 14 Port block diagram (1)

19

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(8) Ports P54, P56 Pull-up control

(9) Ports P55, P57

Pull-up control Direction register Data bus Port latch Data bus Pulse output mode Timer output CNTR0 interrupt input P54 only (10) Port P6 Pull-up control (11) Port P70 Direction register Data bus CNTR1 interrupt input A-D trigger interrupt input Direction register Port latch

Port latch Data bus

A-D conversion input Analog input pin selection bit (12) Ports P71­P77 Pull-up control (13) Port P80 Port Xc switch bit + Pull-up control Port XC switch bit Direction register Data bus Data bus Port latch Port latch

Direction register

Oscillation circuit (14) Port P81 Port Xc switch bit + Pull-up control Port XC switch bit Direction register Data bus Port latch Port P81 Port XC switch bit

(15) COM0­COM3 VL3

VL2 VL1 Sub-clock generating circuit input (16) SEG0­SEG17 VL2/VL3 VSS The voltage applied to the sources of P-channel and N-channel transistors is the controlled voltage by the bias value.

The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value.

VL1/VSS

Fig. 15 Port block diagram (2)

20

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

INTERRUPTS
Interrupts occur by seventeen sources: eight external, eight internal, and one software.

Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter.

Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority.

Table 9. Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 INT1 Serial I/O reception Serial I/O transmission Timer X Timer Y Timer 2 Timer 3 CNTR0 CNTR1 Timer 1 INT2 INT3 Key input (Key-on wake up) ADT 16 A-D conversion BRK instruction 17 FFDD16 FFDC16 FFDF16 FFDE16 At completion of A-D conversion At BRK instruction execution Priority 1 2 3 4 Vector Addresses (Note 1) High Low FFFD16 FFFC16 FFFB16 FFF916 FFF716 FFFA16 FFF816 FFF616 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of serial I/O data reception At completion of serial I/O transmit shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At timer 1 underflow At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input At falling of conjunction of input level for port P2 (at input mode) At falling of ADT input Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O is selected

5 6 7 8 9 10 11 12 13 14 15

FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116

FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016

Valid when serial I/O is selected

External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid when an "L" level is applied) Valid when ADT interrupt is selected External interrupt (Valid at falling) Valid when A-D interrupt is selected Non-maskable software interrupt

Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority.

21

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

sNotes on interrupts When setting the followings, the interrupt request bit may be set to "1". ·When setting external interrupt active edge Related register: Interrupt edge selection register (address 3A16) Timer X mode register (address 2716) Timer Y mode register (address 2816) ·When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: A-D control regsiter (address 3416)

When not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. Set the corresponding interrupt enable bit to "0" (disabled). Set the interrupt edge select bit or the interrupt source select bit to "1". Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. Set the corresponding interrupt enable bit to "1" (enabled).

Interrupt request bit Interrupt enable bit

Interrupt disable flag (I)

BRK instruction Reset

Interrupt request

Fig. 16 Interrupt control
b7 b0

Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit Not used (return "0" when read)

0 : Falling edge active 1 : Rising edge active

b7

b0

Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1 interrupt request bit Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit

b7

b0

Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1 interrupt request bit Timer 1 interrupt request bit INT2 interrupt request bit INT3 interrupt request bit Key input interrupt request bit ADT/AD conversion interrupt request bit Not used (returns "0" when read)

0 : No interrupt request issued 1 : Interrupt request issued

b7

b0

Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit

b7

b0

Interrupt control register 2 (ICON2 : address 003F16) CNT R0 interrupt enable bit CNT R1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit Key input interrupt enable bit ADT/AD conversion interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit)

0 : Interrupts disabled 1 : Interrupts enabled

Fig. 17 Structure of interrupt-related registers

22

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Key Input Interrupt (Key-on Wake Up)
A Key-on wake up interrupt request is generated by applying a falling edge to any pin of port P2 that have been set to input mode. In other words, it is generated when AND of input level goes from

"1" to "0". An example of using a key input interrupt is shown in Figure 18, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P20­P23.

Port PXx "L" level output PULL register A Bit 2 = "1" Port P27 direction register = "1"
Key input interrupt request



Port P27 latch

P27 output

Port P26 direction register = "1"


Port P26 latch

P26 output

Port P25 direction register = "1"


Port P25 latch

P25 output

Port P24 direction register = "1"


Port P24 latch

P24 output

Port P23 direction register = "0"


P23 input

Port P23 latch

Port P2 Input reading circuit



Port P22 direction register = "0"


P22 input

Port P22 latch

Port P21 direction register = "0"


P21 input

Port P21 latch



Port P20 direction register = "0"


P20 input

Port P20 latch

P-channel transistor for pull-up CMOS output buffer

Fig. 18 Connection example when using key input interrupt and port P2 block diagram

23

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMERS
The 3825 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches "00 16", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1".

Read and write operation on 16-bit timer must be performed for both high- and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation.

Real time port control bit "1" P52 Q D Latch P52 direction register "0" P52 latch Real time port control bit "1" Q D P53 Latch P53 direction register "0" P53 latch

Data bus P52 data for real time port

P53 data for real time port Real time port control bit "0" "1" Timer X stop control bit
Timer X (low) latch (8) Timer X (low) (8)

Timer X mode register write signal Timer X write control bit
Timer X (high) latch (8) Timer X (high) (8)

f(XIN)/16 (f(XCIN)/16 in low-speed mode)
Timer X operatCNT R0 active edge switch bit ing mode bits "00","01","11" "0"

P54/CNTR0

"10" "1" Pulse width measurement mode CNTR0 active edge switch bit "0" "1" P54 latch Pulse output mode f(XIN)/16 (f(XCIN)/16 in low-speed mode]) Timer Y stop control bit "00","01","11"
Falling edge detection

Timer X interrupt request CNTR0 interrupt request

Pulse output mode QS T Q
Rising edge detection Period measurement mode

P54 direction register

Timer Y operating mode bits "00","01","10"
Pulse width HL continuously measurement mode

CNT R1 interrupt request

"11"

P55/CNTR1

CNT R1 active edge switch bit "0" "1"

Timer Y (low) latch (8) Timer Y (low) (8)

Timer Y (high) latch (8) Timer Y (high) (8)

"10" Timer Y operating mode bits

Timer Y interrupt request

f(XIN)/16 (f(XCIN)/16 in low-speed mode]) Timer 1 count source selection bit "0" Timer 1 latch (8) XCIN Timer 1 (8) "1"

Timer 2 count source selection bit Timer 2 latch (8) "0" Timer 2 (8) "1"
f(XIN)/16 (f(XCIN)/16 in low-speed mode])

Timer 2 write control bit

Timer 1 interrupt request Timer 2 interrupt request

TOUT output active edge switch bit "0" P56/TOUT

TOUT output control bit QS "0" Timer 3 latch (8) Timer 3 (8) "1" Timer 3 count source selection bit

T "1" P56 latch Q P56 direction register TOUT output control bit f(XIN)/16(f(XCIN)/16 in low-speed mode])

Timer 3 interrupt request

Internal

clock = XCIN/2.

Fig. 19 Timer block diagram

24

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timer X
Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write and the real time port by setting the timer X mode register.
b7 b0 Timer X mode register (TXM : address 002716) Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid P52 data for real time port P53 data for real time port Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNT R0 active edge switch bit 0 : Count at rising edge in event counter mode Start from "H" output in pulse output mode Measure "H" pulse width in pulse width measurement mode Falling edge active for CNTR0 interrupt 1 : Count at falling edge in event counter mode Start from "L" output in pulse output mode Measure "L" pulse width in pulse width measurement mode Rising edge active for CNT R0 interrupt Timer X stop control bit 0 : Count start 1 : Count stop

(1) Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).

(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR 0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P54 direction register to output mode.

(3) Event counter mode
The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P54 direction register to input mode.

(4) Pulse width measurement mode
The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If CNTR0 active edge switch bit is "0", the timer counts while the input signal of CNTR0 pin is at "H". If it is "1", the timer counts while the input signal of CNTR0 pin is at "L". When using a timer in this mode, set the corresponding port P5 4 direction register to input mode. qTimer X Write Control If the timer X write control bit is "0", when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is "1", when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. qReal Time Port Control While the real time port function is valid, data for the real time port are output from ports P5 2 and P5 3 each time the timer X underflows. (However, if the real time port control bit is changed from "0" to "1" after set of the real time port data, data are output independent of the timer X operation.) If the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the corresponding port direction registers to output mode.

Fig. 20 Structure of timer X mode register

sNote on CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit.

25

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
b7 b0 Timer Y mode register (TYM : address 002816) Not used (return "0" when read) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Falling edge active for CNTR1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNTR1 interrupt Timer Y stop control bit 0 : Count start 1 : Count stop

(1) Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).

(2) Period measurement mode
CNTR 1 interrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Except for the above-mentioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR1 pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR 1 pin input signal is found by CNTR1 interrupt. When using a timer in this mode, set the corresponding port P55 direction register to input mode.

(3) Event counter mode
The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P55 direction register to input mode.

Fig. 21 Structure of timer Y mode register

(4) Pulse width HL continuously measurement mode
CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the corresponding port P55 direction register to input mode.

sNote on CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit.

26

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. The timer latch value is not affected by a change of the count source. However, because changing the count source may cause an inadvertent count down of the timer. Therefore, rewrite the value of timer whenever the count source is changed. qTimer 2 Write Control If the timer 2 write control bit is "0", when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is "1", when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. qTimer 2 Output Control When the timer 2 (T OUT) is output enabled, an inversion signal from pin TOUT is output each time timer 2 underflows. In this case, set the port P56 shared with the port TOUT to the output mode.
b7 b0 Timer 123 mode register (T123M :address 002916) TOUT output active edge switch bit 0 : Start at "H" output 1 : Start at "L" output TOUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled Timer 2 write control bit 0 : Write data in latch and counter 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 1 count source selection bit 0 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) 1 : f(XCIN) Not used (return "0" when read) Note: Internal clock is f(XCIN)/2 in the low-speed mode.

sNote on Timer 1 to Timer 3
When the count source of timers 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is generated in count input of timer. If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. Fig. 22 Structure of timer 123 mode register

27

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SERIAL I/O
Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation.

(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the mode selection bit of the serial I/O control register to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB (address 001816).

Data bus Address 001816
Receive buffer register Serial I/O control register

Address 001A16

Receive buffer full flag (RBF) Receive interrupt request (RI)
Clock control circuit

P44/RXD

Receive shift register

Shift clock

P46/SCLK Serial I/O synchronization clock selection bit Frequency division ratio 1/(n+1)
Baud rate generator

BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 P47/SRDY F/F
Falling-edge detector

1/4

Address 001C16
Clock control circuit

Shift clock P45/TXD
Transmit shift register
T ran smit buffer register (T B)

Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Address 001916

Address 001816 Data bus

Serial I/O status register

Fig. 23 Block diagram of clock synchronous serial I/O

Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TXD Serial input RXD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7

Receive enable signal SRDY Write signal to receive/transmit buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection

TBE = 1 TSC = 0

Notes 1 : T he transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE = 1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TXD pin. 3 : T he receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" .

Fig. 24 Operation of clock synchronous serial I/O function

28

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis-

ter, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received.

Data bus Address 001816 OE Receive buffer register Character length selection bit STdetector 7 bits Receive shift register
8 bits

Serial I/O control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16

P44/RXD

PE FE

SP detector Clock control circuit

UART control register Address 001B16

Serial I/O synchronization clock selection bit P46/SCLK BRG count source selection bit f(XIN) ( f(XCIN) in low-speed mode) 1/4 Frequency division ratio 1/(n+1) Baud rate generator Address 001C16
ST/SP/PA generator

1/16 P45/TXD Character length selection bit
Transmit buffer register

Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 001916

Transmit shift register

Address 001816 Data bus

Fig. 25 Block diagram of UART serial I/O

Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD ST D0 TBE=0 TBE=1 D1 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1
Generated

TSC=1 SP at 2nd bit in 2-stop-bit mode

Receive buffer read signal

RBF=1 Serial input RXD ST D0 D1 SP ST D0

RBF=0

RBF=1

D1

SP

Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2 : T he transmit interrupt (TI) can be generated to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3 : T he receive interrupt (RI) is set when the RBF flag becomes "1". 4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.

Fig. 26 Operation of UART serial I/O function

29

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

[Transmit Buffer/Receive Buffer Register (TB/ RB)] 001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is writeonly and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer register is "0".

[Serial I/O Status Register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O enable bit SIOE (bit 7 of the Serial I/O Control Register) also clears all the status flags, including the error flags. All bits of the serial I/O status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to "1", the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1".

[Serial I/O Control Register (SIOCON)] 001A16
The serial I/O control register contains eight control bits for the serial I/O function.

[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P45/TXD pin.

[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.

sNotes on serial I/O
When setting the transmit enable bit to "1", the serial I/O transmit interrupt request bit is automatically set to "1". When not requiring the interrupt occurrence synchronized with the transmission enalbed, take the following sequence. Set the serial I/O transmit interrupt enable bit to "0" (disabled). Set the transmit enable bit to "1". Set the serial I/O transmit interrupt request bit to "0" after 1 or more instructions have been executed. Set the serial I/O transmit interrupt enable bit to "1" (enabled).

30

MITSUBISHI MICROCOMPUTERS

3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b7

b0

Serial I/O status register (SIOSTS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE) =0 1: (OE) U (PE) U (FE) =1 Not used (returns "1" when read)

b7

b0

Serial I/O control register (SIOCON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O synchronization clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronized serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronized serial I/O is selected. External clock input divided by 16 when UART is selected. SRDY output enable bit (SRDY) 0: P47 pin operates as ordinary I/O pin 1: P47 pin operates as SRDY output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P44­P47 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P44­P47 operate as serial I/O pins)

b7

b0 UART control regi ster

(UART CON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD P-channel output disable bit (POFF) 0: CMOS