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Order Number: MCUK981201G8

Technical Guide
GD70 Personal Cellular Telephone
Handheld Portable

EB-GD70 6SHFLILFDWLRQ
900 MHz Frequency range Tx/Rx frequency separation RF channel bandwidth Number of RF channels Speech coding Operating temperature Type RF Output Power Modulation Connection Voice digitizing Transmission speed Diversity Signal Reception Intermediate Frequency Antenna Terminal Impedance Antenna VSWR Dimensions Class 4 Handheld 2 W maximum GMSK (BT = 0.3) 8 ch/TDMA 13 kbps RPE-LTP / 13 kps ACLEP / 5.6 kps CELP / VSLEP 270.3 kbps Frequency hopping Double superheterodyne Tx 890 - 915 MHz Rx 935 - 960 MHz 50 <2.1 : 1 Height: 132 mm Width: 45.5 mm Depth: 19.5 mm 125 cc 134 g Graphical chip on glass liquid crystal, Alphanumeric 16 x 3 characters, 5 icons and 6 x 1 characters Green: 4 LEDs for the LCD 8 LEDs for the keyboards 1 LED Incoming call Red: 1 LED Charging indicator 17 keys, Navigation key Plug-in type only 5.8 V 3.6 V Battery Pack (EB-BSD70): 100 hrs Battery Pack (EB-BMD70): 105 hrs Battery Pack (EB-BLD70): 180 hrs Battery Pack (EB-BSD70): 240 mm Battery Pack (EB-BMD70): 250 mm Battery Pack (EB-BLD70): 430 mm Tx 1710 - 1785 MHz Rx 1805 - 1880 MHz 124 Full rate/Half rate/Enhanced Full rate Tx: 890 - 915 MHz Rx: 935 - 960 MHz 45 MHz 200 kHz 374 Full rate/Half rate 1800 MHz Tx: 1710 - 1785 MHz Rx: 1805 - 1880 MHz 95 MHz

-10C to +55C Class 1 Handheld 1 W maximum

Volume Weight Display Illumination

Keypad SIM External DC Supply Voltage Battery Standby Battery Life DRX 9 Conversation Battery Life PL 7, DTX 50%

Unless stated these specifications are with Battery Pack (EB-BSD70) fitted. Battery life figures are dependent on network conditions.

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This Technical Guide is copyright and issued on the strict understanding that it is not to be reproduced, copied, or disclosed to any third party, either in whole or part, without the prior written consent of Matsushita Communication Industrial UK Ltd. Every care has been taken to ensure that the contents of this manual give an accurate representation of the equipment. However, Matsushita Communication Industrial UK Ltd. accepts no responsibility for inaccuracies which may occur and reserves the right to make changes to specification or design without prior notice. The information contained in this manual and all rights in any designs disclosed therein, are and remain the exclusive property of Matsushita Communication Industrial UK Ltd. Other patents applying to material contained in this publication: BULL CP8 PATENTS Comments or correspondence concerning this manual should be addressed to: Customer Support Department, Matsushita Communication Industrial UK Ltd., Colthrop, Thatcham, Berkshire. RG19 4ZD. ENGLAND 1998 Matsushita Communication Industrial UK Ltd.

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MCUK981201G8 Technical Guide

&217(176
1 INTRODUCTION
1.1 1.2 2.1 2.2 3.1 3.2 3.3 4.1 4.2 5.1 5.2 6.1 6.2 7.1 7.2 8.1 8.2 9.1 9.2 9.3 9.4 9.5 Purpose of this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Structure of the Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 10 RF & Accessory Connector . . . . . . . . . . . . . . . . . . . . . . 12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 13 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 15 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Functional Description of the PCB . . . . . . . . . . . . . . . . 21 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 29 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 33 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2 INTERFACES AND TEST POINTS 3 RF OVERVIEW

4 TRANSMITTER 5 RECEIVER 6 BASEBAND OVERVIEW 7 GEMINI 8 VEGA 9 POWER SUPPLIES

10 ACCESSORIES
10.1 Handsfree Unit - Circuit Description . . . . . . . . . . . . . . . 43 10.2 Dual Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

MCUK981201G8 Technical Guide

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Section iv

MCUK981201G8 Technical Guide

INTRODUCTION



,1752'8&7,21

3XUSRVH RI WKLV *XLGH
This guide contains technical information for the Panasonic GD70 personal cellular telephone system operating on the GSM network. Procedures for installing, operating and servicing (e.g. disassembly and testing) the telephone system are provided in the associated Service Manual.

6WUXFWXUH RI WKH *XLGH
The guide is structured to provide service-engineering personnel with the following technical information on the GSM mobile telephone:

1. 2. 3.

Interface details and relevant test points. Functional description of each section of the mobile telephone. Detailed description of each section of the mobile telephone.

MCUK981201G8 Technical Guide

Section 1 1

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INTRODUCTION

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Section 1 2

MCUK981201G8 Technical Guide

INTERFACES AND TEST POINTS



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This section provides details on connections between the RF and Baseband PCB and other interfaces on GD70.

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SIM 5 V SIM IO GND GND BATID BAT TEMP VBAT VBAT VBAT VBAT GND AFC GND PARAMP DQ DQX DI DIX PCNnGSM UQX UQ UIX UI GND OSC_13M 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SIM CLK GND SIM RST GND IFAGCEN PLL CLK PLL SD PLL STRB TX PLL EN GND NOT USED BUZZVIB ON OCE LO EN RXON2 RXON1 GND TXON1 PAON GND RF ON PLCONT GND GND

Figure:1

GD70 Interboard Connector

D70-0201

2.2.1 Baseband and RF
This details the 50-way connector between the RF and baseband PCB.
No. 1 2 3 4 5 6 Signal Name SIM_5V 5V_SIM_IO GND GND BAT_ID BAT_TEMP RF <=> LOGIC <== <=> ==> ==> ==> ==> Total 1 1 12 12 1 1 Function 5.0 Volt supply for SIM SIM Interface: Data Battery Ground Refer to pin 3 Attached battery type: Li+/No battery or NiMH Battery attached/detached detection, battery temperature monitoring Battery Supply Voltage Refer to pin 7 Refer to pin 7 Refer to pin 7 Refer to pin 3 Control voltage for 13 MHz TCVCXO VEGA pin 37 VEGA pin 38 H: Li or no battery L: NiMH H: Abnormal M: Li or NiMH L: No battery GEMINI pin 100 Connection Status 5 V 5% 20 mA max

7 8 9 10 11 12

VBAT VBAT VBAT VBAT GND AFC

==> ==> ==> ==> ==> <==

4 4 4 4 12 1

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INTERFACES AND TEST POINTS
No. 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 BUZZVIB_ON OCE LO_EN RXON2 RXON1 GND TXON1 PA_ON GND RF_ON PL_CONT GND GND <== <== <== <== <== <== ==> <== <== ==> <== <== ==> ==> 1 1 1 1 1 1 12 1 1 12 1 1 12 12 Buzzer On/Off control Vibrator On/Off control Downlink I/Q dc error offset calibration Enable VSVCO & VSTX Regulators, RF & IF Synthesizer IC Enable IF, Demodulator and Baseband stages Enable LNA and 1st Mixer & RF LO Buffer Refer to pin 3 Enable IF Modulator, APC loop Enable VSRF supply to TX buffers Refer to pin 3 Enable VSVCXO & VSRF Regulators Select sensitivity of PA Control Circuit Refer to pin 3 Refer to pin 3 H: Enabled L: Disabled H: Enabled L: Disabled H: Enabled L: Disabled H: Enabled L: Disabled H: Enabled L: Disabled H: Enabled L: Disabled H: Vibrator On L: Vibrator Off Signal Name GND PARAMP DQ DQX DI DIX PCNnGSM UQX UQ UIX UI GND OSC_13MHZ 5V_SIM_CLK GND 5V_SIM_RST GND IFAGCEN PLL_CLK PLL_DATA PLL_STRB TX_PLL_EN GND ==> RF <=> LOGIC ==> <== ==> ==> ==> ==> <== <== <== <== <== ==> ==> <== ==> <== ==> <== ==> <== ==> Total 12 1 1 1 1 1 1 1 1 1 1 12 1 1 12 1 12 1 1 1 1 1 12 Function Refer to pin 3 Ramping waveform for PA Control Circuit Downlink Q signal Downlink nQ signal Downlink I signal Downlink nI signal Select GSM1800 or GSM900 Mode Uplink nQ signal Uplink Q signal Uplink nI signal Uplink I signal Refer to pin 3 13 MHz Master Clock SIM Interface: Clock Refer to pin 3 SIM Interface: Reset Refer to pin 3 AGC Serial Interface: Enable PLL & AGC Serial Interface: Clock PLL & AGC Serial Interface: Data PLL Serial Interface: Enable Tx PLL Enable Refer to pin 3 GEMINI pin 61 H: Enabled L: Disabled H: Enabled L: Disabled GEMINI pin 62 H: Enabled L: Disabled GEMINI 3.25 MHz clock GEMINI pin 70 H: GSM 1800 L: GSM 900 Connection Status

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Section 2 4

MCUK981201G8 Technical Guide

R

switch
14 12
VOICEBAND I/F

VSVCXO 2.8V VSVCO 2.8V
SERIAL I/F PARAMP AFC D/A

VSTX 2.8V

VSRF 2.8V

23 22 21 20
SIGMA-DELTA

UI UIX UQ UQX

DSP I/F

MCUK981201G8 Technical Guide
17 18 15 16 CPU CORE DI DIX DQ DQX ARM CORE

PFD

N

PMB2251

TX/RX TX/RX ANT SW ANT SW 900 1800

VBAT 13MHz buffer
SLICER

PA GSM900

APC IC GSM900

TCVCXO

20 21 22 23 44 34 45 48 7,8 9,10 40 47 12 25 14 19
SLICER I/O

PA GSM1800 RF PLL PMB2347 IF PLL
25 13MHz

APC IC GSM1800

switch

switch

switch 33 PLL_STRB 14 PLL_CLK 19 PLL_SD

5 INPUT A/D

BUZZ BACKLIGHT + KEYPAD

Section 5
RLFO BUFFER
34 TXPLLEN 5 BATID 6 BATTERY 19 PCNnGSMO PLCONT 48 37 BUZZ

900

900

RFLO

1800

RFLO

1800

1800MHz LNA switch
44

VSRF

39 OCE 30 IFAGCEN 42 RXON 1 41 RXON 2

TXON 1 28V POWER SUPPLY 47 33 31 32 7,8 9,10 RF_ON PLLSTRB PLLCLK PLLSD VBAT CHARGE BATTERY & MONITOR CIRCUIT EXT PWR

PMB2333 LNASW 15 16 17 18

RX AUDIO TX AUDIO ACCESSORY CONNECTOR

PMB2411 PLUS Connections for battery management and SIM connections

INTERFACES AND TEST POINTS

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Figure:2

RF board and Interfaces

D70-0203

Figure:3

Logic board and Interfaces

D70-0202

INTERFACES AND TEST POINTS

2.2.2 External Interface
GD70 has two external connectors:

1. 2.

a multi-way connector for use with a handsfree data; additional contacts for charging the battery pack while in the desktop charger;

All interfaces are electrically and mechanically compatible with GD70.

Main Unit <==> External I/O
No. 1 Name GND H/H <=> EXT ==> Total 6 Function Ground
Pin 3

H/H Circuit
Battery Connector

2

PA_ON

==>

1

Gating of spectrum analyser for Transmitter performance testing L: Off, Hi - Z: On) Accessory Power Control signal. In the handsfree this is logical ORed with IGNITION in order that the software can maintain the Handsfree power-on state if the user is in a call and that the IGNITION is switched off. L: Power-on, Hi-Z: Power-off IGNITION is used in 2 cases. 1) Determine the mode of operation of the H/H when the Handsfree accessory is attached. L: At a suitable time enter dummy sleep mode and therefore minimise the drain on the car battery (nLOGIC_POWER = Hi - Z) H: Normal mode 2) Satisfy 2nd of 2 conditions for sending initialise Testset command and entering Testset mode. (see nADP_SENSE for 1st condition) L: Condition 2 satisfied H: Enter Testset mode not satisfied The pin is either an input or an output depending upon the battery connection. 1) Battery/Dummy battery connected: Output supply terminal for attached accessories. 2) No connection: Low current input supply terminal for non-RF performance checking in Testset Mode or Flash programming. Handsfree sense line L: connected H (internal pull-up): disconnected

100R PAGN 100n

3

NLOGIC_PWR

==>

1

330R

100n LOGIC_PWR

4

IGNITION

<==

1

Power On/Off Control Circuit Accessory Control Circuit

5

VBAT

<=>

1

Pin 1

Battery Connector

6

NH/F_SENSE

<==

1

2V8

100k 330R nHF_DETECT 100n

7

NRADIO_MUTE

==>

1

Radio Mute L: mute, Hi-Z: unmute)

330R RADIO_MUTE

8

RX_AUDIO

==>

1

Accessory Receiving Audio -16 dBm0 = 76.7m Vrms

560k Vega_AUXO 47k Memo_ANA IN+ 1 1

9 10

No connection EXT-PWR <== 2 Power supply for battery charging, Power ON/ Off control and accessory control circuits. Voltage: 5.8 0.2 V Current: 650 50 mA
Trickle Charge Circuit Power On/Off Control Circuit Rapid Charge Circuit Accessory Control Circuit

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MCUK981201G8 Technical Guide

INTERFACES AND TEST POINTS
No. 11 Name NON_HOOK H/H <=> EXT <== Total 1 Function Indicates if the optional second handset is on or off hook. In handsfree operation, if the optional handset is not fitted this signal defaults to on hook. (Low.) H/H Circuit
2V8

100k 330R nON_HOOK 100n

12

SERIAL_OUT

==>

1

Downlink Serial Data (Baud rate is same as SERIAL_IN)

2V8

330R Gemini_TXD 1n

13

SERIAL_IN

<==

1

Uplink Serial Data The baud rate is dependant upon the attached accessory, whether operating in Testset Mode or Flash Downloading. SMS cable: 9600 bps RS232 Direct cable: 38.4 kbps Data adapter: 33.8 kbps Testset: 9600 bps Flash Download: 56 kbps NADP_SENSE has 5 possible states. The state is determined by the value of the pull-down resistor in the attached accessory/testset. NADP_SENSE has 2 purposes as follows: 1) To identify an attached accessory. Open (H): No attached accessory 82 k 1% (MH): Headset Adapter 56 k 1% (M): SMS Cable 33 k 1% (ML): RS232C Direct Cable GND (L): Data Adapter 2) Determine whether the 1st of 2 conditions are satisfied for sending the initialise Testset command on SERIAL_OUT, and entering Testset mode (see IGNITION for 2nd condition). H/MH: Condition 1 satisfied M/ML/L: Enter Testset Mode not satisfied Accessory Sending & Receiving Audio paths unmute L: unmute, Hi-Z: mute Refer to pin 1 Accessory Sending Audio -16 dBm0 = 40.4 m Vrms

2V8

10k 330R Gemini_RXD 1n

14

NADP_SENSE

<==

1

2V8

100k 1% 330R Vega_ADIN3 100n

15

NH/F_ON

==>

1

330R HF_ON 100n

16 17

GND TX_AUDIO

==> <==

6 1

Refer to pin 1
10k Vega_AUXI Memo_AUDIOUT n HFTX_MUTE 1 1 3k3 1

18 19 20 21 22

GND GND GND GND CHARGE_ON

==> ==> ==> ==> <=>

6 6 6 6 1

Ground connection of Dual Charger Ground connection of Dual Charger Ground connection of Dual Charger Ground connection of Dual Charger The Dual Charger shall hold CHARGE_ON to the middle level unit a H/H is inserted into the front slot. H: 2.0<=V<=3.0 volts; Dual Charger detects connection of H/H M: 1.0<=V<2.0 volts; Unconnected L: 0.0<=V<1.0 volts; Dual Charger detects connection of H/H The Dual Charger shall control switching of the power supply to the front slot (corresponds to EXT_PWR) based on the state of the CHARGE_ON signal. H: EXT_PWR supplied L: When the H/H can determine whether or not to set CHARGE_ON. After the insertion of the H/H, EXT_PWR shall be subsequently supplied withinTBA hours

Refer to pin 1 Refer to pin 1 Refer to pin 1 Refer to pin 1

330R CHARGE_ON 1 100k

23

EXT_PWR

<==

2

Refer to pin 8

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INTERFACES AND TEST POINTS

Battery Connector
No. 1 Name VBAT H/H <=> EXT <== Total 1 Function Positive battery terminal. Li+ (2 cells in parallel): 3.6 V nom. NiMH (3 cells in series): 3.6 V nom. BAT_TEMP has 2 purposes. 1) Determine whether a battery is attached to the H/H. 2) Monitor battery temperature for the purposes of charging. H: Abnormal battery M: Li+ or NiMH charging L: No battery or abnormal battery Negative battery terminal H/H Circuit

2

BAT_TEMP

<==

1

ChargerIC VREFOUT

22k ESD Vega_ADIN2 100n ESD Protection

3

GND

<==

1

4

BAT_ID

<==

1

BAT_ID is used to identify the type of attached battery. H: Li+ or no battery L: NiMH

See charging ASIC specification

SIM Interface
Pin 1 2 3 4 5 6 7 8 Signal GND 5V Not connected Reset Serial input/output Clock Not connected Not connected

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MCUK981201G8 Technical Guide

RF OVERVIEW



5) 29(59,(:

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3.1.1 General Specifications
GD70 is a Dual Band Product incorporating two switchable transceivers one for GSM900 and another GSM1800 band. The transmit and receive bands for the mobile are given in the table below:
Tx GSM900 GSM1800 890-915 1710-1785 Rx 935-960 1805-1880

Other salient technical features are as follows:
GSM900 Rx Bandwidth Tx Bandwidth Duplex Spacing Number of Channels ARFCN (Channel Numbers) 1st Tx Channel Last Tx Channel 1st Rx Channel Last Rx Channel Maximum Tx Power Minimum Tx Power 25 25 45 124 1-124 890.2 914.8 935.2 959.8 33.0 (Class 4) (PL5) 5.0 (PL19) GSM1800 75 75 95 374 512-885 1710.2 1784.8 1805.2 1879.8 30.0 (Class 1) (PL0) 0.0 (PL15) MHz MHz MHz MHz dBm dBm Units MHz MHz MHz

3.1.2 Description of RF PCB
All the RF circuitry is contained on one PCB. The RF PCB has six layers made from FR4 material (Epoxide woven glass fabric copper-clad laminate as specified in BS4584 Part 102 and prepeg as specified in BS4584 Part 103). Top and bottom layer tracks are gold-plated to prevent oxidisation and enable better soldering. The board thickness is 0.9 mm ( 0.1 mm). The majority of the components are on one side of the PCB leaving as much as possible of the opposite side to be a complete ground plane; this is used to provide RF shielding. The RF board is connected to the baseband digital board via a 50-way dual in-line connector. A metallised plastic chassis is used to separate the RF and the Logic PCB's. When the chassis is sandwiched between the RF and the Logic PCB's the ground plane of the RF board together with the chassis forms an effective shielded enclosure which prevents spurious emissions. The chassis has also been designed to provide smaller walled sections which are used to isolate sensitive RF areas such as the VCTCXO and the VCO from high level interferers such as the PA output.

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RF OVERVIEW

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The major building blocks for the RF design are the Siemens transmit (Tx) and receive (Rx) ICs, Fujitsu RF-IF dual PLL and the antenna subsystem.

Figure:1

RF Block Diagram

D70-0301

3.2.1 Frequency Plan
The GD70 frequency plan is shown below.
Tx GSM900 GSM1800 890-915 1710-1785 Rx 935-960 1805-1880 Tx IF 327 187 Rx IF 282 282 RFLO Tx 1217-1242 1523-1598 RFLO Rx 1217-1242 1523-1598

Fcomp(MHz) GSM900 GSM1800 109 93.5

R 5 6

N 3 2

Tx IF LO(MHz) 545 561

Rx IF LO(MHz) 564 564

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MCUK981201G8 Technical Guide

RF OVERVIEW

RX IF = 282MHz

935-960 IF LO Frx = 564MHz Fdiff 327MHz Fdiff 327MHz

RF LO 1217-1242MHz

1/3 IF LO Ftx = 545MHz

1/5

Fcomparison = 109MHz

TX VCO 890-915MHz

Figure:2

GSM 900 frequency plan

D70-0302

3.2.2 Functional Description of the PLLs

1st Local Oscillator
The 1st local RF Oscillator runs from 1217 MHz to 1598 MHz depending on the mode of operation.

Figure:3

1st Local Oscillator

D70-0303

U404 is a dual PLL IC. The reference signal is generated by the 13 MHz clock and received on pin 2. The output from pin 9 on the U404 drives the VCO. U405 is the RF VCO, whereby the input from pin 6 controls the frequency of oscillation. The output of the VCO is from pin 1. This output is split, with one feed going back into the loop and the other to the amp TR402. From the output of TR402 there are three feeds: a. GSM 900 receiver; b. GSM 1800 receiver; c. Transmitter. In GSM 900 mode (a) the oscillator operates from 1217 MHz to 1242 MHz. In GSM 1800 mode (b) the oscillator operates from 1523 MHz to 1598 MHz. The output from the transmitter (c) will be the same as the receiver mode (a) or (b).

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RF OVERVIEW

2nd Local Oscillator
The 2nd local RF Oscillator operates at three frequencies 545, 561 and 564 MHz.

Figure:4

2nd Local Oscillator

D70-0304

U404 is a dual PLL IC. The reference signal is generated by the 13 MHz clock and received on pin 2. The output from pin 8 on the U404 drives the VCO. TR102 and associated components form the VCO, whereby the output feeds the amplifier U103. This output from the U103 is split into three, with an Rx & Tx feed being returned to the PLL IC. The 2nd local oscillator operates at the following frequencies: GSM 900 transmitter = 545 MHz; GSM 1800 transmitter = 561 MHz; Receiver = 564 MHz.

3.2.3 Antenna
The antenna is a fixed helical type. A mechanical RF switch is used to route the RF signal from the external antenna for handsfree operation and test purposes.

3.2.4 Transmit and Receive
The transmit and receive paths of GD70 are covered in their own specific chapters later in this manual.

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In previous models the RF signal is routed to the accessory connector which contains a micro-switch. If the switch is open the RF signal is routed to the handsfree unit, if closed the signal is routed back up the RF PCB to the antenna. This routing of the RF signal up and down the RF PCB invariably has a finite power loss associated with it. In addition the GD70 has a limited PCB area and the routing of the RF signal in this way reduces further the available PCB area required for the Dual Band circuit. To alleviate these problems the RF connector is located close to the PA module. This reduces the loss and hence the PAs do not have to be driven so hard. This allows the power supply voltage to be lower, thus improving battery performance.

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MCUK981201G8 Technical Guide

TRANSMITTER



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This section provides a technical description of the transmitter circuit of the RF circuit. A circuit diagram of the whole system is provided in the Service Manual (MCUK981201C8). The uplink frequencies for the GSM 900 and GSM 1800 can be calculated as follows:

4.1.1 Uplink Frequencies GSM 900
Uplink frequency = 890 MHz + (ARFCN x 0.2 MHz) e.g. for CH55 890 MHz + (55 x 0.2 MHz) = = 890 MHz + (11 MHz) 901 MHz

4.1.2 Uplink Frequencies GSM 1800
Uplink frequency = 1710 MHz + ((ARFCN - 511) x 0.2 MHz) e.g. for CH512 1710 MHz + ((512 - 511) x 0.2 MHz) = = 1710 MHz + (0.2 MHz) 1710.2 MHz

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Figure:1

Transmitter

D70-0401

The transmitter design is based on an IQ Modulator. The architecture has been carefully chosen to enable the GSM transmitter noise in receiver band requirements to be met without the need for a duplexer. This was a very important consideration in the design of the transmitter as the area required by two duplexers would be too large for the radio design to fit in the desired small area. The Modulation loop uses a modular VCO which contains two VCOs, one for the 900 MHz band and the other for the 1800 MHz band. The required VCO is selected by a control line, PCNnGSM. The output from the Tx VCO is split into two, one feeding the mixer within the modulation loop and the other feeding the PA through a PA buffer and bypass filtering. There are resistive pad s before the PAs and the PA buffer to help with impedance matching and level adjustment. MCUK981201G8 Technical Guide Section 4 13 Issue 1 Revision 0

TRANSMITTER
A discrete diplexer is used after the PA buffer which provides low pass filtering for the 900 MHz band and high pass filtering for the 1800 MHz band. The switching between the receiver and the transmitter for any band is achieved by means of pin diode switches. The antenna ports of these switches are connected to the antenna or the handsfree RF connector. The handsfree connector incorporates a mechanical switch which enables the signal to be routed either to the antenna or to the handsfree connector depending on the operation required. The RF LO is also a modular VCO which contains two VCOs, one for the 900 and the other for the 1800 MHz bands. The operation is similar to the Tx VCO in that the required RF VCO is switched by two control lines. The IF VCO is a discrete design. Both the RF and IF LOs are designed around a dual PLL with the IF frequency range up to 600 MHz and the RF frequency range up to 2 GHz. The 13 MHz oscillator design, similar to all of the previous designs, employs a modular TCVCXO with a buffer. The operation is similar to that of the G600 where the buffer is switched off during idle mode to increase the standby time.

4.2.1 GSM1800 Frequency Plan

Figure:2

Frequency Plan

D70-0402

Two advantages of the new frequency plan are the narrower tuning range requirement for the IF VCO and a high IF frequency for the GSM1800 to enable better filtering of the 3rd harmonic of the Tx IF signal. In either band, GSM900 or GSM1800, the Rx IF is fitted at 282 MHz. Therefore, the 2nd LO is at 564 MHz for receiver modes. For this choice of IF, no receiver blocking is believed to occur due to harmonics of 13 MHz, 3.25 MHz, harmonics of 282 MHZ falling into the Rx bands or due to harmonics of the 2nd LO mixing with harmonics of the 1st LO and causing blocking signals to occur in any Rx channel. In GSM900 transmit mode, the 2nd LO is reprogrammed to 545 MHz via the auxiliary synthesizer. Since this is close to 564 MHz, it should not be necessary to switch an inductor to do this - the resonator should have sufficient range to cover both of these frequencies. In GSM1800 transmit mode, the 2nd LO is reprogrammed to 561 MHz. This is even closer to the Rx frequency of 564 MHz and should not present a problem. The 1st LO provides low-side injection for the GSM1800, since the PMB2251 mixer ports are only specified up to 2 GHz, also the RF input port of the MB15F03SL only increases up to 1.8 GHz. The Tx VCO will be the on-channel in either the GSM900 or GSM1800 modes of operation. The RF LO should not normally require re-tuning between transmit and receive modes, but only when monitoring adjacent cells.

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RECEIVER



5(&(,9(5

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This section provides a technical description of the receiver section of the RF circuit. A circuit diagram of the whole system is provided in the Service Manual (Order No. MCUK981201C8). The downlink frequencies for the GSM 900 and GSM 1800 can be calculated as follows:

5.1.1 Downlink Frequencies GSM 900
Downlink frequency = 935 MHz + (ARFCN x 0.2 MHz) e.g. for CH55 935 MHz + (55 x 0.2 MHz) = = 935 MHz + (11 MHz) 946 MHz

5.1.2 Downlink Frequencies GSM 1800
Downlink frequency = 1805 MHz + ((ARFCN - 511) x 0.2 MHz) e.g. for CH512 1805 MHz + ((512 - 511) x 0.2 MHz) = = 1805 MHz + (0.2 MHz) 1805.2 MHz

)XQFWLRQDO 'HVFULSWLRQ
The main building block for the Dual Band Receiver is the Siemens IC PMB411 V1.1. The receiver is a double superhet type with the first IF at 282 MHz (IF path common to both frequency bands).

GSM 900 MHz 2nd RX FILTER IF SAW

Baseband Amps IF Amps

Baseband Filtering I IB

LPF SW200

Rx

LNA

1st Mixer

Tx FL102 H/F HPF Rx

ON BOARD V100 LNA

FL101 2nd RX FILTER

FL100

V100

Q QB

Tx FL103

V102

FL104

FL104

GSM 1800 MHz

Figure:1

Receiver IC PMB411 V1.1

D70-0501

The Rx IC contains the following stages:

1. 2. 3. 4. 5.

GSM900 LNA. GSM900 RF mixer. Gain controlled 5-stage IF amplifier. I,Q quadrature down converter. Baseband Op Amps for further amplification and some filtering of the baseband I,Q signals.

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RECEIVER

5.2.1 GSM900

Rx LPF Tx FL102

LNA

2nd RX FILTER

1st Mixer

ON BOARD V100

FL101

Figure:2

GSM900 Receiver

D70-0502

RF input to the receiver is either via the antenna or via the H/F RF connector for test purposes. The input signal from the antenna or the H/F RF connector is fed into the GSM900 onboard LNA through the GSM900 LPF Diplexer port, through the GSM900 Tx/Rx switch and finally through the unbalanced GSM900 Rx SAW filter. The diplexer band splits the two GSM frequency bands whilst the pin switches route the signal flow from the receiver and the transmitter as required. The receiver 1st SAW filter provides the roofing filter for the Rx front end. The LNA gain can be controlled via a three-wire bus between a typical value of 19 dB and approximately -3 dB. The LNA gain reduction is required for operation under strong signal conditions where input power levels are greater than about -40 dBm. Typical NF for the LNA is 2.4 dB and the third order intercept point at its input is -4 dBm. The output from the LNA goes through a differential BP SAW filter and is differentially fed into the 1st down-converter mixer. The mixer has a third order intercept point of -2 dBm with a maximum SSB noise of 9dB. The LO for the mixer is generated by a PLL (Fujitsu MB15F03SL) employing a modular VCO. The output from the VCO is buffered by an RF MMIC amplifier. The LO frequency range for the GSM900 is 1217 to 1242 MHz. The IF output at 282 MHz from the mixer is filtered by the differential IF SAW filter before it is fed into the gain-controlled IF amplifiers. The use of differential filters eliminates the need for baluns and provides some cost and space advantage. The IF amplifier is a five stage cascaded section. The gain is controllable by a three-wire bus from -10 to +70 dB in 2 dB steps. This function is used for AGC purposes. The output from IF amplifiers is fed into two quadrature mixers where it is converted down to baseband. The IF LO is generated at 564 MHz by an external discrete VCO. An on-chip divider on the Rx IC divides this by two and also produces two outputs in quadrature to generate the baseband I and Q signals. The outputs from the mixers are connected to external pins through a pair of buffers. Two on-chip Op Amps are used to amplify the AC signal from the mixers to meet the overall signal budget requirements. The DC level at the output of the Op Amps is 0.95 V with a 1.25 Vpp single ended AC swing sufficient to drive the baseband IC VEGA (see Section 8). The coupling between RF output and the baseband input has been designed as a DC coupling in order to minimise the turnon time of the Rx IC for the purpose of current optimization.

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RECEIVER

5.2.2 GSM900 Signal Levels
The signal levels through the receiver IC for the GSM900 are given below.

Figure:3

GSM900 Nominal and Worst Case Signal Levels

D70-0503

MCUK981201G8 Technical Guide

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RECEIVER

5.2.3 GSM1800

Rx HPF Tx FL103

LNA

2nd RX FILTER

V102

FL104

FL104

Figure:4

GSM1800 Receiver

D70-0504

RF input to the receiver is either via the antenna or via the H/F RF connector for test purposes. The input signal from the antenna or the H/F RF connector is fed into the GSM1800 external LNA through the GSM1800 LPF Diplexer port, through the GSM1800 Tx/Rx switch and finally through the unbalanced GSM1800 Dielectric filter. The diplexer band splits the two GSM frequency bands whilst the pin switches route the signal flow from the receiver and the transmitter as required. The receiver Dielectric filter provides the roofing filter for the Rx front end. The LNA gain can be controlled via a three-wire bus on the PMB2411between a typical value of 18 dB and approximately -19 dB. The LNA gain reduction is required for operation under strong signal conditions where input power levels are greater than about -40 dBm. Typical NF for the LNA is 2.0 dB and the third order intercept point at its input is -5 dBm. The output from the LNA goes through an unbalanced BP SAW filter and is differentially fed into the 1st down-converter mixer, via a single-ended to differential matching network. The mixer has a third order intercept point of -1 dBm with a maximum SSB noise of 11dB. The LO for the mixer is generated by a PLL (Fujitsu MB15F03SL) employing a modular VCO. The output from the VCO is buffered by an RF MMIC amplifier. The LO frequency range for the GSM1800 is 1523 to 1598 MHz. The IF output at 282 MHz from the mixer is then fed into the common IF path as previously described for the GSM900.

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RECEIVER

5.2.4 GSM1800 Signal Levels
The signal levels through the receiver IC for the GSM1800 are given below.

Figure:5

GSM1800 Nominal and Worst Case Signal Levels

D70-0505

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BASEBAND OVERVIEW



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All Baseband circuitry is contained on one PCB. The Baseband PCB has six layers made from FR4 material. Top and bottom layers are gold-plated to prevent oxidisation and enable better soldering. The board thickness is 1.0 mm (+0.0, -0.1 mm). The Baseband board is connected to the RF board via a 50 way dual in line connector. A metallised plastic chassis is used to separate the Baseband and the RF PCBs. The continuous chassis design is important for EMC purposes. When the chassis is sandwiched between the Baseband and the RF PCBs the ground plane of the RF board together with the chassis forms an effective shielded enclosure, which prevents spurious emissions.

)XQFWLRQDO 'HVFULSWLRQ RI WKH 3&%
The GD70 baseband is based around a 2 chip GSM chipset developed by Texas Instruments. One chip (GEMINI) carries out signal processing with DSP and CPU, and the other chip (VEGA) contains the analogue interface chip. The highly integrated nature of these components means each contain a large number of functions.
GEMINI LEAD Megamodule JTAG TEST & EMULATION TEST & ROM EMULATION & RAM IRQ SYSTEM SIMULATOR DATA ADAPTER TESTSET TEST MOBILE SIM CARD DAI RST CPU CORE API PLL & CLOCKS XIO XIO DSP SERIAL I/F BURST DIFF STORE ENCODE GMSK MOD 8-Bit I DAC 8-Bit Q DAC LPF LPF ULI ULQ INTER PCB CONNECTOR SYSTEM SIMULATOR VEGA

FILTER FILTER

SIGMA-DELTA SIGMA-DELTA

ANTIALIASING FILTER ANTIALIASING FILTER APC (D/A)

DLI DLQ PARAMP AFC

SPI

nLVA_INT ACCESSORY CONNECTOR

APIF UART 5V DC/DC CONVERTER + LEVEL SHIFTER TPU T S P

MCU SERIAL I/F

INTH

INTERNAL REGISTERS

AFC (D/A) DAI

INTER PCB CONNECTOR

SIM I/F

ARM CORE

TDM TIMEBASE TIMER

A C T

VOICEBAND SERIAL I/F

BPF

SIGMA-DELTA

LPF

BPF

SIGMA-DELTA

VIBRATOR

I/O MICROWIRE I/F BUZZER BACKLIGHT POWER ON/OFF CONTROL & POWER SOURCE FAILURE CIRCUIT VOICE MEMO EEPROM 2K*8 FLASH 1M*16 SRAM 256K*8 LCD EXTENDED OUTPUT TRICKLE CHARGE CIRCUIT MEMORY I/F CLKM SLICER SLICER 5 INPUT 10-BIT A/D AGC (D/A) TEST

BAT_VOLT CURRENT

KEYPAD

RAPID CHARGE & BATTERY MONITORING CIRCUIT

VSET JTAG

IGNITION nHF_SENSE nLOGIC_PWR

BAT_ID BAT_TEMP

INTER PCB CONNECTOR

ACCESSORY CONNECTOR

BATTERY

Figure:1

Baseband Block Diagram

MCUK981201G8 Technical Guide

Section 6 21

TX_AUDIO RX_AUDIO

EXT_PWR

13MHz

VBAT

D70-0601

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BASEBAND OVERVIEW

6.2.1 Keypad
The Keypad has a 5 x 5 matrix allowing 25 keys to be scanned on a key being pressed, a keypad interrupt is generated. To find which key is pressed the software must assert each column in turn and read which row is active. To eliminate key bounce, the key press must then be confirmed twice at about 20 ms intervals. The Keyboard scanning is software controlled. Key pressed is indicated by an interrupt, but key release is controlled by software.

KBR(0:4) 4 TP74 KBC(0:4) * TP69 S401 0 0 TP70 S402 1 TP71 S403 2 OK TP72 S404 3 CLR TP73 S405 4 TP29 D3 nPOWKEY RB512S-30TE61 S421 D18 MAZS0470GL PWR/END 3 VOICE_MEMO 4 1 2 S410 S415 S420 > v PB S409 S414 S419 < v SND S408 S413 S418 9 6 3 S407 S412 S417 8 5 2 S406 S411 S416 7 4 1 TP75 3 TP76 2 TP77 1 0 TP78

Figure:2

Keypad Matrix

D70-0602

6.2.2 Subscriber Identity Module (SIM)
The SIM interface is designed to support 5 V SIMs. The GD70 GEMINI process is unable to support 5 V tolerant inputs. Therefore, in order to Interface GEMINI with a 2.8 V supply, and the SIM with a 5 V supply, it is necessary to include a level shift. U3 is able to perform the required level shift. In addition the device includes a switched capacitor charge pump DC/DC converter to generate the 5 V SIM supply from VBAT.

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BASEBAND OVERVIEW

6.2.3 Time Processing Unit (TPU)
The TPU provides the GSM TDMA timing requirements for the system, external timing signals are provided by an area of Microcode within the GEMINI chip.
GEMINI Pin 65 71 67 68 69 70 118 119 58 59 64 61 62 Description VEGA BENA VEGA OCE VEGA BULON VEGA BDLON PA_ON PCNnGSM RF signal RXON1 RF signal RXON2 VEGA_SEL PLL_STRB RF signal TXON1 TX_PLL_EN IFAGCEN

6.2.4 CPU Memory
The memory requirements for GD70 are:

1. 2. 3.

16 Mbit 3 V FLASH organised as 1M * 16; 2 Mbit 3 V RAM organised as 256k * 8; 16 kbit 3 V Serial EEPROM as 2k * 8.

6.2.5 LCD
The LCD assembly is a subassembly comprising of LCD glass and driver chip on a flexible PCB with connection to the Logic PCB via zebra strip connections. A 96 x 58 pixel graphical display is used to give maximum information. It can also display Chinese characters and large numbers. For example, 12 x 2 line or 16 x 3 line, both with 2 lines of icons.

Figure:3

LCD Dimensions

D70-0603

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BASEBAND OVERVIEW

6.2.6 Microphone
The microphone is an omni-directional type as used with previous models. GSM requires that when in Handheld use the sending audio frequency response must fit within the mask shown below.

5 dB 0

-5

-10

-15 100

1000

Frequency (Hz)

10000

Figure:4

Handheld GSM Transmit Audio frequency response mask

D70-0604

When using the Handsfree feature GSM requires that the sending audio frequency response must fit within the mask shown below.

5 dB 0

-5

-10

-15 100

1000

Frequency (Hz)

10000

Figure:5

Handsfree GSM Transmit Audio frequency response mask

D70-0605

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BASEBAND OVERVIEW

6.2.7 Speaker
To meet Handsfree volume requirements with a single Li+ battery, a low impedance (dynamic) type must be used. GSM requires that the receive audio frequency response in Handheld use must fit within the mask shown below. GD70 is designed to meet Handheld requirements with a type 1 artificial ear.
5 dB 0

-5

-10

-15 100

1000

Frequency (Hz)

10000

Figure:6

Handheld GSM Receive Audio frequency response

D70-0606

Volume levels Volume level 1 2 3 4 PGA 3dB 0dB -3dB -3dB Volume 0dB 0dB 0dB -6dB Total Gain 3dB 0dB -3dB -9dB

When using the internal Handsfree feature, the receive audio frequency response must fit within the mask shown below.

0 dB

-5

-10

-15 100

1000

Frequency (Hz)

10000

Figure:7

Handsfree GSM Transmit Audio frequency response mask

D70-0607

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BASEBAND OVERVIEW

6.2.8 Internal Handsfree
In Handheld mode the speaker is driven by the ear-piece amplifier inside VEGA. For internal Handsfree operation, the ear-piece amplifier is disabled and the speaker is driven using an external power amplifier via the auxiliary speaker output in VEGA. The power amplifier can be enabled and disabled by the INTERNAL_HF signal.

EARP Vega EARN

AUXO Power Amp INTERNAL_HF

Figure:8

Speaker connection for Handheld and Handsfree use

D70-0608

6.2.9 Buzzer
The volume level of the buzzer is defined by the 6 bit PWM register setting in GEMINI I/O. The buzzer tone is then superimposed on this level using software. Timer 1 in GEMINI is used to time the period between switching the buzzer on and off to make the tone. For more complex buzzer ringing tones, the buzzer volume level can also be altered after each time-out of timer 1.

Figure:9

Buzzer Control Circuit

D70-0609

6.2.10 Timers
Two 16 bit general purpose timers which can be used either as auto-reload or 1 shot timers to provide interrupts to the ARM CPU. The timer clock duration is defined by a prescaler and 16 bit register. The Timer unit receives a 928 kHz clock from the GEMINI clock module. A combination of prescaler and timer register gives a time range of 1.078 sec to 9.039 sec.

Timer 1 2

Function Buzzer Timer Watch Dog Timer

Setting Tone frequency 3 sec

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BASEBAND OVERVIEW

6.2.11 USART
The serial port is compatible with an Intel 8251 and has six pins.

USART Pin Assignments Signal Name TXD RXD DTR DSR TXE RXE Pin No. 113 111 114 110 115 116 Function USART serial data Tx USART serial data Rx Used as I/O pin Used as I/O pin Used as I/O pin Used as I/O pin I/O O I O I O O

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MCUK981201G8 Technical Guide

GEMINI



*(0,1,

,QWURGXFWLRQ
Gemini contains the DSP, CPU and GSM timing functions and many peripheral functions. The software for the DSP is contained in masked ROM.

)XQFWLRQDO 'HVFULSWLRQ
TIMERS BASEBAND INTERFACE GSM TDMA TIMER TPU SPEECH INTERFACE UART ARM I/O SERIAL I/F MEM I/F

PWM

DSP CORE

DSP ROM

DSP RAM

JTAG

SIM I/F

Figure:1

GEMINI Block Diagram

IRQ

INTERFACE

600-0701

7.2.1 Digital Signal Processor
The Digital Signal Processor (DSP) core is compatible with the Texas Instruments TMS350C5xx family of DSPs. Included in the DSP core is an interface to the CPU by a shared memory interface. The DSP memory is also located within GEMINI. The ROM code size is determined by the size of the software.

7.2.2 CPU
The CPU is a 32 bit RISC CPU with 16 bit instruction set. The CPU is designed to access 32 bit memory and peripherals; a further module within the GEMINI chip allows access to 8 or 16 bit memory.
Memory Access Times Clock Speed 19.5 MHz 13 MHz 9.75 MHz 6.5 MHz 4.875 MHz 3.75 MHz Memory Access Time 41 ns 67 ns 91 ns 144 ns 194 ns 298 ns Additional Access time per wait state 51 ns 77 ns 102 ns 154 ns 204 ns 308 ns

For 120 ns access FLASH and RAM a 13 MHz clock gives 1 wait state access to both devices.

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GEMINI

7.2.3 Memory Interface
The memory interface allows the 32 bit CPU to access 16 and 8 bit devices, and allows the addition of wait states to memory access. The memory interface allows between 0 and 7 wait states to be added. The ROM area is hardware write protected, a FLASH write enable bit in the ROM wait state configuration register can be used to enable write access the ROM area.
CPU Memory MAP Device Name ROM RAM BUS CNTRL API RAM TPU RAM APIC SIM TSP INTH TPU REG CLKM TIMER APIF UWIRE ARMIO 8251 CS2 nCS0 nCS1 Start address 0000:0000 0020:0000 0040:0000 0050:0000 0050:4400 0050:4000 0050:4800 0050:4C00 0050:5000 0050:5400 0050:5800 0050:5C00 0050:6000 0050:6400 0050:6800 0050:6C00 0060:0000 0080:0000 00A0:0000 Size 2M 2M 1M 8k 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 2M 2M 2M Use FLASH 1 Mbytes RAM 256 kbytes wait state registers CPU/DSP shared ram GSM timer Microcode RAM CPU/DSP interface controller SIM interface Timed Serial port Interrupt controller GSM timer registers Clock control module software timers ARM peripheral interface Synchronous Serial port Keypad, buzzer, LCD & I/O UART LCD driver Extended I/O not used Bus width 16 bits 8 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bit 16 bit 16 bit 16 bit 16 bit 8 bit 8 bit -

7.2.4 Interrupt Handler
The ARM CPU has 2 interrupts, FIQ is a Fast non-maskable interrupt and IRQ is a standard maskable interrupt. Gemini has 11 interrupt sources. The Interrupt handler assigns priorities to these interrupts and routes them to either the FIQ or IRQ inputs of the ARM CPU. Additionally, the interrupt handler controls waking up of the CPU on receiving an unmasked interrupt, if the CPU is in sleep mode. For GD70 the FIQ interrupt is reserved for the power supply fail priority interrupt.
Interrupt Level Assignments Interrupt source IRQ_TIM1 IRQ_TIM2 IRQ_API IRQ_EXT IRQ_USART IRQ_ARMIO IRQ_FRAME IRQ_PAGE IRQ_TIM_GSM IRQ_TSP IRQ_SIM IRQ_F_USART IRQ_RSS Timed serial port Interrupt SIM Interrupt Fast interrupt from USART Radio subsystem interrupt Description Buzzer timer operating system timer DSP Interface interrupt Power supply fail interrupt UART Interrupt Keypad Interrupt Frame Interrupt Page Interrupt Interrupt detection Edge sensitive Edge sensitive Edge sensitive Level sensitive Level sensitive Low for 1 clk period Edge sensitive Edge sensitive Edge sensitive Edge sensitive Level sensitive Level sensitive Edge sensitive

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GEMINI

7.2.5 General Purpose I/O
The general purpose I/O includes keypad scanning, 2 PWM ports and 16 general purpose I/O lines. The general purpose I/O lines are multiplexed onto other functions, if I/O is selected the other function is unavailable.
I/O Pin Assignments Signal Name I/O 0: NLCDCS I/O 1: RXE I/O 2: TXE I/O 3: DTR I/O 4: DSR I/O 5: EXTINT I/O 6: NRSTOUT I/O 7: SIM_RnW I/O 8: SIM_PWCTRL I/O 9: SIM_CD I/O 10: LT I/O 11: ARMCLK I/O 12: TSPACT(0) I/O 13: NPWRCS I/O 14: nCS1 I/O 15: nCS0 Pin No. 117 116 112 114 110 109 106 105 104 95 134 73 65 56 50 48 IO_CTRL 0 1 1 1 1 0 1 1 1 1 0/1 1 0 1 X 0 Function Status H = PSU kept on L = PSU off H = Handsfree On L = Handsfree Off H = IGNITION Off L = IGNITION On H = Low RF Power level L = High RF power level H = Charging LED on L = Charging LED off H: SIM 5V Enable L: SIM 5V Disable H = Off hook 2nd Handset L = On hook 2nd Handset Backlight On: LT (PWM) Backlight Off: I/O (10) = Low H = No Hands Free L = Hands Free connected I/O N/A O 1 O I N/A O O O I O I N/A O N/A N/A

WIRE_VOICECS
LOGIC_PWR nEXT_PWR HF_ON nIGNITION nLVA_INT PL_CONT CHARGE_LED SIM_PWRCNT nON_HOOK LT nHF_DETECT BENA VEGA_PWDN N/C nCS0

Specific I/O are reserved for the backlight, buzzer and keyboard. The luminosity of the backlight and the loudness of the buzzer are controlled by a PWM (Pulse Width Modulation). The PWM are outputs only.
I/O Pin Assignments Signal LT BU Gemini Pin 134 120 Use LED backlight 6 BIT PWM Buzzer 6 BIT PWM

The PWM is clocked at 13/3 MHz. Tones are generated by using timer 1 to switch the buzzer PWM on and off at the frequency of timer 1. By altering the value of timer 1 ringing tones can be played. During Handsfree operation the ringing tone is derived from the DSP using its tone generator.

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VEGA



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VEGA contains the interface circuits to the Audio, RF and auxiliary analogue functions for the baseband circuit.

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TIMING 10 bit I DAC 10 bit Q DAC

JTAG FILTER

SIGMA DELTA

BURST STORE

GMSK MOD

FILTER FILTER FILTER SIGMA DELTA

FILTER FILTER

8 bit SIGMA-DELTA 8 bit SIGMA-DELTA 8 bit DAC 13 bit DAC

10 bit DAC

RAMP DATA

8 bit DAC

SP INTERFACE

DSP INTERFACE

Figure:1

VEGA Block Diagram

600-0801

8.2.1 Uplink I and Q
VEGA performs GMSK modulation on Data samples received from GEMINI at 270 kbits per second.

Timing interface

Din

Burst Register

Burst Timing Control

Offset Register

270 kHz Cosine Table Differential Encoder Gaussian Filter Integrator Low Pass Filter ULIP ULIN

8 bit DAC

phase(i) 16 *270 kHz Sine Table 8 bit DAC Low Pass Filter ULQP ULQN

Power Register

Ramp-up Shaper

Offset Register To Power control DAC

Figure:2

Functional structure of the baseband uplink path

600-0802

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VEGA

8.2.2 Downlink I and Q

Offset Calibration

Offset Register SUB

DLIP DLIN

Antialiasing Filter

Sigma_Delta Modulator

SINC Filter

FIR Filter To baseband serial interface

fs1=6.5 MHz

fs2=1.08 MHz

fs3=270.8 kHz

DLQP DLQN

Antialiasing Filter

Sigma_Delta Modulator

SINC Filter

FIR Filter SUB

Offset Calibration

Offset Register

Figure:3

Functional structure of the baseband downlink path

600-0803

8.2.3 Power Amplifier Ramp
The PA Ramp is formed by 2 D/As. The first, a 5 bit D/A, defines the ramp shape; the second, an 8 bit D/A, defines the maximum level. The ramp shape is defined by 64 steps. The shape can be defined differently for rising and falling ramps. Typically a raised cosine shape will be used as a starting basis of the ramp shape.

Ramp Down
35.00 35.00

Ramp Up

30.00

30.00

25.00
5 bit D/A Value 5 bit D/A Value

25.00

20.00

20.00

15.00

15.00

10.00

10.00

5.00

5.00

21

21

51

51

12

15

18

24

27

30

33

36

39

42

45

48

54

57

12

15

18

24

27

30

33

36

39

42

45

48

54

57

60

63

Step

Step

Figure:4

Example for the PA ramp

600-0804

The raised cosine shape will be modified to compensate for RF circuit characteristics. The ramp time is selectable between each step being 1/16 of a bit and each step being 1/8 of a bit giving a maximum ramp time of either 14.77 s or 29.53 s. An 8 bit value is used to program the ramp output level.

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MCUK981201G8 Technical Guide

60

63

0

3

6

0

3

6

9

9

0.00

0.00

VEGA

8.2.4 AFC Control
The 13 MHz system clock frequency is controlled by a 13 bit sigma-delta D/A in the VEGA chip

3/5 V

1 BIT DAC 13 BIT DIGITAL & LOW - PASS MODULATOR FILTER Output swing control RINT1 RINT2 VTCXO AFC

PROGRAMATION REGISTER

CEXT

Figure:5

AFC block diagram

600-0805

8.2.5 Audio
VEGA provides the analogue interface for the digital audio samples processed by the DSP in GEMINI.

Voice Uplink Path
MICBIAS

Bias Generator

MICIP MICIN

Microphone PGA Amplifier

Sigma_Delta Modulator

SINC Filter

IIR Bandpass Filter

To voice serial interface

fs1=1 MHz

fs2=40 KHz

fs3=8.0 KHz

AUXI

Auxiliary Amplifier

Figure:6

Voice ADC block diagram

600-0806

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Section 8 35

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VEGA

Voice Downlink Path
Auxiliary Amplifier

AUXO

EARP Earphone EARN Amplifier

Smoothing Filter Volume Cont & PGA

One bit DAC

Sigma_Delta Modulator

IIR Bandpass Filter

SINC Interpolation Filter

From voice serial interface

fs1=1 MHz

fs2=40 KHz

fs3=8.0 KHz

Figure:7

Voice DAC block diagram

600-0807

8.2.6 Auxiliary A/D
VEGA provides 5 A/D inputs. G520 takes advantage of the A/D inputs on VEGA allowing external power to be monitored with just 2 resistors each and no need for a buffer transistor.
VEGA input ADIN0 ADIN1 ADIN2 Pin Number 36 37 38 Use Battery Voltage Battery Type Battery Temperature Range 0 = 0V 3FFh = 5.5 V 0~144h = Ni-MH 145~3FFh = Li-ION 372h = -20C 16Dh = +25C 06Bh = +70C 385~3FF = No accessory 28D~384 = Headset Adaptor 1E4~28C = SMS Cable 0E7~1E3 = RS232 Direct Cable 000~0E6 = Data Adaptor 0h = 0 mA 3FFh = 1200 mA

ADIN3

39

nADP _SENSE

ADIN4

40

Current

8.2.7 Charging Voltage Control DAC
Vega provides 10 bits DAC for AGC control. GD70 does not need to control Rx gain by DAC. Therefore, GD70 will use this DAC for charging control, where the output is able to accurately control charging voltage for Li+ battery. GD70 has electrical volume for calibration of this DAC.

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This section describes the Power Supply Unit (PSU) used on the GD70 logic PCB and the method by which it is controlled. The Battery life during GSM1800 operation benefits from lower transmit power and higher PA efficiency and is therefore more efficient than when operating in GSM900. This section has detailed information on:

1. 2. 3. 4.

An overview of the circuit functionality. Powering-up the phone. Powering-down the phone. Power management.

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The logic circuit uses three separate power supplies as follows:

1. 2. 3.

2.8 Volts supply is used for the main power supply, 2V8 provides power to the digital part of the baseband circuit (Gemini, Memory and LCD). A2V8 is used to power the analogue part of the baseband circuit (Vega and voice memo). 2.5 Volts is provided to power internal blocks within the Gemini, this will be replaced by a 1.8 V supply for the smaller die size Gemini ICs. 5.0 Volts is provided to power the SIM and the SIM interface. This is generated by a switched capacitor charge pump which shifts the nominal 3.6 V battery voltage up to 5 V.

The RF circuit uses four power supplies each provided by a separate 2.8 Volt regulator. They are VSVCO and VSTX which are present when the LO_EN signal is present, and VSRF and VSVXCO which are present with the signal RF_ON. The power amplifiers are powered directly from the battery VBATT.

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The power-up procedure has two phases. If an initial check to see if the battery is in good condition is successful, the second phase determines the source of the power-up request, key press, external power, accessory, etc. and acts accordingly. The phone can be defined as powered-on whenever the linear regulators are active. It is not always obvious to the user that the phone is powered-on as it may be in one of four modes:
Mode Sleep Charge Restricted Active Description In this mode the CPU has been prevented from deactivating the linear regulators by EXT_PWR. There is no CPU activity. The CPU is alive but may perform only battery charging functions and monitor the power key. LEDs light, beeps, can charge battery etc. but it is not permitted to use the radio. The mobile is fully functional; LEDs light, beeps, search for network etc.

9.3.1 Battery Condition
The CPU must check the battery condition before deciding to power-up. The CPU can measure battery voltage and temperature. If the temperature measurement is invalid, giving a ridiculous temperature reading, a non-standard battery has been fitted, the battery is missing or the whole phone is operating far outside its specified temperature range. In any of these cases the phone must not power-up. The CPU will regularly monitor the battery condition while the phone is on. If EXT_PWR is present the regulators will be forced on and the CPU will not be able to deactivate them. If the CPU wants to power-down, all it can do is to enter sleep mode.
Battery Voltage (V) X (don't care) X <3.0 <3.5 >3.5 Temp. reading invalid invalid X valid valid EXT_PWR_SENSE 0.5 V 1.2 V <0.5 V 1.2 V X Result Power-down (battery fault) Sleep (battery fault) Power-down (low battery) LOW OK

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9.3.2 Power-up Sequence
The power-up sequence can be initiated by pressing the power key or by the presence of an external power source on the signal EXT_PWR. Both enable the linear regulators and the CPU becomes active. The CPU must then check the battery condition; if the phone is not required to power-down or sleep immediately, the result must be OK or LOW. The CPU then checks to see if a hands-free unit is connected by polling the nHF_SENSE signal, LOW when HF is connected. Now the CPU can make the decision whether to remain powered-up or not according to the truth-table below. In each case the active parameters are shaded.
Battery Condition OK LOW OK or LOW OK LOW HF X X no yes yes EXT_PWR_SENSE X >1.2 V >1.2 V >1.2 V >1.2 V nIGNITION X X X <0.5 V <0.5 V KBR0 1 1 0 0 0 LOGIC_PWR 1 1 1 1 1 Mode active restricted charge active or charge restricted or charge

With a hands-free, the phone can be configured via the MMI to power-up and down with transitions of the vehicle ignition. These are sensed by the CPU on nIGNITION, LOW when the ignition is on. Any other state than those in the table will cause the phone to deactivate the PSU by setting STAY_ALIVE LOW. While the CPU is active, it must monitor the battery condition and accessory connectivity and change state accordingly.
Current Mode Charge Charge Restricted HF X X X EXT_PWR_SENSE X 1.2 V X nIGNITION X X X KBR0 1 1 0 Battery Condition OK LOW OK New Mode active restricted active

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There are two power-down procedures:
Procedure Normal power-down Description In this case, the software has full control over the power-down procedure. Calls can be terminated gracefully etc. In some cases the PSU is not deactivated but there is a change of operating mode. This situation is caused by battery removal and is flagged by EXTINT. In this case the CPU only has time to perform a subset of the normal procedure. The priority is to prevent corruption of SIM data.

Emergency power-down

The truth-table for the power state transitions are shown below, the cause of a transition is shaded. In some cases the phone does not power-down completely but may enter a state of reduced functionality, e.g. from active to charge mode. When the new mode is OFF or sleep, the CPU will set STAY_ALIVE LOW.
Current mode X X X active active active active active active active active active active X X <3.5 V <3.5 V <3.5 V <3.5 V <3.5 V X X X X X Battery Voltage HF X X X X no yes yes yes no yes yes yes X Nignition X X X X X >2.5 V <0.5 V >2.5 V X <0.5 V >2.5 V >2.5 V X EXTINT 1 0 1 1 1 1 1 1 1 1 1 1 1 KBR0 X X 1 0 1 1 1 0 1 1 1 0 0 EXT_PWR_SENSE <0.5 V X <0.5 V >1.2 V >1.2 V X >1.2 V X >1.2 V >1.2 V X >1.2 V <0.5 V power-down normal emergency normal normal normal normal normal normal normal normal normal normal normal New mode OFF OFF OFF restricted charge OFF charge OFF charge charge OFF OFF OFF

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The power supply circuit supplies regulated power to the base-band parts, controls battery charging and monitors battery usage. The Power Management section consists of five parts as follows:

1. 2. 3. 4. 5.

Power Source. Power On/Off Control & Power Source Failure. Voltage Regulation. Battery Charging & Monitoring. Accessory Control.

The power amplifiers used in the GD70 operate from a nominal 3.6 Volts. GD70 derives this 3.6 Volts from two Lithium Ion batteries connected in parallel, or as an option, three NiMH cells connected in series. The PAs used operate at full specification between 3.0 and 3.6 Volts. They are powered directly from the battery supply to maximise the power available to them.

9.5.1 Power Source
Given the high-end nature of the GD70, Lithium-ion (Li+) cells are used for the standard battery pack. The advantages of using Li+ cells are reduced weight, size and improved gravimetric and volumetric energy densities compared to that of the NickelMetal-Hydride (NiMH).

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Power supply block diagram D70-0901 Section 40 MCUK981201G8 Technical Guide

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9.5.2 Power On/Off Control & Power Source Failure
The hardware model for the Power On/Off Control and Power Source Failure functions can be expressed by the following boolean expression and logic diagram. On/Off = VBAT + (LOGIC_PWR (nLVA_INT + (nPOWKEY nIGNITION nEXT_PWR)))

nLVA_INT

nPOWKEY nIGNITION nEXT_PWR

LOGIC_PWR

On/Off

VBAT

Figure:9

Power On/Off Control & Power Source Failure Logic Diagram

D70-0902

On/Off: Initially this active low signal is under Hardware control, the purposes of which are as follows: 1) Enable 2V8, A2V8 & 2V5 voltage supplies to Baseband. 2) Enable VSRF & VSVCXO voltage supplies to RF. 3) Generation of 13 MHz Master Clock signal. 4) Set nRESET signal LOW. 5) Wait approximately 200 ms for the voltage output of the regulators and 13 MHz Clock to become stable. Allow reset of GEMINI and VEGA internal blocks. 6) Set nRESET HIGH causing the ARM processor to start from address 0. nLVA_INT: Power Source Failure Interrupt. Active low signal generated by Low Voltage Detector circuit when VBAT drops below 2.7 V. nPOWKEY: Active low signal generated by Hardware upon the Power-On Key being pressed. nIGNITION, nEXT_PWR and LOGIC_PWR. VBAT: 3.6 V nominal battery supply provided either by 2 x Li cells in parallel or 3 x NiMH cells in series.

9.5.3 Voltage Regulation
The GD70 has the following power sources: D2V8 : Baseband power supply for digital circuitry (GEMINI, Memory and LCD) Voltage: Current: Dropout: Voltage Current Dropout: 2.8 V 2.5 % 140 mA max. 100 mV max. 2.5 V 2.5 % 120 mA max. 400 mV max.

2V5 : Power supply for GEMINI process version 2533C10 (ARM, DSP and ASIC)

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1V8 : Power supply for GEMINI process version 1833C07 (ARM, DSP and ASIC) Voltage Current Dropout: 1.8 V 2.5 % 120 mA max. 150 mV max.

Will replace the 2V5 supply when the 1833C07 process is available. A2V8 : Baseband power supply for Analogue circuitry (VEGA and Voice-Memo) Voltage Current Dropout: Voltage Current Voltage Current 2.8 V 2.5 % 60 mA max. 150 mV max. 5.0 V 5 % 20 mA max. 5.8 V 0.2 V 650 mA 50 mA

SIM5V : SIM power supply (SIM & GEMINI/SIM interface)

EXT_PWR : Power supply for battery charger

2V5 :VSVCO, voltage supply for VCO, only turned on when LO_EN signal is high 2V5 :VSTX, voltage supply for the transmitter, only turned on when LO_EN signal is high 2V5 :VSRF, voltage supply for RF circuit, only turned on when RF_ON signal is high 2V5 :VSVXCO

9.5.4 Battery Charging & Monitoring
The status of the LCD battery icon is determined by the value of BAT_VOLT returned from VEGA, the battery ICON has 4 states. The battery charging is controlled by the CPU within the phone. If rechargeable cells are detected and the temperature is within specified limits the charger starts a rapid charge algorithm. When the battery is NiMH, charging is determined by -V with time, temperature and voltage safe-guards. When the battery is Li+, charging is determined by constant current and constant current voltage with time, temperature, current and voltage safeguards. A current limit no greater than the maximum charge current for any battery option must be provided by the external power source. In the case of deeply discharged batteries there may not be enough power in the battery to initiate a charge. Therefore, the charging circuit must automatically start to trickle charge until there is enough power to switch on the phone.

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Printed in UK UK981201GD70G8