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Programmes After Market Services NHE­8/9 Series Transceivers

Chapter 3 System Module

issue 2 11/97

NHE­8/9 System Module

PAMS Technical Documentation

CONTENTS Page No
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit Description Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baseband Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard and Display Light . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RFI2, N450 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Signals and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Technical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Antenna selection switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Module ­ GJ3_09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Module ­ GJ3_10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3­5 3­5 3­6 3­7 3­7 3­8 3 ­ 23 3 ­ 38 3 ­ 39 3 ­ 39 3 ­ 40 3 ­ 41 3 ­ 45 3 ­ 46 3 ­ 51 3 ­ 51 3 ­ 51 3 ­ 51 3 ­ 54 3 ­ 56 3 ­ 60 3 ­ 63 3 ­ 64 3 ­ 64 3 ­ 64 3 ­ 65 3 ­ 65 3 ­ 79

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List of Figures Page No
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Block Diagram ­ BB/RF Modules . . . . . . . . . . . . . . . . . . . . . . . . . Power Distribution Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Charge Switch Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . Power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Loading acknowledgement procedure . . . . . . . . . . . . . . . XMIC Bridge Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . Power distribution diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3­ 6 3­23 3­24 3­29 3­35 3­42 3­52 3­54

Note: In printed manuals all A3 drawings are located at the back of the binder.

Schematics/Layouts (GJ3_09 ) Figure 9 Component Layout Diagram ­Top . . . . . . . . . . . . . . . . . . . . . . . Figure 10 Component Layout Diagram ­ Bottom . . . . . . . . . . . . . . . . . . . Figure 11 SYSTEM Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12 RX/TX Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 13 RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 14 TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15 Baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 16 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 17 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18 DSP Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 19 Keyboard /Display interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 20 MCU memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 21 Power Supply & Charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 22 BB/RF Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 23 System Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematics/Layouts (GJ3_10 ) Figure 24 Component Layout Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 25 Component Layout Bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 26 System Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 27 RX/TX Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 28 RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29 TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 30 Baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 31 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 32 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 33 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 34 Keyboard / Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 35 MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 36 Power Supply / Charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 37 BB / RF Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 38 System Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3­A1 3­A2 3­A3 3­A4 3­A5 3­A6 3­A7 3­A8 3­A9 3­A10 3­A11 3­A12 3­A13 3­A14 3­A15 3­A16 3­A17 3­A18 3­A19 3­A20 3­A21 3­A22 3­A23 3­A24 3­A25 3­A26 3­A27 3­A28 3­A29 3­A30

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Overview
The nhe­8/9 is a radio transceiver unit for the pan­European GSM network. It is a GSM phase 1 power class 4 transceiver providing 11 power levels with a maximum output power of 2 W. The transceiver consists of a Radio module (GJ3), UIF­module (GU9) and assembly parts. The plug­in (small size) SIM (Subscriber Identity Module) card is located inside the phone.

Modes of Operation
There are four different operation modes ­ power off mode ­ idle mode ­ active mode ­ local mode In the power off mode only the circuits needed for power up are supplied. In the idle mode circuits are in reset, powered down and clocks are stopped as long as possible. In the active mode all the circuits are supplied with power although some parts might be in the idle state part of the time. The local mode is used for alignment and testing.

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Circuit Description Summary
The transceiver electronics consists of the Radio Module (RF + BB blocks), the UI­module and the display module. The UI­module is connected to the Radio Module with a connector and display module is connected to UI­module by solder joint. BB blocks and RF blocks are interconnected with PCB wiring. The Transceiver is connected to accessories via a bottom system connector with charging and accessory control. The BB blocks provide the MCU and DSP environments, Logic control IC, memories, audio processing and RF control hardware (RFI2). On board power supply circuitry delivers operating voltages for BB blocks. RF blocks have regulators of their own. The general purpose microcontroller, Hitachi H8/3001, communicates with the DSP, memories and Logic control IC with an 8­bit data bus. The RF block is designed for a handportable phone which operates in the GSM system. The purpose of the RF block is to receive and demodulate the radio frequency signal from the base station and to transmit a modulated RF signal to the base station.
Keyboard

SIM

Display RESET

PSCLD RX RX IF 13 M

RESET RESET SYSTEM ASIC Clk 13 M MCU M2BUS

Clk 13 M DUPLEX FILTER SYNTE SYNTE AFC Clk 13 M

FBUS

RFI2

DSP

AUDIO

TX TX

TXI,TXQ TXC RF CONTROL

Clk 13 M RESET

Clk 512 k, Clk 8 k SYSTEM BLOCK

RF BLOCK

Figure 1. Block Diagram ­ BB/RF Modules

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Power Distribution
The power supply is based on the ASIC circuit PSCLD. The chip consists of regulators and control circuits providing functions like power up, reset and watchdog functions. External buffering is required to provide more current. The MCU and the PSCLD circuits control charging together, detection being carried out by the PSCLD and higher level intelligent control by the MCU. Charger voltages as well as temperature and size of the battery are measured by internal ADC of MCU or RFI (depending on the state of the phone). MCU measures battery voltage via DSP by means of RFI2 internal ADC.

Baseband Module
The GJ3 module is used in GSM products. The baseband is implemented using DCT2 core technology. The baseband is built around one DSP, System ASIC and the MCU. The DSP performs all speech and GSM related signal processing tasks. The baseband power supply is 3V except for the A/D and D/A converters that are the interface to the RF section. The A/D converters used for battery and accessory detection are integrated into the same device as the signal processing converters. The audio codec is a separate device which is connected to both the DSP and the MCU. The audio codec support the internal and external microphone/earpiece functions. External audio is connected in a dual ended fashion to improve audio quality together with accessories. The baseband implementation support a 32.768 kHz sleep clock function for power saving. The 32.768 kHz clock is used for timing purposes during inactive periods between paging blocks. This arrangement allows the reference clock, derived from RF to be switched off. The baseband clock reference is derived from the RF section and the reference frequency is 13 MHz. A low level clipped sinusoidal wave form is fed to the ASIC which acts as the clock distribution circuit. The DSP is running at 39 MHz using an internal PLL. The clock frequency supplied to the DSP is 13 MHz. The MCU bus frequency is the same as the input frequency. The system ASIC provides both 13 MHz and 6.5 MHz as alternative frequencies. The MCU clock frequency is programmable by the MCU. The nhe­8/9 baseband uses 13 MHz as the MCU operating frequency. The RF A/D, D/A converters are operated using the 13 MHz clock supplied from the system ASIC The power supply and charging section supplies Lithium Ion and NiMH type of battery technology. The battery charging unit is designed to accept constant current type of chargers, that are approved by NMP. The power supply IC, contains four different regulators. The output voltage from two of the regulators are 3.15V nominal. A third regulator controls an external boost transistor for a 3.15V 'high' current supply. The last regulator supplies the SIM card voltage, which is 4.9V.

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Technical Specifications
The Baseband in nhe­8/9 Operates in the following Modes Active, as during a call or when baseband circuitry is operating Sleep, in this mode the clock to the baseband is stopped and timing is kept by the 32.768 kHz oscillator. All Baseband circuits are powered Acting dead, in this mode the battery is charged but only necessary functions for charging are running Power off, in this mode all baseband circuits are powered off. The regulator IC N300 is powered External Signals and Connections
Table 1. List of Connectors Connector Name System Connector SIM Connector Code 5469007 5409033 X100 X102 Notes Specifications / Ratings

Table 2. System Connector X100 Pin 1, 7, 18, 20 2 3 Name GND Parameter Charger & System Ground Accessory Output Supply External Microphone Input 3.40 8 Min Typ 0 800 Max 0 1500 9.3 50 Unit V mA V mV Remark Measuring Reference Max Value for Charger Peaks Output Current 50 mA. The maximum value corresponds to 0 dBm network level with input amplifier gain set to 20 dB. Typical value is maximum value ­16 dB. No Accessory 2.22 1.7 1.15 0 2.4 0 2.39 1.9 1.3 2.56 2.05 1.4 0.5 3.2 0.5 V V V V V Infra Red Link connected Headset Adapter Connected Compact HF Connected External RF in use Internal antenna in use Accessory FBUS transmit signal, Serial data bus. The signal has a pull­up inside g the ASIC. Baud rate 9.6 ­ 115.2kBit / s. V V General Purpose Control and Test Control Bus

V_OUT XMIC ID

Endless IR Link Headset Compact HF 4 EXT_RF External RF control i t l input t FBUS transmit

5

TX

2.4

3.2

6

MBUS

Serial Control Bus

"0" "1"

0 2.4

0.5 3.2

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Table 2. System Connector X100 Pin 8 Name SGND Parameter Signal ground Min Typ 0 Max 0

(continued) Unit V Remark Measuring Reference for Audio signals. 47 ohm to Audio Ground Connected to Audio Codec Inverted Output. Typical level corresponds to ­16 dBmO network level with volume control in nominal position 8db below maximum. Maximum 0 dBm0 max. volume codec gain ­6dB. HF Speaker Mute HF Speaker Active HOOK OFF HOOK ON Baseband has 4.7 kohm Pull­up

9

XEAR

External Speaker

0

32

500

mV

MUTE 10 HOOK Accessory Hook Signal

ON OFF OFF ON

0 1 2.4 1.5

0.5 1.7 0.5 3.2

V V V V

11

RX

FBUS receive

0

0.5

V

2.4

3.2

V

Accessory FBUS receive signal, Serial data bus. Baud rate 9.6 ­ 115.2kBit / s. Phone has a pull­up resistor. Battery GND Also used for Vibration Alert Used for SIM Card Detection Main Power Supply Fast Charger ACH­6 (780 mA) Standard Charger ACH­8 (265mA)

13 14 15 16 12, 17, 19

BGND BTEMP BSI VBatt V_IN

GND Battery Temperature Battery Size Battery Voltage Charger supply Voltage

0 0 0 5.3 9.8 12

0 0 0 6 10.3 14

0 3.3 3.3 9.3 10.8 16

V V V V V V

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Table 3. SIM Connector X102

Pin 1 2,6

Name GND, C5 VSIM, C1, C6

Parameter GND SIM Supply Voltage

Logic Level

Min 0 4.8

Typ

Max 0

Unit V V

Remark Digital GND Tr, max. 2V/us max 200 us. Tf max. 200 us. Note1.

4.9

5.0

3

SDATA, C7

SIM DATA VI VO

"1" "0" "1" "0" "1" "0" "1" "0"

0.7xVSIM 0 0.7xVSIM 0 VSIM­0.7 0 0.7xVSIM 0

VSIM 0.8 VSIM 0.4 VSIM 0.6 VSIM 0.5

V

4 5

SRES, C2 CLK, C3

SIM Reset SIM Clock

V V Clock frequency minimum 1 MHz if clock stopping not allowed

Note 1. VSIM supply voltage may be selected to 3 V to meet 3V SIM card specifications. ( Voltage range 3.1 to 3.3 V). The values in NO TAG will be different, values only valid for "5 volt SIM card".

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Table 4. 4 5 6 GND VL SYSRESETX GND KEYLIGHT Ground Display Supply Reset

User Interface Connector X101 0 3.0 "1" "0" 2.4 0 0 "1" "0" 2.8 0 3.2 0.2 3.2 3.2 0.6 V V V V V V Max 1 mA can be drawn from N300 (PSCLD) Max 1 mA can be drawn from N300 (PSCLD) Edge sensitive ti

7 8

Ground Keboard Light

9

LCDLIGHT

Display Light

"1" "0"

2.8 0

3.3 0.2

V

10

BUZZER

PWM signalBuzzer control Ground Serial clock "1" "0"

0

3.2

V

11 12

GND GENSCLK

0 2.4 0 2.4 0 2.4 0 5.3 "1" "0" 5.3 0 3.2 0.6 3.2 0.6 3.2 0.6 9.3 9.3 0.4

V V V V V V V V V V Pulled up to Vbatt inside PSCLD. PSCLD 1.083 MHz

13

GENSD

Serial data

"1" "0"

14

LCDENX

LCD enable

"1" "0"

15 18

VBatt XPWRON

Battery Supply Power ON/ OFF

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Table 4. 19 EARN

User Interface Connector X101 (continued) 0 14 220 mV Connected to Audio Codec Inverted Output. Typical level corresponds to ­16 dBmO network level with volume control giving nominal RLR (=+2dB) 8 db below max. Max level is 0dBmO with max volume (codec gain ­11 db) Connected to Audio Codec non Inverted Output. Typical level corresponds to ­16 dBmO network level with volume control giving nominal RLR (=+2dB) 8 db below max. Max level is 0dBmO with max volume (codec gain ­11 db)

Earphone

20

EARP

Earphone

0

14

220

mV

21

ROW(0)

ROW(0) Input ROW(1) Input ROW(2) Input ROW(3) Input ROW(4) Input

"1" "0" "1" "0" "1" "0" "1" "0" "1" "0"

2.4 0 2.4 0 2.4 0 2.4 0 2.4 0

3.2 0.6 3.2 0.6 3.2 0.6 3.2 0.6 3.2 0.6

V

22

ROW(1)

V

23

ROW(2)

V

24

ROW(3)

V

25

ROW(4)

V

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Table 4. 26 ROW(5)

User Interface Connector X101 (continued) "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" 2.4 0 2.6 0 2.6 0 2.6 0 2.6 0 0 3.2 0.6 3.2 0.4 3.2 0.4 3.2 0.4 3.2 0.4 V V V V V V Also used for data control for LCD

ROW(5) Input COL(0) Output COL(1) Output COL(2) Output COL(3) Output Ground

27 28 29 30 31

COL(0) COL(1) COL(2) COL(3) GND

Table 5. DAI interface connecting test pads Pin 1 Name CODECB(0) Parameter Audio codec clock Logic Level "1" "0" Min 2.4 0 Typ Max 3.2 0.6 Unit V Remark Audio Codec clock for DAI measurements; test pin J316 Serial PCM data receive for DAI measurements; test pin J317 Serial PCM data transmit for DAI measurements; test pin J318 Audio Codec frame synchronisation for DAi measurements; test pin J319 test pin J320 test pin J321

2

CODECB(4)

DSP Serial Data Receive

"1" "0"

2.4 0

3.2 0.6

V

3

CODECB(5)

DSP Serial Data Transmit Audio codec sync

"1" "0"

2.4 0

3.2 0.6

V

4

CODECB(1)

"1" "0"

2.4 0

3.2 0.6

V

5 6

VL GND

Digital Supply GND

3.0 0

3.3 0.2

V V

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Internal Signals and Connections
Table 6. SYS_CONN Block Connections Name of Signal or Bus XEAR/MUTE SGND XMIC/ID EXT_RF BTYPE BTEMP HOOK CHARGER+ GND VBATT MBUS V_OUT TX RX RF IN I/O OUT OUT IN I/O Type IN OUT OUT OUT OUT OUT OUT OUT Notes External earphone input from AUDIO block to System connector Used as reference for external audio External Microphone output from System connector to AUDIO block External RF control output from System Connector to CCPU block Battery type Battery temperature Accessory Interrupt Charger positive contact Ground Battery Supply Input to Power Block Serial Data Bus to MCU External Accessory supply voltage Accessory FBUS digital data output Accessory FBUS digital data input External RF connector signal References

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Table 7. Audio Block Connections Name of Signal or Bus SGND Type OUT Notes Negative Output From N200 (Codec) Pin 2 used as reference for external audio Serial Digital Bus for Speech transmission to/from CCPU Block Serial Control Bus from CCPU Block External Microphone Input from System Connector Positive Microphone input from internal Microphone Negative Microphone input from internal Microphone Positive Output from N200 (CODEC) Negative Earpiece output signal from N200 (Codec) Positive Earpiece output signal from N200 (Codec) Buzzer Output to User Interface Connector LP Filtered Signal from XMIC input for Accessory Detection. Connected to CCPU and RFI Block References

CODECB(5:0) SCONB(5:0) XMIC MICP MICN XEAR EARN EARP BUZZER ACCDET

IN/OUT IN/OUT IN IN IN OUT OUT OUT OUT OUT

Table 8. Keyboard Block Connections Name of Signal or Bus KEYB(9:0) PWRONX COL(3:0) ROW(5:0) PWRX Type IN/OUT OUT OUT IN IN Notes Keyboard input/output Power on signal to Power Block Column Output to Keyboard connector X101 Row inputs from keyboard Connector X101 Power On Signal input from Keyboard Connector Active Low References

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Table 9. Power Block Connections Name of Signal or Bus MBUS(2:0) CODECB(5:0) MCUP4(7:0) SCONB(5:0) SIMI(5:0) BSI BTEMP CHARGER GND PWRONX SLEEPIX VBAT VBATT VBATT CHARGE V_OUT VLCD VA VSL VL SLEEPOX PURX M2BUS SIMCARD(3:0) LIGHTC(1:0) ADCONV(5:0) IN IN IN OUT OUT I/O OUT OUT OUT OUT OUT OUT OUT I/O I/O OUT OUT Type I/O IN/OUT I/O I/O I/O IN IN IN Notes Serial Data Bus to MCU Serial Synchronous Data Bus for DAI and Testing MCU Port 4 Bus Serial Control Bus for Regulator IC Control SIM Card Signals from CCPU Block Battery Size Signal from System Connector Battery Temperature Signal from System Connector Charger Supply Input to Power Block Ground Power On Signal from Keyboard Block Sleep Control Signal from CCPU Battery Supply Input to Power Block Battery Voltage to UI module Battery Power Supply to RF Charge Detection Signal to CCPU Accessory Power Supply Supply Voltage to LCD and Driver Supply voltage to Audio / analog circuitry. Supply voltage and sleep mode supply Supply voltage for logic circuitry Sleep signal to control RF VCXO Power Up Reset to CCPU Block Serial Control Bus to System Connector SIM Card SIgnals to Card Connector X102 Display & Keyboard Light Control signals BSI, BTEMP, VBAT and VCAR Voltage to Baseband A/D Converter Active Low, VXOENA Active Low VBAT MCUMEMC(6) References

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Table 10. CCPU Block Connections Name of Signal or Bus DSP_DATA(15:0) DATA(7:0) RFI_DATA(11:0) MBUS(2:0) CODECB(5:0) ACCES(1:0) CPUAD(5:0) PURX RFCLK RFDAX CHARGE HEADS RFCGND RFICLK DSPINT(3:0) DSPGENP(3:0) SCONB(5:0) DSP_ADDR(15:0) MEMC(6:0) MCUP4(7:0) SIM(5:0) DMEMC(3:0) RFO CONT ADDR(23:0) RFCONT(7:0) RFIADC(5:0) KEYB(9:0) Type I/O I/O I/O I/O I/O I/O IN IN IN IN I/O IN IN OUT IN OUT OUT/IN OUT OUT I/O I/O OUT OUT OUT OUT OUT OUT/IN Notes 16 Bit DSP Data Bus 8 Bit MCU Data Bus 12 Bit RFI2 Data Bus Serial Data Bus to MCU DSP and Audio Codec Serial Bus Accessory FBUS data Input to MCU A/D Converter Power Up Reset System Clock from RF Data Available Signal From RFI2 Charger Presence Signal Accessory Interrupt Reference Ground for RFCLK 13 MHz Clock to RFI2 DSP Interrupt signals DSP General Purpose Outputs Control Bus for Power Supply IC, Display Driver and Audio Codec DSP Address Bus Chip Select and Memory control signals from MCU MCU Port 4 Signals SIM Card SIgnals to Power Block DSP Memory Control Signal Bus External RF output control MCU Address Bus RF and Synthesizer Control Signal Bus RFI2 Address and Control signal Bus Keyboard ROW and Column Signals References

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Table 11. DSP_MEM Block Connections Name of Signal or Bus DSPMEMC(3:0) DSP_ADDR(15:0) DSP_DATA(15:0) Type IN IN I/O Notes DSP Memory Control Signals from CCPU Block 16­Bit DSP Address Bus from CCPU Block 16­Bit DSP Data Bus from CCPU Block References

Table 12. MCU_MEM Block Connections Name of Signal or Bus MEMC(6:0) ADR(23:0) DATA(7:0) Type IN IN I/O Notes Memory Control Signals from CCPU Block 23­Bit MCU Address Bus from CCPU Block 8­Bit MCU Data Bus from CCPU Block References

Table 13. RFI Block Connections Name of Signal or Bus RFIDATA(11:0) DSPINT(3:0) AUXAD(5:0) RFIADC(5:0) VXOENA VBATT RFICLK RFIDAX RXQ RXI VREF 2.5V AFC TXC TXIN TXIP TXQN TXQP RFIPORT(6:0) Type I/O OUT IN OUT IN IN IN OUT IN IN OUT OUT OUT OUT OUT OUT OUT OUT Notes 12 Bit Data Bus Between RFI2 and CCPU Block Interrupt to CCPU Block Baseband Measurement A/D Converter Signals to RFI2 Block 4 Bit Address and 2 Bit Control Bus from CCPU Block Sleep signal to control RFI2 analog power supply Battery Supply Voltage from Power Block 13 MHz clock from CCPU Block Data Available Signal From RFI2 Input Signal From RF Input signal from RF Reference Voltage to RF AFC Voltage to RF VCXO Power Ramp Control Signal to RF Negative In Phase Signal to RF Positive In Phase Signal to RF Negative Quadrature Signal to RF Positive Quadrature Signal to RF Parallel Port From RFI Block Active Low, SLEEPOX References

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Table 14. AC and DC Characteristics of the RF­baseband signals Signal name VBATT Fro m battery t To RF Parameter Voltage Current RF regulal tor Logic high "1" Logic low "0" Current timing inaccuracy RXPWR ASI C RF regulator Logic high "1" Logic low "0" Current SYNTHP WR ASI C RF regulator Logic high "1" Logic low "0" Current TXPWR ASI C RF regulator Logic high "1" Logic low "0" Current SENA1 ASI C PLL Logic high "1 Logic low "0" Current Load capacitance SDATA ASI C PLL Logic high "1 Logic low "0" Load resistance Load capacitance Data rate frequency SCLK ASI C PLL Logic high "1 Logic low "0" Load impedance Load capacitance Data rate frequency 3.25 2.4 0 10 10 3.25 3.15 3.3 0.8 2.4 0 10 10 3.15 2.4 0 3.15 2.4 0 3.15 2.4 0 3.15 2.4 0 3.15 2.4 0 3.15 Min 5.3 Typical Max Unit 6.0 9.3 150 0 3.3 0.5 0.5 10 3.3 0.5 0.5 3.3 0.5 1.0 3.3 0.5 0.5 3.3 0.8 50 10 3.3 0.8 V mA V V mA us V V mA V V mA V V mA V V uA pF V V koh m pF MH z V V koh m pF MH z Synthesizer clock Synthesizer data Dual PLL Enable TX supply voltage ON TX supply voltage OFF RF regulators ON RF regulators OFF RX supply voltage ON RX supply voltage OFF Synth. regulator ON vcxo voltage ON, Synth. regulator OFF, VCXO voltage OFF Function Supply voltage for RF

VXOENA

ASI C

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Table 14. AC and DC Characteristics of the RF­baseband signals (continued) Signal name TXP Fro m ASI C To RF Parameter Logic high "1" Logic low "0" Load Resistance Load Capacitance Timing inaccuracy RFC VCT ASI CX C O Frequency Signal amplitude Load Resistance Load Capacitance PDATA0 RFI 2 LNA Logic high "1" LNA Logic low "0" Current Logic high "1" Logic low "0" Current PDATA2 RFI 2 Logic high "1" Logic low "0" Current PDATA3 RFI 2 Logic high "1" Logic low "0" Current PDATA4 RFI 2 Logic high "1" Logic low "0" Current PDATA5 RFI 2 Logic high "1" Logic low "0" Current 2.4 0 3.15 2.4 0 3.15 2.4 0 3.15 2.4 0 3.15 2.4 0 3.15 2.4 0 3.15 0.4 10 5 3.3 0.8 0.1 3.3 0.5 10 3.3 0.5 10 3.3 0.5 10 3.3 0.5 10 3.3 0.5 10 13 1.0 3.0 Min 2.4 0 50 10 1 Typical Max Unit 3.15 3.3 0.8 V V koh m pF us MH z Vpp koh m pF V V mA V V uA V V uA V V uA V V uA V V uA Not used ! Not used ! Not used ! Not used ! Nominal front end gain Reduced front end gain Nominal front end gain Not used ! High stability clock sig­ nal for the locig circuits Function Transmitter power control t l enable bl

RFI 2 PDATA1 RFI 2

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Table 14. AC and DC Characteristics of the RF­baseband signals (continued) Signal name AFC Fro m RFI 2 To Parameter Min 0.26 11 10 500 1 25 570 Typical Max Unit 3.94 V bits koh m
uVrm s

Function Automatic frequency control signal f t l i l for VCTCXO

VCT Voltage CX Resolution O Load impedance (dynamic) Noise Voltage Settling time

10...10000 Hz

ms mV pp ohm koh m Differential RX 13 MHz signal to baseband

RXIP / RXIN

CR RFI FRF 2 T

Output level

Source impedance Load Resistance Load Capacitance Phase Imbalance Amplitude Imbalance TXIP/ TXIN RFI 2 CR Differential voltage FRT swing Differential Offset voltage Diff. Offset voltage temp. dependence DC level Offset voltage Source Impedance Load Resistance Load Capacitance Resolution DNL INL Group delay mismatch TXQP/ TXQN RFI 2 CR Same spec as for TXIP / TXIN FRT 8 16 2.01 2.1 6 2.23 2.40 10

300

5 2 1

pF deg dB

2.57 Vpp +­4. mV 7 +­ 2 2.40 V +­ 10 50 mV ohm koh m 10 pF bits +­0. LSB 9 + ­1 LSB 100 ns

Differential in­phase TX baseband signal for th RF modulator d l t the

Differential quadrature phase TX baseband signal for the RF modulator

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Table 14. AC and DC Characteristics of the RF­baseband signals (continued) Signal name TXC Fro m RFI 2 To Parameter Min 3.86 0.26 Typical Max Unit 3.94 V 0.34 V 10 50 10 10 10 500 10 LSB ohm koh m pF us
uVrm s

Function Transmitter power control, t l CRFRT gain coni trol

CR Voltage Max FRT Voltage Min Vout temperature dependence Source Impedance Input resistance Input capacitance Settling Time Noise level Resolution DNL INL

0...200kHz

bits +­0. LSB 9 +­ 4 2.493 LSB V 3.3 0.6 2 V V W External RF signal from/to bottom connector RFC signal ground RF reference voltage External RF control

VREF 2.5 RFO_CO NT RFOUT

RFI 2 MC U RF

RF RF

Voltage level Logic high "1" Logic low "0" 2.4 0

OU T RF

RFCGND

ASI C

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Functional Description
Power Supply

VBATT to RF Vxoena VBAT R344 N451 4.50 V L312 V306 GND CHARGER + L311 L306 VRFI N450 VBATT to UI module

C340 V305

VL 3.16 V VLCD 3.16 V VLMCU 3.16 V D150 D400 VLDSP D152 D404 D405 3.16 V Z451 VLRFI

L107

CHARGER UNIT
V100 AGND

PSCLD N300
GND VA 3.16 V VSIM Z152 VSL VSLRC 3.16 V D151; pin 124 VSLC 3.16 V D151 D401 D403

Z150

Z153

L108

CHGND L101 BGND

5/3V

Z151

N450

GND

Figure 2.

Power Distribution Diagram.

The power supply for the baseband is the main battery. A charger input is used to charge the battery. Two different chargers can be used for charging the battery. A switch mode type fast charger that can deliver 780 mA and a standard charger that can deliver 265 mA. Both chargers are of constant current type. The baseband has one power supply IC, N300 delivering power to the different parts in the baseband. There are two logic power supply and one analog power supply. The analog power supply VA is used for analog circuits such as audio codec, N200 and microphone bias circuitry. Due to the current consumption and the baseband architecture the digital supply is divided into two parts. Both digital power supply rails from the N300, PSCLD are used to distribute the power dissipation inside N300, PSCLD. The main logic power supply VL has an external power transistor, V306 to handle the power dissipation that will occur when the battery is fully charged or during charging.

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D151, ASIC and the MCU SRAM, D403 are connected to the same logic supply voltage. All other digital circuits are connected to the main digital supply. Charging Control Switch Functional Description The charging switch circuit diagram is shown below. The figure is for reference only.
L303

VBA
L300

VBAT
V304 V305

CHARGER

R308

R342 C308

R301 C300 C301 C302 R326 R343

R327 C304 R308

C305

R309 V311 V301 R302 R305 R304 R303 C303 R306 V302 V303

PW

GND

Figure 3.

Charge Switch Circuit Diagram

The charging switch transistor V304 controls the charging current from the charger input to the battery. During charging the transistor is forced in saturation and the voltage drop over the transistor is 0.2­0.4V depending upon the current delivered by the charger. Transistor V304 is controlled by the PWM output from N300, via resistors R309, R308 and transistor V311. The output from N300 is of open drain type. When transistor V304 is conducting the output from N300 pin is low. In this case resistors R305 and R306 are connected in parallel with R304. This arrangement increases the base current thru V304 to put it into saturation. Transistors V304, V302, V303 and V311 forms a simple voltage regulator circuitry. The reference voltage for this circuitry is taken from zener diode V301. The feedback for the regulator is taken from the collector of V304. When the PWM output from N300 is active, low, the feedback voltage is determined by resistors R308 and R309. This arrangement makes the charger control switch circuitry to act as a programmable voltage regulator with two output voltages depending upon the state of the PWM output from N300. When the PWM is inactive, in high impedance state, the feedback voltage is almost the same as on the collector of V304. Due to the connection the voltage on V303 and V311 emitters are the same. The feedback means that the system regulates the output voltage from V304 in such a way that the base of V303 and V311 are at the same voltage. The voltage on V302 is determined by the V301 zener voltage.

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The darlington connection of V303 and V302 service two purposes ; 1 the load on the voltage reference V301 is decreased, 2 the output voltage on V304 is decreased by the VBE voltage on V302 which is a wanted feature. The voltage reduction allows a relative temperature stable zener diode to be used and the output voltage from V304 is at a suitable level when the PWM output from N300 is not active. The circuitry is self starting which means that an empty battery is initially charged by the regulator circuitry around the charging switch transistor. The battery is charged to a voltage of maximum 4.8V. This charging switch circuitry allows for both NiCd, NiMH and Lithium type of batteries to be used. At the same time it will secure that the battery will not over charge in case one cell is short circuited. When the PWM output from N300 is active the feedback voltage is changed due to the presence of R308 and R309. When the PWM is active the charging switch regulator voltage is set to 9.3V maximum. This means that even if the voltage on the charger input exceeds 11.5V the battery voltage will not exceed 9.3 V. This protects N300 from over voltage even if the battery was to be detached while charging. The RC network C304, R308 and R309 also acts as a delay circuitry when switching from one output voltage to an other. This happens when the PWM output from N300 is pulsing. The reason for the delay is to reduce the surge current that will occur when V304 is put into conducting state. Before V304 is put in conducting state there is a significant voltage drop over V304. The energy is stored in capacitors in the charger and these capacitors must first be drained in order to put the charger in constant current mode. This is done by discharging the capacitors into the battery. The delay caused by C304 will reduce the surge current thru V304 to an acceptable value. R301 and R326 are used to regulate the zener current. During charging with empty battery the zener voltage might drop due to low zener current but this is no problem since the regulator is operating in constant current mode while charging. The zener voltage is more important when the charger voltage is high or in case that the PWM output from N300 is inactive. In this case the charger idle voltage is present at the charger supply pins. R300 and R327 together with V304 forms a constant current source. The surge current limitation behavior is frequency dependent since L107 is an inductor. The purpose of this circuitry is to reduce the surge current thru V304 when it is put in conducting state. Due to the low resistance value required in L107 this arrangement is not very effective and the RC network R308, R309 and C304 contributes more to the surge current reduction. V305 is a schottky diode that prevents the battery voltage from reverse biasing V304 when the charger is not connected. The leakage current for V305 is increasing with increasing temperature and the leakage current is passed to ground via R308, V311 and R304.

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This arrangement prevents V304 from being reversed biased as the leakage current increases at high temperatures. Components L107, C300, C301, C302 and L108 forms a filter for EMC attenuation. The circuitry reduces the conductive EMC part from entering the charger cable causing an increase in emission as the cable will act as an antenna. V100 is a 18V transient suppressor. V100 protects the charger input and in particular V304 for over voltage. The cut off voltage is 18V with a maximum surge voltage up to 25V. V100 also protects the input for wrong polarity since the transient suppressor is bipolar. Power Supply Regulator PSCLD, N300 The power supply regulators are integrated into the same circuit N300. The power supply IC contains three different regulators. The main digital power supply regulator is implemented using an external power transistor V306. The other two regulators are completely integrated into N300. PSCLD, N300 External Components N300 performs the required power on timing. The PSCLD, N300 internal power on and reset timing is defined by the external capacitor C330. This capacitor determines the internal reset delay, which is applied when the PSCLD, N300 is initially powered by applying the battery. The baseband power on delay is determined by C311. With a value of 10 nF the power on delay after a power on request has been active is in the range of 50­150 ms. C310 determines the PSCLD, N300 internal oscillator frequency and the minimum power off time when power is switched off. The sleep control signal from the ASIC, D151 is connected via PSCLD, N300. During normal operation the baseband sleep function is controlled by the ASIC, D151 but since the ASIC is not powered up during the startup phase the sleep signal is controlled by PSCLD, N300 as long as the PURX signal is active, low. This arrangement ensures that the 13 MHz clock provided from RF to the ASIC, D151 is started and stable before the PURX signal is released and the baseband exits reset. When PURX is inactive, high, sleep control signal is controlled by the ASIC D151. To improve the performance of the analog voltage regulator VA an external capacitor C329 has been added to improve the PSRR. N300 requires capacitors on the input power supply as well as on the output from each regulator to keep each regulator stable during different load and temperature conditions. C305 and C308 are the input filtering capacitors. Due to EMC precautions a filter using C305, L300 and C308 has been inserted into the supply rail. This filter reduces the high frequency components present at the battery supply from exiting the baseband into the battery pack. The regulator outputs also have filter capacitors for power supply filtering and regulator stability. A set of different capacitors are used to achieve a high bandwith in the suppression filter.

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PSCLD, N300 Control Bus The PSCLD, N300 is connected to the baseband common serial control bus, SCONB(5:0). This bus is a serial control bus from the ASIC, D151 to several devices on the baseband. This bus is used by the MCU to control the operation of N300 and other devices connected to the bus. N300 has two internal 8 bit registers and the PWM register used for charging control. The registers contains information for controlling reset levels, charging HW limits, watchdog timer length and watchdog acknowledge. The control bus is a three wire bus with chip select for each device on the bus and serial clock and data. From PSCLD, N300 point of view the bus is used as write only to PSCLD. It is not possible to read data from PSCLD, N300 by using this bus. The MCU can program the HW reset levels when the baseband exits/enters reset. The programmed values remains until PSCLD is powered off, the battery is removed. At initial PSCLD, N300 power on the default reset level is used. The default value is 5.1 V with the default hysteresis of 400 mV. This means that reset is exit at 5.5 V when the PSCLD, N300 is powered for the first time. The watchdog timer length can be programmed by the MCU using the serial control bus. The default watchdog time is 32 s with a 50 % tolerance. The complete baseband is powered off if the watchdog is not acknowledged within the specified time. The watchdog is running while PSCLD, N300 is powering up the system but PURX is active. This arrangement ensures that if for any reason the battery voltage doesn't increase above the reset level within the watchdog time the system is powered off by the watchdog. This prevents a faulty battery from being charged continuously even if the voltage never exceeds the reset limit. As the time PURX is active is not exactly known, depends upon startup condition, the watchdog is internally acknowledged in PSCLD when PURX is released. This gives the MCU always the same time to respond to the first watchdog acknowledge. Baseband power off is initiated by the MCU and power off is performed by writing the smallest value to the watchdog timer register. This will power off the baseband within 0.5 ms after the watchdog write operation. The control bus can also be used to setup the behavior of the N300 regulators during sleep mode, when sleep signal is active low. In order to reduce power during sleep mode two of the three regulators can be switched off. The third regulator, VSL which is kept active then supplies the output of the other regulators. All regulator outputs from PSCLD, N300 are supplied but the current consumption is restricted. It is also possible to keep the VL regulator active during sleep mode in case the power consumption is in excess of what the VSL regulator can deliver in sleep mode to the VL output.

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The PSCLD, N300 also contains switches for connecting the charger voltage and the battery voltage to the base band A/D converters. Since the battery voltage is present and the charger voltage might be present in power off the A/D converter signals must be connected using switches. The switch state can be changed by the MCU via the serial control bus. When PURX is active both switches are open to prevent battery/charger voltage from being applied to the baseband measurement circuitry which is powered off. Before any measurement can be performed both switches must be set in not closed mode by MCU. Charger Detection A charger is detected if the voltage on N300, 'VCHAR' is higher than 0.5V. The charger voltage is scaled outside PSCLD, N300 using resistors R302 and R303. With the implemented resistor values the corresponding voltage at the charger input is 2.8V. Due to the multifunction of the charger detection signal from PSCLD, N300 to ASIC, D151 the charger detection line is not forced ,active high until PURX is inactive. In case PURX is inactive the charger detection signal is directly passed to D151. The active high on 'CHRG_IND/ALARM' pin generates and interrupt to MCU which then starts the charger detection task in SW. The reason for not passing the charger detection signal to the ASIC, D151 when PURX is active is the RTC implementation in ASIC, D151., The same signal is used to power up the system if the RTC alarm is activated and the system is powered up. Due to this the PSCLD, N300 'CHRG_IND/ALARM' pin, is in input mode as long as PURX is active, low. Correspondingly at the ASIC end this pin is an output as long as PURX is active. The RTC function needs SW support and is not implemented in nhe­8/9. The baseband architecture provides for the functionality required. SIM Interface and Regulator in N300 The SIM card regulator and interface circuitry is integrated into the PSCLD, N300. The benefit from this is that the interface circuits are operating from the same supply voltage as the card, avoiding the voltage drop caused by the external switch used in previous designs. The PSCLD, N300 SIM interface also acts as voltage level shifting between the SIM interface in the ASIC, D151 operating at 3V and the card operating at 5V. Interface control in PSCLD is direct from ASIC, D151 SIM interface using SIM(5:0) bus. The MCU can select the power supply voltage for the SIM using the serial control bus. The default value is 3V which needs to be changed to 5V before powering up the SIM interface in the ASIC, D151. Regulator enable and disable is controlled by the ASIC via SIM(2).

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Power Up Sequence The baseband can be powered up in three different ways. When the power switch is pressed input pin 'PWRONX' on PSCLD, N300 is connected to ground and this switches the regulators inside PSCLD on. An other way to power up is to connect the charger,whichr causes the baseband to power up and start charging the battery. The third way to power the system up is to attach the battery.
Power up using Power on Button

This is the most common way to power the system up. It is successful if the battery voltage is higher than the power on reset level set by the MCU, in the PSCLD, N300, default value 5.5 Vdc. The power up sequence is started when the power on input pin 'PWRONX' at PSCLD is activated, low. The PSCLD then internally enters the reset state where the regulators are switched on. At this state the PWM output 'CHRGSW' on the PSCLD is forced active to support additional power from any charger connected. The sleep control output signal is forced high enabling the regulator to supply the VCO and startup the clock. After the power on reset delay of 50­150 ms PURX is released and the system exits reset mode. The PWM output is still active until the MCU writes the first value to the PWM register. The watchdog has to be acknowledged within 16 s after that PURX is released, go high. The power up sequence using power on/off button is shown below.

PwrSwitch has been pressed

Supply voltage VL

Master Reset PurX

MCU Clock starts

MCU Reset release

Figure 4.

Power up sequence

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Power up with Empty Battery using Charger

When the charger is inserted into the DC jack or charger voltage is supplied at the system connector contacts/pins, PSCLD ( N300) powers up the baseband. The charging control switch is operating as a linear regulator, the output voltage is 4.5V­5V. This allows the battery to be charged immediately when the charger is connected, which guarantees successful power up procedure with an empty battery. With an empty battery the only power source is the charger. When the battery has been initially charged and the voltage is higher than the PSCLD, N300 switch on the sleep control signal which is connected to the PSCLD for power saving function. Sleep mode, enters inactive state, high, to enable the regulator that controls the power supply to the VCO to be started. The ASIC, D151 which normally controls the sleep control line has the sleep output inactive, low, as long as the system reset 'PURX', from PSCLD, is active, low. After a delay of about 5­10 ms the system reset output from PSCLD enters high state. This delay is to ensure that the clock is stable when the ASIC exits reset. The sleep control output from the PSCLD that has been controling VXOENA until now, returns the control to the sleep signal from the ASIC as the PURX signal goes inactive. When the PURX signal goes inactive, high, the charge detection output at PSCLD, that is in input mode when PURX is active, switches to output and goes high indicating that a charger is present. When the system reset, PURX, goes high the sleep control line is forced inactive, high, by the ASIC, D151 via PSCLD, N300. Once the system has exited reset mode the battery is initially charged until the MCU writes a new value to the PWM register in the PSCLD. If the watchdog is not acknowledged the battery charging is switched off when the PSCLD shuts off the power to the baseband. The PSCLD will not enter the power on mode again until the charger has been extracted and inserted again or the power on/off switch has been pressed. The battery is charged as long as the power on line, PWRONX is active low. This is done to allow the phone to be started manually from the power button when the charger is conncted and there is no need to disconnect the charger to get a power up if the battery is empty.
Power On Reset Operation

The system power up reset is generated by the regulator IC, N300. The reset is connected to the ASIC, D151 that is put into reset mode whenever the reset signal, PURX is low. The ASIC ( D151 ) then resets the DSP (D152), the MCU (D150) and the digital parts in RFI2 (N450). When reset is removed the clock supplied to the ASIC, D151 is enabled inside the ASIC. At this point the 32.768 kHz oscillator signal is not enabled inside the ASIC, since the oscillator is still in the startup phase.

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To start up the block requiring 32.768 kHz clock the MCU must enable the 32.768 kHz clock. The MCU reset counter is now started and the MCU reset is still kept active, low. the 6.5 MHz clock is started to MCU in order to reset the MCU( D150 ) , it is a synchronous reset device and needs clock to reset. The reset to MCU is inactivated after 128 MCU clock cycles and MCU is started. DSP ( D152) and RFI2 (N450) reset is kept active when the clock inside the ASIC, D151 is started up. 13 MHz clock is applied to DSP (D152) and resets it. The DSP, D152 is a synchronous reset device, which requires clock to reset. The RFI2, N450 digital parts are reset asynchronously and does not need clock to support reset. As both the MCU, D151 and DSP, D152 are synchronous reset devices all interface signals connected between these devices and ASIC D151 which are used as I/O are set into input mode on the ASIC, D151 side during reset. This prevents bus conflicts until the MCU, D150 and the DSP, D152 has been reset. The DSP ( D152) and RFI2 (N450) reset signal remains active after the MCU has left reset mode. The MCU writes to the ASIC register to disable the DSP reset. This arrangement allows the MCU to reset the DSP, D152 and RFI2 ,N450 when ever needed. The MCU can reset the DSP by setting the reset active in the ASIC, D151 register.
Power Off due to low Battery Voltage

The battery monitor software determines when the handset must power off due to low battery voltage. This happens when the battery voltage, estimated by the monitor software, reaches a predefined level, the cutoff voltage. The cutoff voltage depends upon the battery type, in HD844 they are 5.3V for NiMH, and 5.5V for Li­ION.

TX­on

TX­off

MCU The baseband uses a Hitachi H3001 type of MCU. This is a 16­bit internal MCU with 8­bit external data bus. The MCU is capable of addressing up to 16 MByte of memory space linearly depending upon the mode of operation. The MCU has a non multiplexed address/data bus which means that memory access can be done using less clock cycles thus improving the performance but also tightening up memory access requirements.

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NHE­8/9 System Module

PAMS Technical Documentation

The MCU is used in mode 3 which means 8­bit external data bus and 16 Mbyte of address space. The MCU operating frequency is equal to the supplied clock frequency. The MCU has 512 bytes of internal SRAM. The MCU has one serial channel, USART that can operate in synchronous and asynchronous mode. The USART is used in the MBUS implementation. Clock required for the USART is generated by the internal baud rate generator. The MCU has 5 internal timers that can be used for timing generation. Timer TIOCA0 input pin 71 is used for generation of netfree signal from the MBUS receive signal which is connected to the MCU USART receiver input on pin 2. The reason for generating the MBUS netfree using the counter is the fact that the 32.768 kHz clock that would have been used for this timing is a slow starting oscillator. Which means that in production testing the MBUS can not be operated until the netfree counter is operational. As the netfree counter is implemented using the MCU internal counter the netfree counter is available immediately after reset. In the same way the MCU OS timer is operated from an internal timer in the early stage until the 32.768 kHz clock can be enabled and the OS timer provided in the ASIC can be used. The MCU contains 4 10­bit A/D converters channels that are used for baseband monitoring. The MCU, D150 has several programmable I/O ports which can be configured by SW. Port 4 which multiplexed with the LSB part of the data bus is used baseband control. In the mode the MCU is operating, this port can be used as an I/O port and not as part of the data bus, D0­D7. MCU Access and Wait State Generation The MCU can access external devices in 2 state access or 3 state access. In two state access the MCU uses two clock cycles to access data from the external device. In 3 state access the MCU uses 3 clock cycles to access the external device or more if wait states are enabled. The wait state controller can operate in different modes. In this case the programmable wait mode is used. This means that the programmed number of wait states in the wait control register is inserted when an access is performed to a device located in that area. The complete address space is divided into 8 areas each covering 2 MByte of address space. The access type for each area can be set by bits in the access state control register. Further more the wait state function can be enabled separately for each area by the wait state control enable register. This means that in 3 state access two types of accesses can be performed with a fixed setting: 3 state access without wait states 3 state access with the number of wait states inserted determined by the wait control register If the wait state controller is not enabled for a 3 state access area no waits states are inserted when accessing that area even if the wait control register contains a value that differs from 0.

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PAMS Technical Documentation

NHE­8/9 System Module

MCU and Memory Map The chip selects for the memories is generated by the ASIC. MCU address lines A23­A21 are used for this purpose. This means that the MCU address space can be divided into 8 areas, the same amount of areas that the MCU supports for wait state generation. For ASIC, D150 access MCU address A5­A0 is used. 7­bits are required during MCU boot access while ASIC register access requires 6­bits. The boot ROM and internal ASIC, D151 registers are located in separate areas to allow the use of only 7 address bits for addressing both the boot ROM and ASIC registers. The MCU starts up with address lines A23­A21 configured as I/O lines even if the operating mode is set to extended mode by HW. To avoid address decoding problems the internal addresses for decoding the ASIC registers are gated until the first write operation to the ASIC registers. Before this write operation is performed, the MCU must set up address signal A23­A21 to be used as addresses lines. The MCU IC design has been modified in later versions to work according to mode setting pin. The first write operation, a "dummy" write, enables the address lines internally in the ASIC and ASIC registers can be accessed by write operations. The MCU Boots from address 000000H. After D151 reset sequence this address is located in the ASIC, D151 internal ROM, which is 128 bytes. During the execution of this code the MCU, D150 looks if pin 3, serial clock SCK is pulled low. In this case the execution stops and the MCU waits for the flash prommer to initiate flash loading. If the SCK line is not pulled low and if the flash is empty the MCU starts execution from the flash address 40000EH. The flash area 400000H­40000DH is reserved for baseband related HW identifiers. This field is used to tell the MCU the configuration of the baseband it is operating in. MCU operating speed, number of program memories, amount of wait states, EEPROM configuration etc. is coded into these bytes. The flash prommer specifications deals with this in more detail. In case of SW update the flash prommer will use the same identifier as read out at the startup of the reprogramming. As the MCU external SRAM is mapped in the same area as the boot ROM the MCU must write to the ASIC in order to disable the boot ROM and enable the external SRAM. The MCU then sets up the wait state registers and the access registers. After reset all access is performed using 3 state access with 3 wait states inserted to allow initial boot with very slow devices. Since the interrupt vector table resides in the area 000004H­0000F3H the vector table must be copied from the flash to the SRAM before any interrupt is enabled. In case this is not done properly the SW will crash at the point when the interrupts are to be serviced. The ASIC is located in the address area close to the end to allow short addressing operations to the ASIC registers to improve the performance of the system.

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NHE­8/9 System Module

PAMS Technical Documentation

The flash area is divided into two areas to allow for two devices to be used in case of availability problem or large memory requirement. nhe­8/9 uses only one device in the first flash area. The EEPROM area is reserved for parallel EEPROM devices. nhe­8/9 is prepared for parallel EEPROM, but the default EEPROM is a serial device connected to the MCU I/O port. MCU Flash Loading The flash loading equipment is connected to the baseband by means of the test connector before the module is cut out from the frame. Updating SW on a final product is done by removing the battery and connect a special adapter that contains the necessary contacting elements. The contacts on the baseband board are test points that are accessable when the battery is detached. The power supply for the base band is supplied via the adapter and controlled by the flash programming equipment. The base band module is powered up when the power is connected to the battery contact pins. The interface lines between the flash prommer and the baseband are in low state when power is not connected by the flash prommer. The data transfer between the flash programming equipment and the base band is synchronous and the clock is generated by the flash prommer. The same USART that is used for MBUS communication is used for the serial synchronous communication. The PSCLD watchdog is disabled when the flash loading battery pack and cable is connected. After the flash battery pack adapter has been mounted or the test connector has been connected to the board the power to the base band module is connected by the flash prommer or the test equipment. All interface lines are kept low except for the data transmit from the baseband that is in reception mode on the flash prommer side, this signal is called TXF. The MCU boots from ASIC and investigates the status of the synchronous clock line. If the clock input line from the flash prommer is low or no valid SW is located in the flash the MCU forces the initially high TXF line low, acknowledging to the flash prommer that it is ready to accept data . The flash prommer sends data length, 2 bytes, on the RXF data line to the baseband. The MCU acknowledges the 2 data byte reception by pulling the TXF line high. The flash prommer now transmits the data on the RXF line to the MCU. The MCU loads the data into the internal SRAM. After having received the transferred data correctly MCU puts the TXF line low and jumps into internal SRAM and starts to execute the code.

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PAMS Technical Documentation

NHE­8/9 System Module

After a guard time of 1 ms the TXF line is put high by the MCU. After 1 ms the TXF is put low indicating that the external SRAM test is going on. After further 1 ms the TXF is put high indicating that external SRAM test has passed. The MCU performs the flash memory identification based upon the identifiers specified in the Flash Programming Specifications. In case of an empty device, identifier locations shows FFH, the flash device code is read and transmitted to the Flash Prommer. Ready to send External SRAM Flash ID test going on External SRAM test passed

Internal SRAM execution begin Boot OK Length OK Reset

TXF

1 ms
Figure 5. Flash Loading acknowledgement procedure

After that, the device mounted on base band has been identified the Flash Prommer down loads the appropriate programming algorithm to the baseband. The algorithm is stored in the external SRAM on the baseband module and after having down loaded the algorithm and the data transfer SW, MCU jumps to the external SRAM and starts to execute the code. The MCU now asks the prommer to connect the flash programming power supply. This SW loads the data to be programmed into the flash and implements the programming algorithm that has been down loaded. The flash data is loaded in bytes. Flash Prommer Connection Using Dummy Battery For MCU SW updating in the field a special adapter can be used to connect to the test points which are accessable through SIM opening in the chassis, located behind the battery. Supply voltage must be connected as well as the flash programming equipment Flash, D400 A 8 MBit flash is used as the main program memory, D400 the device is 3 V read/program with external 12V VPP for programming. The device is sectored and contains 16 64 kByte blocks. The sector capability is not used in the nhe­8/9 application. The speed of the device is 180 ns. The MCU operating at 13 MHz will access the flash in 3 state access, requiring 190 ns access time from the memory.

issue 2 11/97

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NHE­8/9 System Module

PAMS Technical Documentation

The flash has a deep power down mode that can be used when the device is not active. There is a requirement for a longer access time if the device is accessed immediately after exiting power down. This requirement is met since the signal controlling the VCO power control is used for this purpose. The flash power down pin, pin 12 is connected to ASIC, D151 pin 130. The reason for connecting it to the ASIC and not direct to the VCO power control signal is that this pin on the ASIC is low as long as the ASIC is in reset mode. This signal resets the flash memory and acts as a power up reset to the memory. SRAM D403 for MCU The baseband is designed to use SRAM size 128x8/64kx8. Default in nhe­8/9 is 64Kx8. The required speed is 100 ns as the MCU will operate at 13 MHz and the SRAM will be accessed in 3 state access. The SRAM has no battery backup which means that the content is lost even during short power supply disconnections. As shown in the memory map the SRAM is not accessable after boot until the MCU has enabled the SRAM access by writing to the ASIC register. Serial EEPROM D402 The nhe­8/9 Base Band uses 2Kx8 bit I2C serial EEPROM , which is connected to the MCU port P4. The 16 kbit serial EEPROM has a 16 byte page. The byte/page write time is 10 ms. The EEPROM uses I2C serial interface to communicate with the MCU. In addition to this the EEPROM has a write protect signal, pin 7 that protects the EEPROM from accidental write operations, if high. The write protect signal, pin 7 must be low, before the write operation to the EEPROM can start. After that the write operation is completed the write enable signal is put into inactive state, high. The MCU generates by SW the required I2C timing on the SDA (serial data) and SCL (serial clock) pins at port P4 used for the EEPROM interface. The device acknowledges it's presence after each address written to it. When writing, each byte is acknowledged. The acknowledge procedure takes place during the " fictive" transmission of the 9 th bit. The MCU must therefore release the line for the 9 th bit, give the clock pulse for the device, to perform the acknowledgement. The serial data line is operating as open drain which requires pull up resistor on the base band. The device has 3 external address pins. These adress pins are user selectable. The relation between the transmitted address and the pin setting is inverted. The device pins will be tied to ground on the base band which means that the first 4 address bits to be put out on the data line are "1010", the MSB is interna