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PAMS Technical Documentation RAE-3 Series PDA
3. RF+System Module BL8
issue 1 06/01
Copyright E 2001. Nokia Mobile Phones. All Rights Reserved.
RAE-3 3. RF+System Module BL8
PAMS Technical Documentation
AMENDMENT RECORD SHEET
Amendment Number Date Inserted By OJuntunen Comments
06/01
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RAE-3 3. RF+System Module BL8
CONTENTS Troubleshooting Page No
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAE-3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAE-3 Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List of Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Summary of System Part . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Backup battery connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIM card connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Infrared interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System RF interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resets and Watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System to interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MEMORIES block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XIP Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRDA block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UI block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phone LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Earpiece and HF Speaker lines . . . . . . . . . . . . . . . . . . . . . . Battery removal signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYSCON block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 39 39 39 3 10 3 11 3 12 3 12 3 13 3 14 3 15 3 15 3 16 3 17 3 17 3 21 3 25 3 25 3 25 3 26 3 26 3 28 3 28 3 28 3 29 3 31 3 31 3 31 3 31 3 32 3 32 3 33 3 33 3 33 3 33 3 33 3 34 3 34 3 34 3 35
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External Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Charger Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POWER block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Use of CCONT ADC channels . . . . . . . . . . . . . . . . . . . . . . . AUDIO_RFI block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to RF of BL8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF frequency plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 V regulator in VCP line . . . . . . . . . . . . . . . . . . . . . . . . . . Power distribution diagram . . . . . . . . . . . . . . . . . . . . . . . . . . RF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGC strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AFC function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Antenna switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SWITCH (SW_1, SW_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . TXFILTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RXFILTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX EGSM900/DCS1800 DUALBAND SAW FILTER . . . . EGSM Preamplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . DCS1800 Preamplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . GSM/PCN IC (Hagar), RX part . . . . . . . . . . . . . . . . . . . . . . . Transmitter blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IQmodulator and TXAGC in HAGAR IC . . . . . . . . . . . . . EGSM TX saw filter 725057 . . . . . . . . . . . . . . . . . . . . . . . . . Diplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TXbuffer and 3dB attenuator . . . . . . . . . . . . . . . . . . . . . . . . Dualband power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . Directional coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizer blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 35 3 36 3 36 3 36 3 37 3 38 3 38 3 38 3 40 3 40 3 40 3 41 3 41 3 41 3 42 3 43 3 44 3 44 3 45 3 46 3 46 3 48 3 48 3 48 3 49 3 49 3 50 3 50 3 50 3 50 3 51 3 51 3 51 3 52 3 52 3 53 3 53 3 53 3 54 3 54 3 54 3 55 3 56 3 56 issue 1 06/01
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VCTCXO, reference oscillator . . . . . . . . . . . . . . . . . . . . . . . . SHF PLL in HAGAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCO module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF connector and antenna switch . . . . . . . . . . . . . . . . . . . . . . RFSystem interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit power Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizer clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 56 3 56 3 57 3 58 3 58 3 58 3 58 3 62 3 62 3 62
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Abbreviations
ACCIF A/D ADC AFC AGC AMM API ARM ASIC AVG BB BGA bl8 BLL3 CCONT CCR CHAPS CMT COBBA COBBA_GJP CRFU3 CSD CSP CTSI D/A DAC DCD DCE DCT3 DNL DMA DL2 DSP DTMF DTR EAD EMC EMI ESD FBUS FFS GPIO ACCessory InterFace block of MADLinda AnalogtoDigital AnalogtoDigital Converter Automatic Frequency Control Automatic Gain Control ARM MegaModule ARM Port Interface in LMM Advanced RISC Machines Application Specific Integrated Circuit Average Baseband Ball Grid Array package RAE-3 System/RF module LitiumIon battery back for RAE-3 Multifunction power management IC for DCT3 used in bl8 system HW Clock Configuration Register in MADLinda DCT3 Charging control ASIC used in bl8 system HW Cellular Mobile Transceiver DCT3 RFinterface and Audio codec IC Serial control interface version of COBBA used in bl8 system HW UHF RF IC used in bl8 RF HW Cardspecific Data, register in MultiMediaCards Chip Scale Package Clocking, Timing, Sleep & Interrupt block of MADLinda DigitaltoAnalog DigitaltoAnalog Converter Data Carrier Detect Data Communication Equipment 3rd generation Digital Core Technology Differential nonlinearity Direct Memory Access RAE3 Color UI module Digital Signal Processor Dual Tone Multi Frequency Data Terminal Ready External Accessory Detect Electromagnetic Compatibility Electromagnetic Interference Electrostatic Discharge Full Duplex Serial Bus in NOKIA's phones Flash File System General Purpose Input/Output (block in MADLinda) issue 1 06/01
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HAGAR HF HSCSD HW IC ICE INL IO IR IrDA JTAG LCD LEAD LEAD2 LMM MAD MAD2 MAD2PR1 MAD2WD1 MADLinda MBUS MCU MFI MMC MMU MPU NTC PCI PCM PCR PDA PHF PLL PMM PPM PUP PWB PWM R&D RAM RF RFI ROM RTC SCU
Direct conversion RF ASIC used in bl8 RF HW Hands Free High Speed Circuits Switched Data Hardware Integrated Circuit InCircuit Emulator Integral nonlinearity Input/Output Infrared Infrared Data Association Joint Test Action Group, commonly used as a synonym for boundary scan (IEEE 1149.1) testing Liquid Crystal Display Low power Enhanced Architecture DSP Digital Signal Processor block of MADLinda LEAD2 MegaModule DSP module in MADLinda MCU+ASIC+DSP chip (MCUASICDSP) GSM version of MAD A pin reduction version of the MAD2 High Speed Data version of MAD2 by Wireless Data MAD based version of RAE-3 Communicator ASIC 1wire half duplex serial bus in NOKIA's phones Micro Controller Unit Modulator and filter interface in MAD2 MultiMediaCard Memory Management Unit Micro Processor Unit in text refers to MADLinda's ARM9 processor Negative Temperature Coefficient (resistor) Phone Control Interface Pulse Code Modulation Pin Configuration Register in MADLinda Personal Digital Assistant Personal Hands Free Phase Locked Loop Permanent Memory Management block (Plato UI) Post Programmable Memory PIO, USART and PWM block of MADLinda Printed Wiring Board Pulse Width Modulation Research and development Random Access Memory Radio Frequency RF Interface Read Only Memory Real Time Clock Synthesizer Control Unit
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SCR SDRAM SIM SIMIF SIR SPI Spock SSR SUMMA SW TAP TI TVS UART USART UI UI1 VCTCXO VCXO VIA WD1 XIP (TBC) (TBD)
System Configuration Register in MADLinda Synchronous Dynamic RAM Subscriber Identify Module Subscriber Identify Module Interface Serial Infrared (speed 115.2kbit/s) Serial Peripheral Interface Second generation communicator RAE2 System Status Register in MADLinda VHF RF IC used in bl8 RF HW Software Test Access Port (Boundary Scan) Texas Instruments Transient Voltage Suppressor Universal Asynchronous Receiver Transmitter Universal Synchronous/Asynchronous Receiver Transmitter User Interface RAE-3 Black&White UI module Voltage Controlled Temperature Compensated Oscillator Voltage Controlled Oscillator Versatile Interconnection Architecture (inside MADLinda) Wireless Data Engine 1 Execute In Place (memory) (To be checked) (To be defined)
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RAE-3 Structure
This document specifies the system HW part of RAE3 GSM900/GSM1800 Dual Band Communicator. The BL8 module contains both the system hardware and the RF components. The system part of the BL8 module functions as a combined CMT baseband and PDA engine.
RAE-3 Modules
DL2 Color UI module
UL8 QWERTY flex module
BL8 SYSTEM/RF module MIC
Lithium Battery BLL3 (LiIon)
Battery removal switch
Ear Audio piece holder HF speaker
Figure 1. RAE3 modules
List of Modules
Table 1. List of submodules Name of module RF&System User Interface Keyboard and Hinge flex MRAE3 Type code BL8 DL2 UL8 Material code 0201278 0201282 0201667 0261997 Notes GSM phone + PDA module, European FLASH mem PDA + CMT displays, Colour LCD Audio PWB and connectors Mechanical assembly parts , no language dependent parts
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Technical Summary of System Part
The RAE-3 system hardware is based on a special version of the DCT3 MAD2 ASIC called MADLinda. MADLinda carries out all the signal processing and operation controlling tasks of the phone as well as all PDA tasks. To be able to run simultaneously both CMT and PDA applications, MADLinda (ROM1) has a 52MHz ARM9 core. MADLinda's main blocks include: ARM925 MPU Subsystem, Traffic Controller (TC), LEAD2 DSP megamodule (LMM), GSM System Logic and PDA peripherals. ARM925 MPU Subsystem includes ARM9TDMI core, data and instruction caches, data and instruction memory management units (MMU) and write and address buffers. Traffic Controller includes primary DMA controller, LCD controller and Flash and SDRAM memory interfaces. The System Logic of MAD2 is able to support high speed data features (HSCSD). PDA peripherals include interfaces for Serial Flash, MMC, IrDA, serial port, IOs and PWMs. In addition of the MADLinda IC the system hardware includes memories, infrared transceiver, COBBA_GJP, CCONT and CHAPS ASICs, audio amplifier and power regulators. CSP packages are used for all ASICs. System HW also has connectors for MultiMediaCard (MMC) and SIM card, UI connector and pads for system connector's spring contacts. Three XIP Flash devices are used for program code storage. A serial Flash device is used half for the Flash file system and half to save application code. A synchronous DRAM (SDRAM) device is used as data memory. Code can also be run from the SDRAM. This is used to run applications loaded from Serial Flash or MultiMediaCard. The main battery voltage range in RAE-3 is 3.0V to 4.2V. Battery charging is controlled in SW using CCONT and CHAPS ASICs. RAE-3 can also supply 3 V(max 100mA) accessory voltage out from system connector. The system electronics run from a 2.8V power rail. 1.8V is used as core voltage inside MADLinda and as I/O voltage for XIP Flash memory interface. Power supplying of the BL8 module, both system HW and RF, and also 2.8V supplying for the UI module is carried out in system HW. A linear regulator is used to generate 2.8V VBB voltage and a DC/DC converter is used to generate the 1.8V Vcore voltage. Accessory voltage and MMC supply are generated with separate 3V linear regulators. Other supplies are generated using the CCONT power ASIC (4.7V needed in DCT4 RF is generated in RF side). CCONT generates also the main reset for the system. Both 3V and 5V Plugin SIMcards are supported. SIM is interfaced through CCONT, which does signal level shifting and generates correct supply voltage for SIM. A real time clock function is integrated into CCONT, which utilizes the same 32kHz clock supply as the sleep clock. A rechargeable backup battery provides backup power to run the RTC when the main battery is removed. The backup time is about 10 days. Note also the information in section 8 chapter 2.6. issue 1 06/01
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The interface from the system part and the RF and audio sections is handled by a specific ASIC COBBA_GJP. This ASIC provides A/D and D/A conversion of the inphase and quadrature receive and transmit signal paths and also A/D and D/A conversions of received and transmitted audio signals. Data transmission between the COBBA_GJP and the MADLinda is implemented using serial connections. Digital speech processing is executed by the MADLinda ASIC. External audio is connected to RAE-3 through system connector's XMIC and XEAR lines. Serial connection channels in RAE-3 include IrDA, MBUS, and serial port. MBUS and serial port have logic level signals which are connected through system connector. IR transceiver is next to the system connector at the bottom end of RAE-3 device.
Block Diagram
SERIALFLASH SDRAM XIP MEMORIES FLASH
MULTI MEDIA CARD CONNECTOR
MADLINDA
PDA PERIPHERALS ARM925 MPU SUBSYSTEM TRAFFIC CONTROLLER SYSTEM LOGIC LMM (DSP) HALL SENSOR IRDA
UI CONNECTOR
SYSTEM CONNECTOR SERIAL INTERFACES EXTERNAL AUDIO
UI SIGNALS
AUDIO
(EARP, SPEAKER)
EXTERNAL RF CHARGER
AUDIO AMP COBBA_GJP PCM CODEC
POWER AUDIO_RFI CCONT BACK UP BATTERY CHAPS BATTERY CONNECTOR RFI VBB REG. VCORE REG. VMMC REG.ACCPWR REG.
32KHZ XTAL
MIC
SIM CARD CONNECTOR
SYSTEM SUPPLIES
SYS RF
RF SUPPLIES
RF SIGNALS
Figure 2. RAE-3 SYSTEM PART BLOCK DIAGRAM
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Electrical Characteristics
Power Supply
Table 2.
Operating voltages and power consumptions
Min 3.4 3.0 3.6 450 Typ Max 18 4.8 Unit V V mA 4.8 4.8 2.86 400 V V V mA V Charging voltage Voltage directly from main battery to Vcore req. and RF part, typical for whole bl8 Filtered battery voltage to VBB req. and to UI Filtered battery voltage to CCONT and audio HF amplifier System HW supply voltage, typ. measured, max available from regulator Connected to MADLinda IO in assembled devise. Functions as program enable in 2.8V. Takes flashing current form Vcc pin Core voltage to MADLinda and XIP Flash IF typ. measured, max available form regulator MMC supply voltage max supported consumption level Accessory supply voltage output max current out Voltage to SIM, 5V selected (CCONT VSIM) 2) Voltage to SIM, 3V selected 2) COBBA_GJP analog supply (CCONT VR6) current during call, 4) To RF (CCONT VR1) Available from CCONT, 4) To RF (CCONT VR2) Available from CCONT, 4) To RF (CCONT VR4) Available from CCONT, 4) To RF (CCONT VR3) Available from CCONT, 4) To RF (CCONT VR5) Available from CCONT, 4) Notes
Name VIN VBATT
Parameter Voltage Voltage
VB VB_CCONT VBB
Voltage Voltage Voltage Current
3.0 3.0 2.74
3.6 3.6 2.8 45
FLVPP
Voltage
0
2.8
Current Vcore Voltage Current VMMC Voltage Current VACC Voltage Current VSIM Voltage Current Voltage Current VCOBBA Voltage Current VXO Voltage Current VRX Voltage Current VSYN_1 Voltage Current VSYN_2 Voltage Current VTX Voltage Current 2.7 2.7 2.7 2.7 2.7 4.8 3 2.8 1 2.7 3.03 2.74 1.7
36 1.8 70 3.0 1.9 300 3.1 100 3.3 3.4 100 5.0 10 3.0 6 2.8 15.7 2.8 2.85 63 2.8 2.85 63 2.8 2.85 63 2.8 2.85 50 2.8 2.85 63 5.2 30 3.2 30 2.85
uA V mA V mA V mA V mA V mA V mA V mA V mA V mA V mA V mA
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Table 2.
Operating voltages and power consumptions (continued)
Min 4.8 Typ 5.0 Max 5.2 30 1.478 1.500 1.523 Unit V mA V mA mA Notes To RF (CCONT V5V) Available from CCONT, 2) Reference voltage to COBBA_GJP and RF (VREF_2) (CCONT VREF) Available from CCONT, Consumption in system HW
Name VCP
Parameter Voltage Current
VREF
Voltage
Current Current
150 36
2) VCP and VSIM together max 30mA 4) Total current from CCONT VR1VR6 max 330mA rms
System Connector
Table 3. Electrical Pin 1 2 Name L_GND VIN Voltage in Current in Voltage in Current in Voltage in Current in 3 CHRG_ CTRL Output LOW Output HIGH PWM Frequency PWM duty cycle Output resistance 4 SGND Output AC impedance Series output capacitance Resistance to phone ground 5 XEAR Output AC impedance Series output capacitance Load AC impedance Load AC impedance Max. output level Load DC resistance Load DC resistance DC voltage Earphone signal 0 16 2.8 70 630 10 1500 16 4.7 10 1.8 1 22 47 10 330 47 10 300 0 2.4 32 99 8.5 10.0 350 0.5 2.85 6.8 7.8
characteristics of the system connector (X450) signals
Min 0 Typ 0 Max 0 30 1.5 8.8 850 14.0 Unit V V A V mA V mA V V Hz % k µF µF k Vpp k V mVrms ref. to SGND (Headset) ref. to SGND (Accessory) no load ref. to SGND (Accessory) ref. to SGND (Headset) 44k pullup to VBB HFHFCM from COBBA_GJP HF output ref. to GND ref. to GND Supply ground CHAPS' absolute max. input voltage Fusing current Unloaded Fast Charger (ACP9, LCH9) Charging current Unloaded Standard Charger (ACP7) Charging current Charger control (PWM) low Charger control (PWM) high fast charger connected Notes
Parameter
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Table 3. Electrical Pin 6 Name XMIC
characteristics of the system connector (X450) signals (continued)
Min Typ 2.2 1 1.47 2.5 100 0 1.55 2.8 600 0.22*VBB 2 4.7 270 0 0.7*VBB 0 0.7*VBB 270 0 0.8*VBB 0.22*VBB VBB 4 270 0 0.7*VBB 270 0.3*VBB VBB 0.3*VBB VBB 0.3*VBB VBB Max Unit k Vpp V V µA V mA k V V V V V V mA V V Accessory power output refer to VACC in NO TAG Data Terminal Ready input Internal pullup max. 140mA From AccTxData 47k Pullup to VBB in bl8 To AccRxData 220k Pullup to VBB in bl8 to VBB Open drain output Accessory muted (not for headset) Accessory unmuted Notes
Parameter Input AC impedance Max. input signal Output DC level Output DC level Bias current
7
MBUS
Output LOW Output LOW current Pullup resistance Series resistance Input LOW Input HIGH
8
DCE_TX
Input LOW Input HIGH Series resistance
9
DCE_RX
Output LOW Output HIGH Output current Series resistance
10
DCE_DTR
Input LOW Input HIGH Series resistance
11 12 13 14 15
GND RF_GND RF_INTERNAL RF_COMMON RF_GND
0
0
V
Supply ground
To internal antenna defined in RF spec NO TAG From RF defined in RF spec NO TAG
Battery Connector
Table 4. Battery Connector (X100) Electrical Specifications
Pin 1 Name VBATT Min 3.0 Typ 3.6 Max 4.2 4.8 2 BSI 0 2.8 Unit V V V Notes Battery voltage Maximum voltage with charger Battery size indication System HW has 100kW 5% pull up resistor. Battery removal detection (shorter contact) (Threshold is 2.4V@VBB=2.8V) 22±1% 68±5% kW kW Service battery pull down value 4.2V LiIon battery pull down value
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Table 4. Battery Connector (X100) Electrical Specifications
Pin 3 Name BTEMP Min 0 Typ Max 1.4 Unit V
(continued)
Notes
Battery temperature indication Phone has 100k 5% pullup resistor, Battery package has NTC pull down resistor: @+25C 47k 5%, B=4050±3% Fast power up (in production) Battery ground connected directly to system HW GND
0 4 BGND 0
1 0
kW V
Backup battery connector
Table 5. Backup battery connector X102
Pin 1 2 Name VBACK IN VBACK OUT Min 2.82 1.8 Typ 3.15 Max 3.28 3.3 Unit V V Notes Backup battery voltage from CHAPS @ Ibackup = 100mA Backup battery voltage to CCONT/VBACK (not specified in CCONT spec)
VBACKIN and VBACKOUT are connected together in back up battery's positive terminal.
Table 6. Microphone contacts
Pin 1 2 Name MICP MICN Min Typ Max 0.1 0.1 0.2 2.0 2.1 Unit Vpp Vpp Vpp V Notes Pad P200 Pad P201 MICPMICN differential voltage range MICP, MICN biasing output level
SIM card connector
Only Plugin SIM (small SIM) cards are supported.
Table 7. SIM Connector (X101) Electrical Specifications
Pin Signal Name Type 4 3 GND VSIM GND VCC (C1) GND Supply Voltage Supply Voltage 6 SIMDATA I/O (C7) Vout HIGH Vout HIGH Vout LOW Trise/Tfall I/O Series Resistance 100 0 4.8 2.8 4.0 2.8 0 5.0 3.0 0 5.2 3.2 VSIM VSIM 0.4 1 V V V V V V mS W Ground 5V SIM Card 3V SIM Card 5V SIM Card 3V SIM Card 3V/5V SIM Card 3V/5V SIM Card (Vin not defined in CCONT specification ) SIM Contact Parameter Min Typ Max Unit Notes
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Table 7. SIM Connector (X101) Electrical Specifications
Pin Signal Name Type 2 SIMRST RST (C2) Vout HIGH Vout HIGH Vout LOW Trise/Tfall O 1 SIMCLK CLK (C3) Series Resistance Vout HIGH Vout HIGH Vout LOW Frequency Trise/Tfall O 5 VSIM VPP (C6) Series Resistance Supply Voltage Supply Voltage 4.8 2.8 47 5.0 3.0 5.2 3.2 3.25 25 4.0 2.8 100 VSIM VSIM 0.4 4.0 2.8 VSIM VSIM 0.4 100 SIM Contact Parameter Min Typ Max
(continued)
Unit Notes
V V V ns W V V V MHz ns W V V
5V SIM Card 3V SIM Card 3V/5V SIM Card 3V/5V SIM Card
5V SIM Card 3V SIM Card 3V/5V SIM Card 3V/5V SIM Card 3V/5V SIM Card
Programming voltage, pin5 and pin3 tied together
MMC Connector
Table 8. MMC Connector Electrical Specifications
Pin Signal Name Type 7 MMCDa 7 / DAT[0] Output HIGH Output LOW Input HIGH Input LOW I/O 6 5 GND MMCClk 6 / VSS2 5 / CLK Output HIGH Output LOW Frequency O 4 VMMC 4 / VDD Series Resistance powered on powered off Current 3 2 GND MMCCmd 3 / VSS1 2 / CMD Output HIGH Output LOW Input HIGH I/O Input LOW Series Resistance 100 2.1 0 2.1 2.76 0 100 3.0 3.1 0 100 0 2.9 0.65 2.9 0.8 mA V V V V V W There is 10k Pullup to VMMC in bl8 Supply Current Ground Command/Response Series Resistance 0 2.1 100 0 2.9 0.65 13 2.1 2.1 2.9 0.65 3.1 0.8 V V V V W V V V MHz W V Supply voltage Ground Clock There is 100k Pullup to VMMC in bl8 Data MMC Contact Parameter Min Typ Max Unit Notes
Note: There is no pin 1 in connector (Not connected in MultiMediaCard mode; SPI mode not supported issue 1 06/01
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Infrared interface
IrDA and HPSIR compatible Data rates from 9600bits/s to 115kbits/s Transmitter wavelength: min 880nm, max 900nm
UI Signals
Table 9. UI Connector
Pin Signal Name Type 27, 28, 29 15 VB Main battery Flash Vpp 3.0 From/To Parameter Minimum Nominal Maximum Unit Function
4.8
V
Battery voltage
FLVPP not UI signal
pins 15 and 16 connected in UL8 pins 15 and 16 connected in UL8 2.7 0 2.85 2.9 0 V Supply voltage Supply ground
16
VPROG not UI signal
MADLinda (Prog_IO)
17 1, 8, 21, 25, 30, 34, 41, 66, 70 49
VBB GND
COL0 I/O
MADLinda (Prog_IO) (Prog IO)
Output high "1" Output low "0" Output current Input high "1" Input low "0" Series resistance
0.8*VBB 0.22*VBB 2 0.7*VBB 0.3*VBB 200
V V mA V V W
Keyboard column
62
COL1 I/O
MADLinda (Prog_IO) MADLinda (Prog_IO) MADLinda (Prog_IO) MADLinda (Prog_IO) MADLinda (Prog_IO) MADLinda (Prog_IO) MADLinda (Prog_IO) MADLinda (Prog_IO)
(Refer to COL0)
Keyboard column
60
COL2 I/O
(Refer to COL0)
Keyboard column
35, 59 33, 54 55
COL3 I/O COL4 I/O COL5 I/O
(Refer to COL0)
Keyboard column
(Refer to COL0)
Keyboard column
(Refer to COL0)
Keyboard column
56
COL6 I/O
(Refer to COL0)
Keyboard column
61
COL7 I/O
(Refer to COL0)
Keyboard column
53
COL8 I/O
(Refer to COL0)
Keyboard column
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Table 9. UI Connector
Pin Signal Name Type 51 COL9 I/O 50 ROW0 I/O MADLinda (Prog_IO) MADLinda (Prog_IO) (Prog IO) (Refer to COL0) From/To Parameter
(continued)
Nominal Maximum Unit Function
Minimum
Keyboard column
Output high "1" Output low "0" Output current Input high "1" Input low "0" Series resistance
0.8*VBB 0.22*VBB 2 0.7*VBB 0.3*VBB 200
V V mA V V W
Keyboard row
69
ROW1 I/O
MADLinda (Prog_IO) MADLinda (Prog_IO) MADLinda (Prog_IO) MADLinda (Prog_IO) MADLinda (Prog_IO (Prog IO / UIF)
(Refer to ROW0)
Keyboard row
67
ROW2 I/O
(Refer to ROW0)
Keyboard row
65
ROW3 I/O
(Refer to ROW0)
Keyboard row
64
ROW4 I/O
(Refer to ROW0)
Keyboard row
32, 63
ROW5LCDCD I/O
Output high "1" Output low "0" Output current Input high "1" Input low "0" Series resistance
0.8*VBB 0.22*VBB 2 0.7*VBB 0.3*VBB 200
V V mA V V W
Serial LCD driver Command/Data select
Keyboard row
57
ROW6 I/O
MADLinda (Prog_IO) MADLinda (Prog_IO) MADLinda (Prog_IO) MADLinda (Prog_IO)
(Refer to ROW0)
Keyboard row
68
ROW7 I/O
(Refer to ROW0)
Keyboard row
58
ROW8 I/O
(Refer to ROW0)
Keyboard row
52
ROW9 I/O
(Refer to ROW0)
Keyboard row
42
BATT_REM I
MADLinda (GPIO)
Input high "1" Input low "0" Series resistance
0.7*VBB 0.3*VBB 200
V V W
Battery removal switch
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Table 9. UI Connector
Pin Signal Name Type 11 GenSClk O MADLinda (UIF), ( ), (and to CCONT) Output high "1" Output low "0" Output current Frequency 0 From/To Parameter
(continued)
Nominal Maximum Unit Function
Minimum
0.8*VBB 0.22*VBB 2 3.25
V V mA MHz
Serial LCD driver clock (Phone LCD) ( )
3.25MHz during Phone LCD access, 2.17MHz during CCONT access
Series resistance 9 GenSDIO O MADLinda (UIF) Output high "1" Output low "0" Output current Series resistance 0.8*VBB
200
W V 0.22*VBB 2 V mA W Serial LCD driver data (Phone LCD)
200
12
LCDEN O
MADLinda (UIF)
Output high "1" Output low "0" Output current Series resistance
0.8*VBB 0.22*VBB 2 200
V V mA W
Serial LCD driver chip select (Phone LCD)
10
LCDPWM O
MADLinda (PWM)
Output high "1" Output low "0" Output current Series resistance Frequency
0.8*VBB 0.22*VBB 2 200 0 0.8*VBB 0.22*VBB 2 200 0 231 50.7
V V mA W
PWM for PDA LCD contrast control
kHz
V V mA W PWM for PDA LCD backlight control
31
BACKPWM O
MADLinda (PWM)
Output high "1" Output low "0" Output current Series resistance Frequency
Hz
V 0.22*VBB 2 V mA W PDA LCD power control
6
LCD_PWR O
MADLinda (GPIO)
Output high "1" Output low "0" Output current Series resistance
0.8*VBB
200
14
LCDRSTX O
MADLinda (GPIO)
Output high "1" Output low "0" Output current Series resistance
0.8*VBB 0.22*VBB 2 200
V V mA W
Phone LCD reset
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Table 9. UI Connector
Pin Signal Name Type 13 KBLIGHTS O MADLinda (GPIO) Output high "1" Output low "0" Output current Series resistance From/To Parameter
(continued)
Nominal Maximum Unit Function
Minimum
0.8*VBB 0.22*VBB 2 200
V V mA W
Phone LCD & keyboard light control
5
LCDDa0 O
MADLinda (LCD)
Output high "1" Output low "0" Output current Series resistance
0.8*VBB 0.22*VBB 2 200
V V mA W V
PDA LCD data
26
LCDDa1 O
MADLinda (LCD) MADLinda (LCD) MADLinda (LCD) MADLinda (LCD/GPIO) MADLinda (LCD/GPIO) MADLinda (LCD/GPIO) MADLinda (LCD/GPIO) MADLinda (LCD/GPIO) MADLinda (LCD/GPIO) MADLinda (LCD) MADLinda (LCD)
(refer to LCDDa0)
PDA LCD data
24
LCDDa2 O
(refer to LCDDa0)
V
PDA LCD data
38
LCDDa3 O
(refer to LCDDa0)
V
PDA LCD data
20
LCDDa4 O
(refer to LCDDa0)
V
PDA LCD data
36
LCDDa5 O
(refer to LCDDa0)
V
PDA LCD data
37
LCDDa6 O
(refer to LCDDa0)
V
PDA LCD data
22
LCDDa7 O
(refer to LCDDa0)
V
PDA LCD data
19
LCDDa8 O
(refer to LCDDa0)
V
PDA LCD data
23
LCDDa9 O
(refer to LCDDa0)
V
PDA LCD data
39
LCDDa10 O
(refer to LCDDa0)
V
PDA LCD data
7
LCDDa11 O
(refer to LCDDa0)
V
PDA LCD data
2
DISPClk O
MADLinda (LCD)
Output high "1" Output low "0" Output current Frequency Series resistance
0.8*VBB 0.22*VBB 2 8.67 200 0.8*VBB 0.22*VBB 2 10.8
V V mA MHz W V V mA kHz
PDA LCD data clock
40
LLClk O
MADLinda (LCD)
Output high "1" Output low "0" Output current Frequency
PDA LCD line data latch to displa display
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Table 9. UI Connector
Pin Signal Name Type Series resistance 4 FSP O MADLinda (LCD) Output high "1" Output low "0" Output current Frequency Series resistance 3 DISPON O MADLinda (GPIO) Output high "1" Output low "0" Output current Series resistance 18 LCDM O MADLinda (LCD) Output high "1" Output low "0" Output current Frequency Series resistance From/To Parameter
(continued)
Nominal 200 Maximum Unit Function
Minimum
W V 0.22*VBB 2 V mA Hz W V 0.22*VBB 2 V mA W V 0.22*VBB 2 V mA kHz W PDA LCD modulation signal (Polarity change) PDA LCD display logic on/off control, control ( (MPUGenOut7 internally in MADLinda) PDA LCD frame start sync pulse s nc p lse
0.8*VBB
51.6 200 0.8*VBB
200 0.8*VBB
10.8 200
48
EARP O
COBBA_GJP
Maximum Output swing Vpp Maximum Output swing Vpp EARP/N Offset Load resistance
2.36
2.5
V
Earpiece
47
EARN O
COBBA_GJP
2.36
2.5
V
(signal details NO TAG)
50 32
50
mV W
43, 44 45, 46
SPKP O SPKN O
Audio Amp
Output level
1.8
Vrms
HF Speaker
Audio Amp
Output level
1.8
Vrms
(signal details NO TAG)
Load resistance
8
W
System RF interface
Table 10. AC and DC Characteristics of signals between RF and System blocks
Signal name VBATT VREF VXO VSYN_1 From Main battery CCONT (VREF) CCONT (VR1) CCONT (VR4) PA RF (HAGAR) VCTCXO Vdd_bb, LNAs To Parameter Voltage Voltage Voltage Voltage Minimum 3.0 1.478 2.7 2.7 Typical 3.6 1.5 2.8 2.8 Maximum 4.8 1.523 2.85 2.85 Unit V V V V Function PA supply voltage (NO TAG) Reference voltage for RF (NO TAG) Supply voltage for VCTCXO (NO TAG) Supply voltage for LNAs and Vdd_bb (NO TAG)
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Table 10. AC and DC Characteristics of signals between RF and System blocks (continued)
Signal name VSYN_2 From CCONT (VR3) CCONT (5V5) CCONT (VR2) CCONT (VR5,VR7) MADLinda To HAGAR, VCO Charge pump regulator HAGAR Parameter Voltage Minimum 2.7 Typical 2.8 Maximum 2.85 Unit V Function Supply voltage for dividers, LO buffers, prescalers and VCO (NO TAG) Supply voltage for PLL charge pump regulator (NO TAG) Supply voltage for LNA2 + mixer + DTOS (NO TAG) Supply voltage for TX modulator (NO TAG) HAGAR reset, active LOW
VCP
Voltage
4.8
5.0
5.2
V
VRX
Voltage
2.7
2.8
2.85
V
VTX HAGARRSTX
HAGAR HAGAR
Voltage Output high "1" Output low "0" Output Current
2.7 0.8*VBB 0
2.8
2.85 VBB 0.22*VBB 2
V V V mA V V mA V V mA Mbit/s
SENA1
MADLinda
HAGAR
Output high "1" Output low "0" Output Current
0.8*VBB 0
VBB 0.22*VBB 2
HAGAR synthesizer interface enable
SDATA
MADLinda
HAGAR
high "1" low "0" Output Current Data rate
0.8*VBB 0
VBB 0.22*VBB 2 3.25
HAGAR synthesizer interface control data
SCLK
MADLinda
HAGAR
Output high "1" Output low "0" Output current Clock rate
0.8*VBB 0
VBB 0.22*VBB 2 3.25
V V mA MHz
HAGAR synthesizer interface clock
AFC
COBBA_GJP
VCTCXO
Voltage Resolution Load resistance (dynamic) Load resistance (static)
0.046 11 10
2.254
V bits kW
Automatic frequency control signal for VC(TC)XO ( )
1 13 0.5 10 1 1.0 2.0
MW MHz Vpp kW nF Series S i capacitance it High stability clock signal from RF block, block
RFC
VCTCXO
MADLinda
Frequency Signal amplitude Load resistance Load capacitance
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Table 10. AC and DC Characteristics of signals between RF and System blocks (continued)
Signal name RXIP From HAGAR To COBBA_GJP Parameter Output level Input impedance Input capacitance RXQP HAGAR COBBA_GJP Output level Input impedance Input capacitance RXREF COBBA_GJP HAGAR Output Voltage Output Impedance External serial load Load Current TXIP/ TXIN COBBA_GJP HAGAR Differential voltage swing DC level Output impedance TXQP/TXQN COBBA_GJP HAGAR Differential voltage swing DC level Differential offset voltage (corrected) Diff. offset voltage temp. dependence Output impedance TXP MADLinda HAGAR Output high "1" Output low "0" Output Current 2.1 0 1.022 1.165 1.1 1.2 1.022 1.165 9 100 1.1 1.2 1.18 1.235 500 1.18 1.235 +/ 2.0 1.15 Minimum Typical 300 1 8 300 1 8 1.2 3 1.25 200 1400 Maximum 1400 Unit mVpp MW pF Vpp MW pF Vpp W kW mA Vpp V W Vpp V mV Differential quadrature phase TX baseband signal for the TX I/Q modu modulator sink or source Differential inphase TX baseband signal for the TX I/Q modulator Reference voltage for RX signals Single ended quadrature RX signal to baseband Function Single ended inphase RX signal to baseband
+/ 1.0
mV
500 2.9 0.8 2
W V V mA Transmitter power control enable
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Table 10. AC and DC Characteristics of signals between RF and System blocks (continued)
Signal name TXC From COBBA_GJP To HAGAR Parameter Voltage Min level Voltage Max level Output impedance active state Output impedance power down state External resistance External capacitance Settling time 10 10 10 high Z Minimum 0.12 2.27 Typical Maximum 0.18 2.33 200 Unit V V W Function Transmitter power control voltage
kW pF ms
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Functional Description
Modes of Operation
There are three main operation modes in the system when power is on: Running Idle Deep Sleep Note that phone can be either on or off in each of power on states.
Power OFF Too low Battery voltage or Battery removed Interrupt Running (VCXO ON) Deep Sleep (VCXO OFF)
Battery voltage high enough Reset Power Up
Interrupt Idle (VCXO ON)
No tasks to run
Deep Sleep conditions met
Figure 3. Basic Operation Modes of RAE-3 (simplified scheme)
Power saving modes are entered under SW control. Returning to running mode is activated by interrupt (generated internally by MADLinda or from CCONT).
Clocking Scheme
The 26MHz main clock frequency is generated by the VCTCXO located in the RF section. This clock is divide in HAGAR to 13MHz. Clock signal is buffered to low level sine wave clock signal (RFC) and fed to system HW side. There it is connected to MADLinda clock input. The MPU within MADLinda can stop the clock by shutting off the VCTCXO's supply voltage (VXO) via CCONT. The CCONT provides a 32kHz sleep clock generated from 32.768kHz quartz crystal. This clock signal is used internally in CCONT to run the RTC and routed to MADLinda (SLEEPCLK). Sleep clock is used to run MADLinda when the main clock is shut down. A backup battery keeps the RTC running if the main battery is disconnected.
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Other clock signals are generated inside MADLinda using PLLs and clock dividers which are controlled by SW. The maximum clock frequency in the MPU side is 52MHz and in the DSP side 78MHz. NO TAG shows the System HW clocking scheme.
Power Control and Reset
In normal operation the system HW is powered from the main battery. An external charger can recharge the battery while also supplying power to RAE-3. The supplied charger is so called performance charger (ACP9), which can deliver 850mA. The power management circuitry provides protection against overvoltages, charger failures and pirate chargers etc. that would otherwise cause damage to RAE-3. Following chapters give an overview about power management issues.
Power Distribution
Figure 4 shows the power distribution of RAE-3. Power supply components CCONT, VBB, Vcore, VACC and VMMC regulators and the audio amplifier are powered with main battery voltage. Main battery voltage is also fed to RF part for RF power amplifier (PA) and to the UI module for backlight and LCD supply. Separate linear regulator generates the 2.8V VBB power supply. VBB powers most of the system HW portions including MADLinda, memories, COBBA_GJP's digital supply and the logic parts of the IR transceiver. It also supplies 2.8V to the UI module. Separate DC/DC regulator generates the 1.8V Vcore voltage. Vcore is used as supply for the MADLinda core and as IO voltage for XIP memories. CCONT's V2V output is used as enable for VBB and Vcore regulators. VSIM regulator of CCONT is used to generate either 3V or 5V supplies for SIM card. This is required so that RAE-3 can support both 3V and 5V SIM cards. VR6 generates the voltage for COBBA_GJP's analogue part. CCONT generates the reference voltage VREF for COBBA_GJP and HAGAR. It also generates the 5V supply voltage (V5V) for RF. In RF side there is separate regulator that drops this voltage to 4.7V for DCT4 RF use. Regulators VR1 to VR5 inside CCONT generate voltages for RF HW. Regulator control signals come from MADLinda. Separate 3V linear regulator is used to power the MMC card. Another 3V linear regulator is used to generate accessory power that can be fed through system connector for external accessory. issue 1 06/01
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Figure 4. Power Distribution of RAE-3
3.7V
BATTERY
VBATT
VB
PA
VPC (HAGAR) Audio Amp.
MMC
3.0V LINEAR REG.
Backlight Power
IR LEDs
3.0V LINEAR REG.
Vacc Power Out VXOPWR SYNTHPWR TXPA
VB_CCONT VBB CCONT VXO 2.8V LINEAR REG. VB 1.8V DC/DC VBATT VSYN_2 VRX VSYN_1 VTX VCOBBA VSIM COBBA HAGAR bias VCP V2V VR 1 VR 2 VR 3 VR 4 VR 5 VR 6 VR 7
VSIM
VREF
V5V
VCTCXO + buffers
LNA
COBBA Analog
3. RF+System Module BL8
SIM
MADLinda VBB FLASH SERIAL FLASH SDRAM IR LOGIC COBBA DIGIT. INTERFACES CMT LCD PDA LCD VBB
MADLinda Core LMM MADLinda I/O FLASH I/O Vcore TXC TXP
HAGAR RFIC RX / TX parts PLL
RXREF
VCO
HAGARRSTX
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VCHP HAGARRSTX
4.7V LINEAR REG. SYSTEM HW PARTS
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Power up
When main battery is connected to device, powering on circuitry keeps CCONT PWRONX/WDDISX pin connected to ground through10kW resistor as long as CCONT releases the PURX reset signal. This activates the CCONT immediately when battery is connected. When the CCONT is activated, it switches on internal baseband and core regulators and generates a power up reset signal PURX for MADLinda. External Vcore and VBB regulators are powered up, Vcore slightly before VBB. After 62ms CCONT releases the PURX reset signal. When the PURX is released, MADLinda releases the system reset (ExtSysResetX), the Flash reset (FLRPX) and internal reset signals and starts the boot program execution. Note that from battery plug in to PURX release it takes about 100ms since there is no power in CCONT. The GenSDIO pin is connected low with pulldown resistor so that booting starts from MADLinda's internal boot ROM. If booting is successful (and the programming device is not connected) the program execution continues from external program memory. The CMT power switch (on the cover) is read as a normal keyboard input. It is not connected to CCONT. CMT Power switch only turns the phone functionality on or off (SW implementation).
Power Off
RAE-3 electronics is powered off only if the main battery voltage drops below the power off SW limit. This happens when the main battery discharges or is removed. When battery voltage drops below SW limit, CCONT is powered down by letting CCONT's watch dog to go off. Early warning of battery removal is generated by the battery removal switch. Switch connects MADLinda's MPUGenIO6 to ground when user presses the locking latch of the battery. Only phone functionality is "powered off" when the CMT power switch is pressed. If the main battery is removed when the CMT is on, the SIMIF in MADLinda powers down the SIM.
Charging
Charging of main battery can be started in any operating mode. The battery type and capacity are identified by MADLinda by measuring a pulldown resistor connected to BSI contact inside the battery pack. Charging software running in MADLinda's MPU measures the battery voltage, size, current and temperature. In Standard charger concept (2wire charger) the power management circuitry controls the charging current delivered from the charger to the main battery. The chargingcurrent switch inside CHAPS is controlled with 1Hz PWM signal, issue 1 06/01
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generated by CCONT. Note that Standard charger is not sold with RAE-3, but it is accepted. In performance charging concept (3wire charger) a 32Hz PWM signal is fed to the charger (CHRG_CTRL in system connector). This high rate keeps the chargingcurrent switch in CHAPS continuously connected. The PWM pulse width is controlled by the MPU in MADLinda which sends a control value to CCONT through a serial control data bus. The main battery voltage rise is limited to a specified level by turning the switch off. Lower limit (4.8V) in CHAPS is permanently selected because only lithium batteries are supported. Charging current is monitored by measuring the voltage drop across a sensor resistor.
Icharge in CHAPS IC (CONTROL SWITCH)
* WakeUp Charge * Voltage protect CHARGE CONTROL (PWM in 3wire concept) CHARGE CONTROL (PWM in 2wire concept)
BATTERY PACK
* 4.2V LiIon
Isupply out
BATTERY SENSING: * Voltage * Size/type * Temperature
CCONT IC
* A/D conversion * PWM output * Serial data in/out CHARGER AND BATTERY INTERRUPT
* Connect/disconnect detection
CHARGER SENSING
ASIC
SERIAL DATA
MPU DSP
Figure 5. Block diagram of charge control in RAE-3
MADLinda IC
Resets and Watchdogs
Powerup reset signal, PURX, is the main reset in RAE-3. PURX is generated by CCONT during poweron. The watchdog within CCONT is enabled and must be fed periodically to keep CCONT (and whole device) powered on. PURX signal is connected to MADLinda's reset input (PURX). Figure 6 shows the board/module level reset scheme in RAE-3.
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SIM
SIMRST
HAGAR (RF)
CCONT
CCONT WATCHDOG
SimCardRstX
HAGARRSTX
MADLinda
PURX
COBBARSTX
COBBA
ExtSysResetX LCDRSTX FLRPX
SER FLASH
UI conn. (To CMT LCD Controller)
Figure 6. Board/Module level reset scheme
FLASH
PURX resets the whole MADLinda. ExtSysResetX signal follows PURX activity during reset. After reset this signal can be configured as IO and thus controlled by SW with MPUGenOut8 control bit. The ExtSysResetX is connected to serial Flash reset pin. The LCD driver reset signal (LCDRSTX) is a MADLinda general purpose output controlled by MPU SW. Flash memory interface in Traffic Controller's MEMIF block includes Flash reset/power down signal (FLRPX). FLRPX signal follows PURX activity during reset. After reset this signal can be controlled by MPU SW. Signal is connected to XIP Flashes. MADLinda's SIM interface block generates the reset signal (SimCardRstX) for the SIM. This signal is fed through CCONT, which makes any level shifting necessary according to the voltage level of the SIM card in use. COBBA_GJP reset signal (COBBARSTX) is DSPGenOut0 general purpose output controlled by DSP SW. Reset state of the pin is LOW. HAGAR reset signal (HAGARRSTX) is DSPGenOut1 general purpose output controlled by DSP SW. Reset state of the pin is LOW.
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System to interface
In following chapters the blocks of system HW in SYSTEM part of BL8 schematics and functions related to each interface are described. The blocks include: CPU, MEMORIES, MMC, IRDA, UI, SYSCON, AUDIO_RFI and POWER. Component placement diagrams are in the A3 section.
CPU block
Main components in the CPU block comprise: MADLinda ASIC (D300), package 240 m*BGA Hall switch TLE4916 (V301) MADLinda is the main ASIC for RAE-3's single processor system. MADLinda is used as engine processor for both CMT and PDA functions. The pins are ot listed because it is not possible to access them except at measurement points. Hall sensor switch is used to detect lid position (open/close). Magnet for detection is in lid part of RAE-3. Hall device's open drain output is pulled up with external 100kW resistor (R302). Output goes to low state when the sensor is not in magnetic field (lid open).
MEMORIES block
Main components in the block include: three 2Mx16 (32Mbit) Flash memories (D351, D352, D353) SDRAM 4Mx16 (64Mbit) (D350) Serial Flash 32Mbit (D354)
XIP Memories
The MPU program code resides in three Flash memories. 128kBytes PPM area for language depend program parts is locate to one of the XIP flashes. Also 4*8kBytes PMM area and 4*8kBytes for EEPROM emulation (EEEMU) is located to that same flash device. Flashes are 4Mbyte (2Mx16) 80ns asynchronous 'Advanced Boot Block' devices packed in 48 pin CSP (VFBGA48). XIP memories are supplied from 2.8V VBB and I/O voltage from 1.8V Vcore.
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Connection in UL8 Flex
X400
UI Connector 15 16
D300
MADLinda DSPGenOut2
D351 VPP D352 VPP D353 VPP
XIP Flashes
Figure 7.
XIP Flash Vpp connection
SDRAM Memory
Synchronous DRAM is used as working memory and PDA display buffer memory. MADLinda includes a separate 16 bit wide interface for SDRAM device. Interface supports also byte accesses. Supported memory clocking speeds are 13MHz and 52MHz. The SDRAM is 64Mbits (8Mbyte) 104MHz device in 52pin CSP. Organisation of the memory is 4Mx16 with byte accesses possibility. Nominal supply voltage Vcc is 2.8V and it is supplied from the common VBB voltage. SDRAM supports self refresh mode. This mode is used in Deep Sleep mode when all clocks are off to preserve SDRAM data . All memory contents are lost when memory is unpowered, so when battery is removed or battery voltage drops under power off voltage.
Serial Flash Memory
Half of the Serial Flash memory is used as Flash file system memory (user data). The other half is used to load parts of application code to serial Flash (For running these applications are first copied to SDRAM). Serial interface to memory is controlled by the Serial Flash interface block in MADLinda. Used memory is 32Mbits (4Mbytes) SPI type Flash in 44 pin CSP package (CBGA44). Page size is 528 bytes. Memory is powered from 2.8V VBB. Maximum used clock rate is 13MHz. issue 1 06/01
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MMC block
Main components in MMC block are: MMC connector (X001) ESD protection zener array (V001) MultiMediaCard mode type serial interface to MultiMediaCard is controlled by the MMC interface block in MADLinda. The MMC interface includes two serial lines, command and data, and one clock line that is used to clock serial transfers in both lines. Used clock frequency is 13MHz. SPI mode MultiMediaCards are not supported in RAE-3. MultiMediaCard is powered with 3.0V supply using controllable regulator. Mechanical switch is used to indicate when the lid covering the MultiMediaCard (and SIM) is opened. Switch is integrated to RAE-3 Bcover mechanics. In BL8 there is only contact pad J001 for the signal. Hot swap as specified in MultiMediaCard System Specification is not supported. MultiMedaCard must be powered off (VMMC turned off) when lid is opened.
IRDA block
Main component in IRDA block is the IR transceiver TFDU5102 (N050). Data transmitting and receiving through IR interface is handled by IrDA block inside MADLinda. MPU controls the interface.
UI block
Components in UI block include: Boardtoboard UI connector (X400) Integrated EMI/ESD filtering components (Z400, Z401, Z402, Z403, Z404) QWERTY flex module UL8 is connected to UI connector. DL2 UI module is connected to system HW through UL8.
Phone LCD Interface
Phone LCD interface is controlled by MPU using LCDSIO part of MADLinda's internal UIF block. This same serial control interface is used also to command the CCONT. Phone LCD resetting and backlight control of LCD and phone keys are controlled by MPU using signals from MADLinda's GPIO.
Keyboard Interface
Keyboard interface is controlled by MPU using programmable I/O block inside MADLinda. I/O signal matrix is used to read both PDA keyboard (qwerty and soft keys) and phone keypad. To detect the key press ROWs are programmed to give interrupt when any of the keys is pressed. After key press detection SW polling is used to find out pressed key.
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Earpiece and HF Speaker lines
Earpiece and speaker lines come from the AUDIO_RFI block.
Battery removal signal
BATT_REM signal comes from the battery removal switch.
SYSCON block
Main components in system connector block include: System connector (X450) (pads for system connector's spring contacts) Coaxial connector for antenna cable (X499) ESD protection zener array (V451) For protecting the communicator against ESD spikes and EMI at the system connector, all lines are equipped with TVS and filtering devices located next to the system connector. The system connector includes the following group of contacts: DC jack for external plugin charger and contacts for desktop charger Contacts for external audios Contacts for serial connections External RF connector with switch Externally, the system connector resembles the system connector in N9110 Communicator. Figure 8 shows the pads on PWB and Figure 9 shows the connector. Serial connection signals are named in RAE-3's connector according to DCE type equipment (as in RAE2). This means that DCE_RX and DCE_DCD (MBUS line) are outputs and DCE_TX and DCE_DTR are inputs.
14 13 8 9 10 11
1
2 3 4 5 6 7
15 12
Figure 8.
Pads for system connector on top side of BL8
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DCE_TX
DCE_RX DTR
GND
Spring contacts to PWB
L_GND DC_jack VIN CHRG_CTRL SGND XEAR XMIC Guiding and locking holes External RF with switch MBUS
Figure 9.
System Connector
Serial connections
Serial interface signals are MBUS (DCE_DCD) [MBUS], DCE_RX [AccTxData], DCE_TX [AccRxData] and DCE_DTR [DTR]. First name is the contact name in the system connector and in square brackets is given the signal name used in schematics. Note that all these signals are logic level signals thus interface buffering/level sifting according some serial interface standards is done outside RAE3. MBUS is normally connected to PUP USART. When PUP USART is selected to be connected to transmit and receive lines (FBUS use) MBUS is not usable as a serial signal. In synchronous mode MBUS is used as USART's clock input. Synchronous mode is used in DCT3 type Flashing. DTR handshaking input is connected to MPUGenIO0. Accessory power output (VACC) is also fed through the DCE_DTR pin. Diode V489 prevents cable's signal output to supply power to BL8, when main battery is not connected, and accessory power regulator to supply 3V directly to MADLinda's input. Pullup R310 is thus needed to generate the high level state of DCE_DTR input to MPUGenIO0.
External Audio Interface
External audio signals, XMIC and XEAR, come from AUDIO_RFI block (see p.38 ). An external headset accessory, car kit or loop set can be connected to the external audio lines. External audio lines are also used to detect different accessories.
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Charger Interface
Charger voltage input line V_IN is connected through 1.5A fuse (F450) to CHAPS (charger control) ASIC's VCH inputs. Divided (47k/4k7) V_IN voltage level is connected to CCONT's VCHAR ADC input. Charger controlling PWM output line, CHRG_CTRL, comes from CCONT's PWM output (PWM_OUT).
External RF
External RF signal comes from RF section of BL8. RF connector in system connector includes switch for external/internal signal routing. When external RF plug is not connected to the system connector, RF signal is connected to coaxial antenna cable connector (X499).
POWER block
Power block includes following functions: supply voltage generation for system and RF parts and 2.8V to UI control of main battery charging power on and power off controlling and reset generation RTC and RTC backup control sleep clock generation SIM interface A/D conversions powering of MultiMediaCard Accessory power output generation (through System Connector) Main components in power block are: CCONT2M power ASIC (N100) CHAPS charging control ASIC (N101) Linear regulator (N102) for VBB DC/DC switching regulator (V105) for Vcore Linear regulator (N103) for MultiMediaCard powering (VMMC) Linear regulator (N104) for Accessory power output (VACC) FET (V108) for control of regulators N102 and V105 32.768kHz crystal oscillator (32k XTAL B100) 2.7V reset device (D101), NC7SZ175 Dflipflop (D102) and fets (V102, V106) for power on & off control 2.0V reset device (D100) for backup disconnection ESD protection zener array (V103) for SIM interface 2pin connector (X102) for backup battery (contacts for positive terminals) Battery connector (X100) for main battery SIM card connector (X101) Clocking, powering, charging and reset issues of CCONT and CHAPS are covered in separate chapters . Backup battery is connected to CCONT's VBACK input and it is charged from CHAPS' VBACK supply. Backup battery's positive contacts are made so that issue 1 06/01
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VBACK from CHAPS is connected to CCONT only when the battery is installed to the connector X102. Backup battery is located on top of RF shield A501 and grounded through the shield. 2.0V reset device (D100) disconnects backup battery if it's voltage drops too much. This prevents deep discharging which would permanently harm the backup battery. 3.0V VMMC supply voltage for MultiMediaCard is generated with linear regulator (N103) from filtered battery voltage (VB). Regulator is controlled with the MMC_PWR signal from MADLinda MPUGenIO5. Accessory power output (VACC) through the system connector's DCE_DTR line is generated with 3.0 volts linear regulator (N104) from filtered battery voltage (VB). Regulator's feed back resistor are internally disconnected from the output pin when the regulator is not enabled, so output will not affect DCE_DTR line's normal signal usage. VACC regulator is controlled with VACC_CTRL signal from MADLinda's MPUGenOut1. .
Use of CCONT ADC channels
Following table describes the analogue signals measured with CCONT's A/D converter.
Table 11. PIN no. A1 B1 D2 A3 D5 B3 C4 A2 CCONT PIN NAME RSSI ICHAR VBAT VCHAR VCXOTEMP BSI BTEMP EAD BSI BTEMP HEADDET VB_CCONT V_IN CONNECTED SIGNAL Not used Charger current measured through a 0.22W resistor X101 Main battery voltage Charger voltage (through voltage division) Not used Main battery size indicator Main battery temperature External accessory detect HEADDET
ADC in CCONT
MEASURES ADC input range
0.1V .. Vref 0.1V .. VBAT+0.4V 0.1V .. VBAT 0.1V .. Vref 0.1V .. Vref 0.1V .. Vref 0.1V .. Vref 0.1V .. Vref
The type of the connected main battery is identified from the BSI line's voltage level. This voltage is formed by the system HW's pullup resistor (100kW) and battery back's pulldown resistor. Level is read with CCONT's BSI A/D input. The BSI contact on the battery connector is also used to detect when the battery is being removed to be able to shut down the operations of the SIM card before the power is lost. The BSI contact is shorter than the supply power contacts so this contact breaks first when the battery pack is removed, giving some time for the shutdown operations. The temperature of the main battery is read from the BTEMP line's voltage level. This voltage is formed by the system HW's pullup resistor (100kW) and battery pack's NTC resistor. Level is read with CCONT's BTEMP A/D input.
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AUDIO_RFI block
The function of the AUDIO_RFI block is to interface between the digital world of the System Hardware and the analogue world of the audio and RF stages. Main components are: COBBA_GJP (N200) Hands free audio amplifier (N201) FET (V200) for amplifier shut down control V202 for mic lines' EMI filtering/ESD protection COBBA_GJP is a combined AUDIO and RFcodec for DCT3 generation phones with serial RF TxIQ & RxIQ data lines and serial control interface.
RFI
COBBA_GJP handles the following RFI functions: IF receiving with I/Q separation and A/D conversion (RxI, RxQ) I and Qtransmit and D/A conversion (TxI, TxQ) transmit power control (TXC) D/A conversion Automatic frequency control (AFC) D/A conversion Digital communication between COBBA_GJP and MADLinda is handled by MADLinda's SerialMFI block which controls both serial RF TxIQ and RxIQ data transfer and COBBA's control interface.
Audio
RAE3 includes both normal phone audio and personal handsfree (PHF) audio functionality. Handsfree mode is implemented by speaker and normal mode by earpiece. Speaker and earpiece are not located on the BL8 module. Signals for speaker and earpiece are passed through the UI connector. Only one high sensitivity microphone will be used for both modes. On the BL8 module there are contacts pads (P200, P201) where microphone is connected with spring contacts. Analogue to digital conversion (ADC) of RAE-3's microphone signals and digital to analogue conversion (DAC) of received audio signals (for speakers) are done in COBBA_GJP. Input and output signal source selection and gain control is performed inside the COBBA_GJP according to control messages from MADLinda. Audio tones are generated and encoded by MADLinda and transmitted to COBBA_GJP for decoding. PCM coded digital audio data is moved between MADLinda's DSP and COBBA_GJP through the PCM bus. The audio functions in COBBA_GJP are controlled through the serial control interface from MADLinda's SerialMFI block. DTMF and keypad tones are routed to earpiece, while ringer, wav and handsfree audios are routed to handsfree speaker. External audio signals, XMIC and XEAR, come from system connector. XMIC is connected to COBBA_GJP's MIC1N and MIC3N inputs through DC blocking capacitors. Reference for XMIC is SGND. XEAR is connected to COBBA_GJP's HF output through DC blocking capacitors. Reference for XEAR is GND. issue 1 06/01
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Audio amplifier IC (N201) is used to amplify the HF output signal of COBBA_GJP for the personal hands free speaker. Audio amplifier shut down mode is controlled with MADLinda's MPUGenOut0 line. Because HF amplifier is powered from battery voltage, controlling of shut down is done through pulldown fet (V200). HeadDet and HookDet interrupting inputs in MADLinda are used to detect different audio accessories. EAD A/D input in CCONT is used to detect the removal of accessory during call. Figure 10 describes the audio connections in system HW.
Audio accessories Headset Carkit Loopset System connector XEAR SGND XMIC GND
COBBA_GJP
HF HFCM MIC1N MIC3N MIC1P MIC3P AUXOUT EARP EARN MBIAS MIC2N MIC2P
UI connector
Earpiece
MADLinda
HookDet HeadDet MPUGenOut 0 DSP PCM SerMFI (control of COBBA)
DSP PCM COBBA[x] Audio Amp. HFSpeaker
CCONT
EAD
Figure 10. Audio connections in BL8
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Introduction to RF of BL8
Maximum ratings
Table 12. Maximum ratings of BL8 RF block Parameter Max battery voltage (VBATT), idle mode Max battery voltage during call, highest power level Regulated supply voltages (VXO, VSYN_1, VSYN_2, VTX, VRX) PLL charge pump supply voltage (VCP) Voltage reference (VREF_2) Voltage reference (RXREF) Operating temperature range (Transceiver ambient) 4.2 V 4.2 V 2.8 +/ 3% V 4.8 +/ 0.2 V 1.5 +/ 1.5% V 1.2 +/ 0.05 V 10...+55 °C Rating
RF frequency plan
925960 MHz
HAGAR
Isignal Qsignal
RX
18051880 MHz
f f/2
26 MHz
VCTCXO
f f/2 VCO PLL
3420 3840 MHz
f f/2
17101785 MHz
f f/2
880915 MHz
Isignal Qsignal
TX
Figure 11.
RF Frequency plan
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DC characteristics
Regulators
Transceiver includes a multi function power management IC (CCONT), which contains among other functions also 7 pcs of 2.8 V regulators. All regulators can be controlled individually with 2.8 V logic directly or through control register. The re