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Data Sheet
gmFC1
DAT-0005-D
November 1998
Genesis Microchip Inc.
200 Town Centre Blvd, Suite 400, Markham, ON Canada L3R 8G5 Tel: (905) 470-2742 Fax: (905) 470-9022 2071 Landings Drive, Mountain View, CA, USA 94043 Tel: (650) 428-4277 Fax (650) 428-4288 www.genesis-video.com / [email protected]
gmFC1 Data Sheet DAT-0005-D
Document DAT-0005 DAT-0005 DAT-0005 DAT-0005
Revision A B C D
Incorporated Errata / Details
First Release Minor update for CD-ROM MSD-0025-A details major changes 1. 64MB memory device interface as in MSD0038 2. Electrical Specifications finalized 3. Errata E04-0005, E05-0005 incorporated 4. I/O pads incorporate pull-down resistors as in MSD-0028 5. Various corrections and clarifications 6. Order Code changed to BR1C 7. Extended Temp. range part available
Release Date Nov. 1997 Dec. 1997 March 1998 Nov. 1998
Copyright 1998, Genesis Microchip Inc. All Rights Reserved
Genesis Microchip Inc. reserves the right to change or modify the information contained herein without notice. It is the customer' responsibility to ensure he/she has the most recent revision of s the document. Genesis Microchip Inc. makes no warranty for the use of its products and bears no responsibility for any errors or omissions which may appear in this document.
CONTENTS
1. 2. 3.
OVERVIEW...................................................................................................................................1 FEATURES AND APPLICATIONS .............................................................................................3 GENERAL OPERATION .............................................................................................................5 3.1 TYPICAL SYSTEMS ........................................................................................................................6
4.
PINOUT .........................................................................................................................................7 4.1 4.2
GMFC1 GMFC1
PINOUT- CHIP DIAGRAM ...................................................................................................7 PINOUT- PIN LIST .............................................................................................................8
5.
FUNCTIONAL DESCRIPTION .................................................................................................15 5.1 POWER ON RESET .......................................................................................................................15 5.2 DATA I NPUT ...............................................................................................................................15 5.2.1 RGB Graphics Input Modes..............................................................................................16 5.2.2 YUV Video Input Modes ...................................................................................................17 5.2.3 Input Active Window Control............................................................................................17 5.2.4 Input Synchronization.......................................................................................................18 5.2.5 Freeze Frame ...................................................................................................................18 5.3 GRAPHICS (RGB) INPUT PORT SIGNALS .......................................................................................18 5.4 VIDEO (YUV) INPUT PORT SIGNALS ............................................................................................24 5.5 GRAPHICS / VIDEO COMMON PORT SIGNALS ................................................................................25 5.6 DATA OUTPUT ............................................................................................................................27 5.6.1 Output Formats ................................................................................................................27 5.6.2 Output Interface Overview ...............................................................................................28 5.6.3 Output Active Size ............................................................................................................29 5.6.4 Output Synchronization ....................................................................................................30 5.6.5 Reverse Scanning .............................................................................................................31 5.6.6 Bypass Mode ....................................................................................................................31 5.6.7 Frame Lock Mode ............................................................................................................32 5.6.8 Output Signals..................................................................................................................32 5.7 FRAME STORE REQUIREMENTS ....................................................................................................34 5.7.1 Interface Overview ...........................................................................................................34 5.7.2 Constraints on I/O Data Rates..........................................................................................35 5.7.3 Frame Store Clock Frequency and Various Data Formats................................................36 5.7.4 SDRAM Power On............................................................................................................36 5.7.5 Clearing SDRAM .............................................................................................................36 5.7.6 SDRAM Power Down .......................................................................................................36 5.7.7 Supported SDRAM Devices ..............................................................................................37 5.7.8 Frame Store Signals .........................................................................................................38 5.8 HOST I NTERFACE REQUIREMENTS................................................................................................39 5.8.1 Interface Overview ...........................................................................................................39 5.8.2 Updating Register Contents..............................................................................................39 5.9 SPI HOST I NTERFACE PROTOCOL REQUIREMENTS ........................................................................40 5.9.1 SPI Interface Control Signals ...........................................................................................40 5.9.2 3-Wire Configuration .......................................................................................................42 5.9.3 4-Wire Configuration .......................................................................................................42 5.9.4 SPI Host Interface State Description ................................................................................43 5.9.5 Host Interface Protocol ....................................................................................................44
5.9.6 5.9.7 6.
Typical Usage Scenarios ..................................................................................................51 Host Interface Registers ...................................................................................................53
ELECTRICAL SPECIFICATIONS ............................................................................................64 6.1 PRELIMINARY DC CHARACTERISTICS ..........................................................................................65 6.2 PRELIMINARY AC CHARACTERISTICS ..........................................................................................67 6.2.1 Input Port Timing.............................................................................................................67 6.2.2 Output Port Timing ..........................................................................................................67 6.2.3 Frame Store Interface Timing...........................................................................................67 6.2.4 Host Interface Timing.......................................................................................................67 6.3 PRELIMINARY I NPUT SETUP AND HOLD TIMES ..............................................................................68 6.3.1 YUV Video Input Interface................................................................................................69 6.3.2 RGB Graphics Input Interface..........................................................................................69 6.3.3 Frame Store Interface ......................................................................................................70 6.3.4 Output (gmZ1/2/3) Interface .............................................................................................70 6.3.5 Host Interface ..................................................................................................................70 6.4 PRELIMINARY OUTPUT PROPAGATION DELAYS ............................................................................71 6.4.1 RGB Graphics Input Interface..........................................................................................72 6.4.2 Frame Store Interface ......................................................................................................72 6.4.3 Output (gmZ1/2/3) Interface .............................................................................................73 6.4.4 Host Interface ..................................................................................................................73
7. 8. 9.
ORDERING INFORMATION ....................................................................................................74 MECHANICAL SPECIFICATIONS ..........................................................................................75 INTERFACING THE GMZ1 AND GMFC1 ..............................................................................76
LIST OF TABLES
TABLE 1: GMFC1 PINOUT DESCRIPTION ......................................................................................................8 TABLE 2: GRAPHICS I NPUT MODES ...........................................................................................................16 TABLE 3: CORRESPONDING I NPUT/OUTPUT SIGNALS IN BYPASS MODE .......................................................31 TABLE 4: FRAME STORE CLOCK REQUIREMENTS .......................................................................................36 TABLE 5: HOST INTERFACE REGISTERS ..................................................................................................54 TABLE 6: ABSOLUTE MAXIMUM RATINGS .................................................................................................64 TABLE 7: DC CHARACTERISTICS ..............................................................................................................65 TABLE 8: OUTPUT DRIVE CAPABILITY / INPUT TOLERANCE ........................................................................66 TABLE 9: YUV INPUT I NTERFACE SETUP/HOLD TIMES ..............................................................................69 TABLE 10: RGB INPUT I NTERFACE SETUP/HOLD TIMES .............................................................................69 TABLE 11: FRAME STORE I NTERFACE SETUP/HOLD TIMES .........................................................................70 TABLE 12: OUTPUT I NTERFACE SETUP/HOLD TIMES ..................................................................................70 TABLE 13: HOST I NTERFACE SETUP/HOLD TIMES ......................................................................................70 TABLE 14: RGB INPUT I NTERFACE DATA PROPAGATION TIMES .................................................................72 TABLE 15: FRAME STORE I NTERFACE DATA PROPAGATION TIMES ..............................................................72 TABLE 16: OUTPUT (GMZ1/2/3) INTERFACE DATA PROPAGATION TIMES ....................................................73 TABLE 17: HOST I NTERFACE DATA PROPAGATION TIMES ...........................................................................73
LIST OF FIGURES
FIGURE 1. GMFC1 - OVERLAPPING CIRCULAR BUFFERS ...............................................................................1 FIGURE 2: GMFC1 FUNCTIONAL BLOCK DIAGRAM .......................................................................................2 FIGURE 3. FRAME RATE CONVERSION PROCESS ...........................................................................................5 FIGURE 4: TYPICAL GMFC1 IMPLEMENTATION ............................................................................................6 FIGURE 5: GMFC1 PINOUT..........................................................................................................................7 FIGURE 6. GMFC1 INPUT MULTIPLEXER ....................................................................................................16 FIGURE 7: XGA VERTICAL I NTERLACE MODE FIELD DETECTION ...............................................................17 FIGURE 8: I NPUT DATA SAMPLING WINDOW ..............................................................................................18 FIGURE 9: GRAPHICS I NPUT DATA HANDSHAKING......................................................................................19 FIGURE 10: GRAPHICS HORIZONTAL SYNC. INPUTS ....................................................................................20 FIGURE 11. CLAMP SIGNAL ....................................................................................................................24 FIGURE 12. VIDEO I NPUT DATA HANDSHAKING .........................................................................................25 FIGURE 13: VERTICAL DE-I NTERLACING ...................................................................................................27 FIGURE 14: HORIZONTAL DE-I NTERLACING ...............................................................................................27 FIGURE 15: OUTPUT TIMING (TO GMZ1/2/3)..............................................................................................28 FIGURE 16: GMFC1 - GMZ1/2/3 INTERFACE .............................................................................................29 FIGURE 17: OUTPUT SUB-REGION OF CAPTURED I NPUT I MAGE ...................................................................30 FIGURE 18. FRAME STORE I NTERFACE TO SDRAM....................................................................................34 FIGURE 19: 4M X 16-BIT FRAME STORE I NTERFACE ...................................................................................37 FIGURE 20: SCLKPOL AND MSBFIRST CONFIGURATION ........................................................................41 FIGURE 21: HOST I NTERFACE OPERATING STATES .....................................................................................43 FIGURE 22: HOST I NTERFACE PROTOCOL...................................................................................................44 FIGURE 23: HOST I NTERFACE START CYCLE (FOLLOWED BY A DDRESS).....................................................45 FIGURE 24: HOST I NTERFACE A DDRESS TRANSFER ....................................................................................47 FIGURE 25: HOST I NTERFACE A DDRESS READ BACK (ARB) TRANSFER ......................................................48 FIGURE 26: HOST I NTERFACE WRITE DATA TRANSFER...............................................................................49 FIGURE 27: HOST I NTERFACE READ DATA TRANSFER ................................................................................50 FIGURE 28: HOST I NTERFACE STOP CONDITION ........................................................................................50 FIGURE 29 CLOCK TIMING MEASUREMENT ................................................................................................67 FIGURE 30: INPUT SETUP AND HOLD TIME MEASUREMENT .........................................................................68 FIGURE 31: OUTPUT PROPAGATION DELAY MEASUREMENT .......................................................................71 FIGURE 32: R1 - 208 PIN PLASTIC QUAD FLAT PACK (PQFP) .....................................................................75
gmFC1 Data Sheet
1. Overview
The Genesis Microchip gmFC1 functions as a graphics and video frame buffer controller capable of performing frame rate conversion by replicating or dropping incoming data as necessary to maintain a set output frame rate. Frame rate conversion is required in applications where it is necessary to manage high input data rates or accommodate varying video and graphics input frame rates when using display devices operating at a fixed frame rate. Schematically, the gmFC1 may be thought of as a control device for two circular buffers; the input buffer being write-only, and the output buffer read-only. (See Figure 1 below.) Incoming data is continuously written to the input buffer loop as it arrives. Output data is continuously read from the output buffer loop as required. If the buffers do not overlap, double buffering of data is enabled and frame tear is prevented. Although it is best to prevent frame tear whenever possible, frame tear may not be objectionable in graphics and video applications containing little motion between adjacent frames. As a rule, unless there are noticeable visual differences in successive frames, frame tear is essentially invisible. In the case of motion video, frame tear artifacts may be perceptible along areas of motion. While double buffering, the location of buffers is managed so the output consists of recently acquired input data, and the input does not overwrite output data as it is being displayed. Thus, entire frames may be dropped or replicated at the output, and an individual output frame will consist of data from only a single input frame.
Frame Store Memory
Input Data Input Controller Output Controller
Output Data
Figure 1. gmFC1 - Overlapping Circular Buffers
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gmFC1 Data Sheet
Figure 2 below illustrates the gmFC1 internal functional blocks and external interfaces. The data input interface is divided into separate RGB (graphics) and a YUV (video) input ports, further described in the following sections.
Frame Store Memory
Frame Store Interface
YUV Data Input FIFO RGB Data Output FIFO RGB/YUV Data Output
Input Controller Input Control Signals
Host Interface
Output Controller Output Control Signals
Host Interface
Figure 2: gmFC1 Functional Block Diagram
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gmFC1 Data Sheet
2. Features and Applications
Features · · · · · · · · · · · · · · · 24-bit single pixel wide I/O interfaces Independent RGB and YUV input ports Supports non-interlaced and vertical / horizontal interlaced formats Simplifies input format detection Enables constant output frame rate with variable input rates Drops or replicates input data to maintain output frame rate Seamless interface to the Genesis gmZ1/Z2/Z3 zoom scaler Seamless interface to three external frame store 1M x 16-bit SDRAMs Eliminates frame tear when double buffering enabled Pads or truncate input lines to a programmed output image size Seamless interface to common RGB ADCs Allows 1:1 windowing of lower resolution inputs on high resolution displays 500Mbytes/sec I/O bandwidth 3.3 Volt operation, 5 Volt tolerant I/O 208 pin PQFP package
Input Format · Single pixel wide input interface (selectable from independent 24-bit RGB and 16-bit YUV ports) · Programmable to accept either sequential or interlaced pixels · Input window cropping · Flags Input Timing Errors - lines are padded to correct size · Supports input formats up to 1024 x 768 at 85 Hz (95 MHz pixel clock) (dependent on output format - maximum total I/O bandwidth limit of ~ 500 MBytes/s)
Output Format · Single pixel wide output interface · Supports output formats up to 1024 x 768 at 85 Hz (dependent on input format - maximum total I/O bandwidth limit of ~ 500 MBytes/s) · 24-bit RGB or 16-bit YUV - dependent on input data format · Frame Rate Conversion - Output faster than input - Output slower than input - Disabled: frame rate locked to input
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gmFC1 Data Sheet
Host Interface · gmZ1/Z2/Z3 compatible three or four wire serial host interface port
Frame Store Interface · 48-bit wide path to external frame store (3 x16 SDRAM devices) · 32-bit wide path to external frame store for YUV-only applications (2x16 SDRAM) · Three 1M x 16-bit devices = 500 Mbytes/sec I/O data rate - 85 Hz XGA in, 60 Hz XGA out. [ (85Hz XGA + 60Hz XGA) x 3 bytes/pixel ] · Compatible 1M x 16-bit, 100MHz memory devices include:
IBM Hitachi NEC Toshiba TI Samsung IBM0316169 HM216165 uPD4516161 TC59S1616AFT TMS626162 KM416S1020B
· Any 4M x 16-bit (64 Mbit) device conforming to SDRAM standards may also interface to the gmFC1. Compatible 4M x 16-bit SDRAM devices include:
Toshiba Mitsubishi Samsung TC59S6416BFT-10 MB611641642A-100FN KM416S4030BT-GB
Applications · Accommodates BIOS and various Windows frame rates during Windows boot up sequence: BIOS Screen - 720x400 text mode, 70 Hz Windows 95 Boot Up Screen Graphics - 640x480 16-color mode, 60 Hz Windows Environment - User selectable, VGA, SVGA, XGA, etc. · Manage high input data rates by reducing frame rates · Manage various input frame rates to support fixed frame rate O/P such as LCD panels, ex: XGA, PAL, RGB, VESA proposed 85 Hz Standards, older DOS screens @ 70 and 85 Hz, MAC standard formats · Games preferring low resolutions · Special effects using frame buffer, ex: cropped zooms, freeze frame, 1:1 windowing · Simplified FRC designs · System cost reduction in applications ordinarily requiring expensive variable refresh LCD panels
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gmFC1 Data Sheet
3. General Operation
The gmFC1 is designed to simplify frame rate conversion of both graphics and digital video (YUV) data, allowing a variety of input formats to be interfaced to a single format display device. Frame rates may be reduced or increased to accommodate the output display. Figure 3 below shows the frame rate reduction and frame replication process, where each horizontal segment represents an entire two dimensional frame. In this example, double buffering is enabled and no frame tearing occurs.
Input data Output data
i0
i1
i2
i3
i4
i5
i6
i7
i8
i0
i1
i2
i3
i5
i6
i7
Frame Rate Reduction (frame ( i4 ) is dropped)
Input data Output data
i0
i1
i2
i3
i4
i5
i6
i7
i8
i-1
i-1
i0
i1
i2
i2
i3
i4
i5
i5
i6
Frame Rate Increase (frames ( i-1, i2, i5 ) are replicated)
Figure 3. Frame Rate Conversion Process
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gmFC1 Data Sheet
3.1 Typical Systems
In a typical system, the gmFC1 is seamlessly interfaced to an SDRAM based frame store, input ADC, and the Genesis gmZ1/Z2/Z3 for output to an LCD display panel (see Figure 4 below). The gmFC1 provides data as required by the gmZ1/Z2/Z3 to sustain the programmed display timing. The gmZ1/Z2/Z3 operates in Free Run Mode, with all required display timing programmed into its display register set. (Frame Lock mode is also possible, although it is recommended only for applications where frame dropping/duplication is not desired.) A shared microcontroller oversees all frame rate conversion, image scaling operations and input format detection through a compatible three or four wire serial host interface.
SDRAM Frame Store Video Video Decoder gmZ1 gmZ2 gmZ3 LVDS / Digital RGB Out
RGB Capture Analog RGB
gmFC1
Microcontroller
Figure 4: Typical gmFC1 Implementation
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gmFC1 Data Sheet
4. Pinout
4.1 gmFC1 Pinout- Chip Diagram
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
VDD INVADC CLAMP fsD0 fsD1 fsD2 fsD3 fsD4 GND fsD5 VDD fsD6 fsD7 fsD8 fsD9 fsD10 fsD11 GND fsD12 VDD fsD13 fsD14 fsD15 fsD16 fsD17 GND VDD fsD18 fsD19 fsD20 fsD21 fsD22 fsD23 GND fsD24 VDD fsD25 fsD26 fsD27 fsD28 fsD29 fsD30 GND fsD31 VDD fsD32 fsD33 fsD34 fsD35 fsD36 fsD37 VDD
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VDD OutCLK /OutSTALL InBLUE7 InBLUE6 InBLUE5 InBLUE4 InBLUE3 InBLUE2 InBLUE1 InBLUE0 OutGREEN7 +5V OutGREEN6 OutGREEN5 OutGREEN4 GND OutGREEN3 VDD OutGREEN2 OutGREEN1 OutGREEN0 OutBLUE7 OutBLUE6 OutBLUE5 GND VDD OutBLUE4 OutBLUE3 OutBLUE2 OutBLUE1 OutBLUE0 OutRED0 GND OutRED1 VDD OutRED2 OutRED3 OutRED4 OutRED5 OutRED6 VDD OutRED7 GND SCLK /SCS /RESET SDI SDO /IRQ fsRefCLK VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
GND InUV0 InUV1 InUV2 InUV3 InUV4 InUV5 GND InUV6 VDD InUV7 InY0 InY1 InY2 InY3 InY4 InY5 InY6 InY7 InVVS InODD InVHS InVCREF InVCLK +5V GND VDD InGVS InRawGHS InGCLK InGCREF InGHS InRED7 InRED6 InRED5 InRED4 InRED3 InRED2 InRED1 InRED0 InGREEN7 InGREEN6 GND InGREEN5 VDD InGREEN4 InGREEN3 InGREEN2 InGREEN1 InGREEN0 RefOutCLK GND
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
gmFC1
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
GND fsD38 fsD39 fsD40 fsD41 fsD42 fsD43 fsD44 fsD45 GND GND VDD VDD fsD46 fsD47 fsDQM1 /FSWE fsDQM0 /FSCAS fsCLK GND /FSRAS fsCKE /FSCS fsA11 GND VDD fsA9 fsA10 fsA8 fsA0 GND fsA7 VDD fsA1 fsA6 fsA2 fsA5 fsA3 GND GND VDD VDD fsA4 /FRAMERESET /LREQ DATAREQ OutODD OutHS OutVS /OUTDFSYNC GND
Figure 5: gmFC1 Pinout
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gmFC1 Data Sheet 4.2 gmFC1 Pinout- Pin List
Table 1 below lists each gmFC1 pin, and provides a concise description of each signal. A detailed signal description may be found on the page listed in the Page column. Table 1: gmFC1 Pinout Description
Pin # 4 5 6 7 8 9 10 11 50 Input Interface Signal Name InBlue7 InBlue6 InBlue5 InBlue4 InBlue3 InBlue2 InBlue1 InBlue0 INDATAACTIVE / IRQ I/O I I I I I I I I
(pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down)
O
Page 23 23 23 23 23 23 23 23 25
Brief Description Input RGB BLUE data MSB Input RGB BLUE data Input RGB BLUE data Input RGB BLUE data Input RGB BLUE data Input RGB BLUE data Input RGB BLUE data Input RGB BLUE data LSB Input Data Active The INDATAACTIVE output signal indicates when the gmFC1 is expecting valid data based on the host programmed active data region registers. Interrupt Request The IRQ interrupt pin of the host interface is physically shared with INDATAACTIVE. The IRQ_OUT_EN bit in the IRQMASK register controls the pin function. The CLAMP output is a pulse with a programmable width and location with respect to InGHS. Can be used to indicate the point for DC restoration in analog RGB signals. The CLAMP pin is shared with: MSBFIRST, Host I/F Mode Select Input. Selects serial data (SDI/SDO) bit ordering. If = ` , the 1' MSB is shifted first. The value is latched on the rising (negating) edge of RESET. Invert ADC sampling clock. (Output) INVADC is used in horizontal interlace mode to request the ADC to invert its sample clock. It will toggle every graphics frame when in this mode. The INVADC pin is shared with: SCLKPOL, Serial Clock Mode Select. (Input) The value is latched on the rising (negating) edge of RESET. This selects the active edge of the host interface shift clock, SCLK. If 0, SDI is sampled on the SCLK rising edge and SDO is shifted out on the SCLK falling edge. Otherwise, SDI is sampled on the SCLK falling edge and
154
CLAMP / MSBFIRST
When RESET = 1, pin 154 = CLAMP When RESET = 0, pin 154 = MSBFIRST
O/I
23
155
INVADC / SCLKPOL
When RESET = 1, pin 155 = INVADC When RESET = 0, pin 155 = SCLKPOL
O/I
23
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gmFC1 Data Sheet
158 159 160 161 162 163 165 167 168 169 170 171 172 173 174 175 176 177 178 179 180 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 200 202 203 204 205 206 InUV0 InUV1 InUV2 InUV3 InUV4 InUV5 InUV6 InUV7 InY0 InY1 InY2 InY3 InY4 InY5 InY6 InY7 InVVS InODD InVHS InVCRef InVClk InGVS InRawGHS InGClk InGCRef InGHS InRed7 InRed6 InRed5 InRed4 InRed3 InRed2 InRed1 InRed0 InGreen7 InGreen6 InGreen5 InGreen4 InGreen3 InGreen2 InGreen1 InGreen0 Note: I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
(pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down)
I
(pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down) (pull-down)
25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 26 25 24 24 23 20 18 19 19 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23
SDO shifted out on the rising edge. UV Video Data Input LSB UV Video Data Input UV Video Data Input UV Video Data Input UV Video Data Input UV Video Data Input UV Video Data Input UV Video Data Input MSB Y Video Data Input LSB Y Video Data Input Y Video Data Input Y Video Data Input Y Video Data Input Y Video Data Input Y Video Data Input Y Video Data Input MSB YUV Port Vertical Sync Input ODD field indicator in interlaced mode YUV Port Horizontal Sync Input InVCLK YUV clock qualifier YUV Port Clock RGB Port Vertical Sync Input Raw Horizontal Sync source input from ADC RGB Port Clock InGCLK RGB clock qualifier RGB Port Horizontal Sync Input Input RGB RED data MSB Input RGB RED data Input RGB RED data Input RGB RED data Input RGB RED data Input RGB RED data Input RGB RED data Input RGB RED data LSB Input RGB GREEN data MSB Input RGB GREEN data Input RGB GREEN data Input RGB GREEN data Input RGB GREEN data Input RGB GREEN data Input RGB GREEN data Input RGB GREEN data LSB Indicates that these gmFC1 inputs are provided with internal pull-down resistors typically valued at 91Kohm.
I (pull-down):
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gmFC1 Data Sheet
Pin # 2 3 12 14 15 16 18 20 21 22 23 24 25 28 29 30 31 32 33 35 37 38 39 40 41 43 54 55 56 57 58
Output Interface Signal Name OutClk OUTSTALL OutGreen7 OutGreen6 OutGreen5 OutGreen4 OutGreen3 OutGreen2 OutGreen1 OutGreen0 OutBlue7 OutBlue6 OutBlue5 OutBlue4 OutBlue3 OutBlue2 OutBlue1 OutBlue0 OutRed0 OutRed1 OutRed2 OutRed3 OutRed4 OutRed5 OutRed6 OutRed7 OUTDFSYNC OutVS OutHS OutODD DATAREQ
I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O I
Page 32 33 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 33 33 33 33
59 60 207
LREQ FRAMERESET RefOutCLK
I I I
33 32 32
Description Clock driving gmZ1/2/3. Based on RefOutCLK. Stall control to gmZ1 / gmZ2 / gmZ3 Output RGB GREEN data MSB Output RGB GREEN data Output RGB GREEN data Output RGB GREEN data Output RGB GREEN data Output RGB GREEN data Output RGB GREEN data Output RGB GREEN data LSB Output RGB BLUE data MSB / Output UV MSB Output RGB BLUE data / Output UV Output RGB BLUE data / Output UV Output RGB BLUE data / Output UV Output RGB BLUE data / Output UV Output RGB BLUE data / Output UV Output RGB BLUE data / Output UV Output RGB BLUE data LSB / Output UV LSB Output RGB RED data LSB / Output Y LSB Output RGB RED data / Output Y Output RGB RED data / Output Y Output RGB RED data / Output Y Output RGB RED data / Output Y Output RGB RED data / Output Y Output RGB RED data / Output Y Output RGB RED data MSB / Output Y MSB Forces gmZ1/2/3 frame re-synchronization Output Vertical Sync Output Horizontal Sync Indicates interlaced output field is ODD Data Request - the gmFC1 will slave to requests for data at the DATAREQ pin when the OP_HANDSH register bit = 0, providing data three clock cycles after DATAREQ is asserted. Line Request Input - accepts gmZ1/2/3 VCLREQ Forces start of new output frame Clock reference for output interface
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gmFC1 Data Sheet
Pin # 1, 19, VDD 27, 36, 42, 52, 62, 63, 71, 78, 92, 93, 105, 112, 121, 130, 137, 146, 156, 166, 183, 201 13, 181 +5V 17, 26, Gnd 34, 44, 53, 64, 65, 73, 79, 84, 94, 95, 104, 114, 123, 131, 139, 148, 157, 164, 182, 199, 208
Power Signal Name
I/O
Page 3.3VDC
Description
+5VDC * Ground
* +5VDC supplies may be wired to 3.3VDC if no 5V tolerance on inputs is required
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gmFC1 Data Sheet
Pin # 45 46 47 48 49 50
Host Interface Signal Name SCLK SCS RESET SDI SDO IRQ / INDATAACTIVE
I/O I I I I O O
Page 40 40 40 41 41 41
Description Host Interface Serial Clock Serial Chip Select - Host Interface Enable Reset input to initialize device Host Interface Serial Data Input Host Interface Serial Data Output Interrupt Request The IRQ interrupt pin of the host interface is physically shared with INDATAACTIVE. The IRQ_OUT_EN bit in the IRQMASK register controls the pin function. Input Data Active The INDATAACTIVE output signal indicates when the gmFC1 is expecting valid data based on the host programmed active data region registers. MSBFIRST - Host I/F Mode Select Input. Selects serial data (SDI/SDO) bit ordering. If = ` , the MSB is shifted first. The value is latched 1' on the rising (negating) edge of RESET. The MSBFIRST pin is shared with CLAMP. The CLAMP output is a pulse with a programmable width and location with respect to InGHS. Can be used to indicate the point for DC restoration in analog RGB signals. SCLKPOL - Serial Clock Mode Select. (Input) The value is latched on the rising (negating) edge of RESET. This selects the active edge of the host interface shift clock, SCLK. If 0, SDI is sampled on the SCLK rising edge and SDO is shifted out on the SCLK falling edge. Otherwise, SDI is sampled on the SCLK falling edge and SDO shifted out on the rising edge. SCLKPOL is shared with INVADC. INVADC - Invert ADC sampling clock. (Output) Used in horizontal interlace mode to request the ADC to invert its sample clock. It will toggle every InGVS when in this mode.
154
MSBFIRST / CLAMP
When RESET = 1, pin 154 = CLAMP When RESET = 0, pin 154 = MSBFIRST
I/O
40
155
SCLKPOL / INVADC
When RESET = 1, pin 155 = INVADC When RESET = 0, pin 155 = SCLKPOL
I/O
40
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gmFC1 Data Sheet
Pin # 74 70 68 66 61 67 69 72 75 77 76 80 153 152 151 150 149 147 145 144 143 142 141 140 138 136 135 134 133 132 129 128 127 126 125 124 122 120 119 118 117 116 115 113
Frame Store Interface Signal Name fsA0 fsA1 fsA2 fsA3 fsA4 fsA5 fsA6 fsA7 fsA8 fsA9 fsA10 fsA11 fsD0 fsD1 fsD2 fsD3 fsD4 fsD5 fsD6 fsD7 fsD8 fsD9 fsD10 fsD11 fsD12 fsD13 fsD14 fsD15 fsD16 fsD17 fsD18 fsD19 fsD20 fsD21 fsD22 fsD23 fsD24 fsD25 fsD26 fsD27 fsD28 fsD29 fsD30 fsD31
I/O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Page 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38
Description Frame Store Address Line Frame Store Address Line Frame Store Address Line Frame Store Address Line Frame Store Address Line Frame Store Address Line Frame Store Address Line Frame Store Address Line Frame Store Address Line Frame Store Address Line Frame Store Address Line Frame Store Address Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line (BLUE / UV data) (BLUE / UV data) (BLUE / UV data) (BLUE / UV data) (BLUE / UV data) (BLUE / UV data) (BLUE / UV data) (BLUE / UV data) (GREEN data) (GREEN data) (GREEN data) (GREEN data) (GREEN data) (GREEN data) (GREEN data) (GREEN data) (RED / Y data) (RED / Y data) (RED / Y data) (RED / Y data) (RED / Y data) (RED / Y data) (RED / Y data) (RED / Y data) (BLUE / UV data) (BLUE / UV data) (BLUE / UV data) (BLUE / UV data) (BLUE / UV data) (BLUE / UV data) (BLUE / UV data) (BLUE / UV data)
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gmFC1 Data Sheet
111 110 109 108 107 106 103 102 101 100 99 98 97 96 91 90 86 82 85 81 87 fsD32 fsD33 fsD34 fsD35 fsD36 fsD37 fsD38 fsD39 fsD40 fsD41 fsD42 fsD43 fsD44 fsD45 fsD46 fsD47 FSCAS fsCKE fsCLK FSCS fsDQM0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 38 Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line Frame Store Data Line (GREEN data) (GREEN data) (GREEN data) (GREEN data) (GREEN data) (GREEN data) (GREEN data) (GREEN data ) (RED / Y data) (RED / Y data) (RED / Y data) (RED / Y data) (RED / Y data) (RED / Y data) (RED / Y data) (RED / Y data)
89
fsDQM1
O
38
83 51 88
FSRAS fsRefCLK FSWE
O I O
38 38 38
Frame Store Column Address Strobe Frame Store Clock Enable Frame Store Clock - based on fsRefCLK Frame Store Chip Select SDRAM Data Mask. FsDQM0 and fsDQM1 (pin 89) are functionally identical but split to reduce loading. Each SDRAM device has an upper and lower DQM. SDRAM Data Mask. FsDQM0 (pin 87) and fsDQM1 are functionally identical but split to reduce loading. Each SDRAM device has an upper and lower DQM. Frame Store Row Address Strobe Frame Store Interface Clock Oscillator Input Frame Store Write Enable
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gmFC1 Data Sheet
5. Functional Description
5.1 Power On Reset
A hard reset is required after power-up to ensure proper operation of all gmFC1 functional blocks and guarantee gmFC1 register contents. A hard reset may be performed by asserting RESET for a minimum of 250ns with a stable frame store clock (fsRefCLK) applied to the gmFC1. All host writable register contents default to ` upon a hard reset, 0' except the SOFT_RESET bit 00 and RESERVED bit 08 in the HOSTCTRL register. See Table 5 for details. After a hard reset, all input clocks must be running and stable before gmFC1 registers may be accessed. A SOFT_RESET affects all gmFC1 functional blocks except the Host Interface registers, effectively disabling the input, output and frame store interfaces. All Host Interface registers may be loaded in any order while SOFT_RESET =1. To complete the initialization procedure, IN_FORC_UPDATE and OUT_FORC_UPDATE are set to ` , 1' and the SOFT_RESET bit is cleared to ` . 0' The gmFC1 frame store SDRAM is unavailable for 200us after a hard or soft reset. The gmFC1 will automatically perform an SDRAM power-on sequence following the negating edge of a RESET to ensure reliable SDRAM access. The SDRAM power-on sequence will also be performed during a host initiated SOFT_RESET. Note that the SDRAM is not cleared on a hard or soft reset. This will result in the first output frame after power up being read as random display data if the output is enabled before the input is enabled.
5.2 Data Input
The gmFC1 provides two separate data input ports: a 24-bit RGB graphics data port, and a 16-bit YUV video data port. Each port provides a complete control interface. The active data source is selected through the IPCTRL host programmable register IP_RGB_nYUV. In this way, the gmFC1 acts as a data stream multiplexer. All Input Port signals except INVADC, InGHS, and CLAMP are provided with internal pull-down resistors.
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gmFC1 Data Sheet
InGCLK InGCREF InGVS InGHS InRED [7:0] InGREEN [7:0] InBLUE [7:0] InDataActive(1) InVCLK InVCREF InVVS InVHS InODD(2) InY [7:0] InUV [7:0]
Graphics Port
ENABLE
Internal data and control path
Video Port
IP_RGB_nYUV
ENABLE
(1)InDataActive signal available through IRQ pin (2)InODD is also available to the Graphics Port
Figure 6. gmFC1 Input Multiplexer 5.2.1 RGB Graphics Input Modes Data input to the gmFC1 RGB graphics port may be interpreted in one of three ways Progressive Scan, Vertical Interlace, and Horizontal Interlace. The appropriate mode is selected through the IP_VINTLC_EN and IP_HINTLC_EN register bits, as in Table 2 below. Note that Horizontal and Vertical Interlace modes may not be enabled simultaneously. Table 2: Graphics Input Modes Mode Progressive Scan Horizontal Interlace Vertical Interlace Not Allowed IP_VINTLC_EN 0 0 1 1 IP_HINTLC_EN 0 1 0 1
In Progressive Scan mode, the input data represents spatially contiguous sample points of the input image. Vertical interlacing is a common technique in video systems to reduce bandwidth. It is less common in computer graphics. In Vertical Interlace mode, data is input to the gmFC1 in fields containing only odd or even lines of data. Successive alternating odd and
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gmFC1 Data Sheet
even fields make up the entire image. The gmFC1 automatically determines the state of the current XGA Vertical Interlace Mode field from the timing of InGHS relative to InGVS (see Figure 7 below). If this feature is disabled by setting the IPCTRL register bit EXTGODD_EN=1, the InODD signal is used to determine the current field state.
Interlaced XGA - ODD field detected InGVS InGHS
# clocks x - 1024
Interlaced XGA - EVEN field detected -
or
< 256
>= 256
where x= the total number of clocks per line of incoming data
Figure 7: XGA Vertical Interlace Mode Field Detection
In Horizontal Interlace mode, data is input to the gmFC1 in fields containing only odd or only even pixels. The fields alternate between sets of odd and even pixels to make up the entire image. This technique may be useful when sampling computer graphics data. The sample rate, and therefore required bandwidth, is halved. See the INVADC description on page 23 for further details. 5.2.2 YUV Video Input Modes The gmFC1 supports Progressive Scan and Vertically Interlaced formats as described in Section 5.2.1 above, although automatic determination of odd/even fields is not available in YUV Modes. Horizontal Interlaced YUV data is not supported. 5.2.3 Input Active Window Control The gmFC1 contains host programmable registers which define the input active data region with respect to input vertical and horizontal sync pulses. Figure 8 below illustrates how these registers control the active input sampling region.
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gmFC1 Data Sheet
InHS INDATAACTIVE InVS
IPV_ACTIV_START (ODD/EVEN) Active Data Sampling Region
IPV_ACTV_LNGTH
IPH_ACTIV_START IPH_ACTIV_WIDTH
Figure 8: Input Data Sampling Window 5.2.4 Input Synchronization Modifications to the input data window registers do not take effect immediately. After all desired changes have been made, the external system may set the input update enable bit, IN_UPDATE_EN. This causes the input parameters to become active only at the next input vertical sync. This mechanism ensures input frames are not captured with partially updated parameters. It is also possible for the host to force an immediate update by setting the IN_FORC_UPDATE bit within the HOSTCTRL register, causing modified parameters to become active without waiting for an input VSYNC. See Section 5.8.2 for further details. 5.2.5 Freeze Frame The input data capture circuitry may be disabled through the host programmed register INP_EN. When disabled, the gmFC1 continues to display previously captured data, providing freeze frame capability.
5.3 Graphics (RGB) Input Port Signals
The Graphics (RGB) Input Port signals are active when the gmFC1 is operating with the RGB port selected, by setting the HOSTCTRL register bit IP_RGB_nYUV=1. Otherwise, this port is ignored. All Graphics Input Port signals except INVADC, InGHS, and CLAMP are provided with internal pull-down resistors. InGCLK InGCLK provides the timing reference for the RGB port signals. The active edge is programmable through the IPCLK_INV register.
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gmFC1 Data Sheet
InGCREF InGCREF further qualifies InGCLK. InGCREF must be active during an active InGCLK edge to validate the InGCLK cycle, i.e., InGCREF can be considered an InGCLK clock enable. In most designs, the CREF signals may be hard-wired to either VCC or GND to validate all clocks. The active polarity of InGCREF is programmable through the IPCTRL register control bit IPCREF_INV. If the CREF qualifier signals InVCREF / InGCREF are left floating or not connected, the gmFC1 may operate incorrectly. It is recommended that any unused input clock reference signals (InVCREF or InGCREF) be tied either HIGH or LOW. When the clock reference is tied HIGH, program the gmFC1 IPCTRL register bit IPCREF_INV (Register 05, bit 1) = 1. When the clock reference is tied LOW, program IPCREF_INV = 0.
InGClk InGCRef InRGB
captured InRGB data [control signals shown active high]
Figure 9: Graphics Input Data Handshaking InGHS InGHS is the RGB port horizontal sync input. The active edge of InGHS is sampled synchronously to InGCLK, and resets clock counters used in determining the active data region. The active polarity of InGHS is programmable through the IPCTRL register control bit IPHS_INV. Some amount of skew, approximately 18 InGCLK periods, is accepted between InGHS and InGVS (i.e., if there are less than 18 InGCLK periods between InGVS and InGHS, the internal line counter is not incremented). This is required since the HSYNC is generally synchronized to the reconstructed pixel clock InGCLK, and may have a different path delay from the VSYNC.
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gmFC1 Data Sheet
InRawGHS InRawGHS is the ` raw' horizontal sync input for the RGB port. This signal is used as the source for horizontal sync timing measurements when the RGB port is selected. By bypassing the PLL, input mode detection is possible prior to PLL programming.
Horz. Sync Input PLL InGHS gmFC1
InCLK
InRawGHS
Figure 10: Graphics Horizontal Sync. Inputs Measurement example: To measure the active pulse width of the Horizontal Sync Input at InRawGHS:
1. Write register MEAS_VS_nHS = 0 (measure Horizontal Sync) 2. Write register PERIOD_nACTIVE = 0 (measure active ` high' width, not entire period) 3. Read MEAS_VALID, wait until MEAS_VALID =1 (a valid measurement is complete) 4. Read the measured result from MEAS_RESULTL register
Note: The selected measurement is performed continuously once steps 1) and 2) are complete. MEAS_VALID will remain set to ` while the selected signal is being 1' continuously re-measured. The most recent measurement is always available in the MEAS_RESULTL register. The MEAS_VALID bit will only be cleared to ` if the 0' MEAS_VS_nHS or PERIOD_nACTIVE bits are re-written. The following measurements are possible:
Measured Parameter H-Sync Period H-Sync ` High' Period V-Sync Period V-Sync ` High' Period Units fsCLK / 2 fsCLK / 2 H-Sync pulses H-Sync pulses gmFC1 HOSTCTRL Register settings MEAS_VS_nHS PERIOD_nACTIVE 0 1 0 0 1 1 1 0
To determine the period of an input Horizontal or Vertical Sync signal, the gmFC1 register MEAS_RESULTL (Registers 1A) is read by the system microcontroller. The measured value in this register is updated continuously. Erroneous values may be
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gmFC1 Data Sheet
interpreted from the MEAS_RESULTL register if a read-back is requested during a register update. For example, if the measured sync value is nominally 0x200, but occasionally varies to 0x1FF, the read-back value may be incorrectly read as 0x2FF if an update occurs between the time the "2" and the next most significant bit are shifted out of the gmFC1. This problem is particularly pronounced during HS measurement read-back, as HS updates occur more frequently than VS updates. To avoid the possibility of incorrect read-back, it is possible to take advantage of the longer window between VS measurement updates to perform an HS measurement value read-back. The recommended sequence is given below, with the corrective steps highlighted in a box. 1. Program the gmFC1 to measure HS:
WRITE (Register 03 bit 09) MEAS_VS_nHS = 0 WRITE (Register 03 bit 10) PERIOD_nACTIVE = 0) (measure HS) (measure full period =1, measure hi time
2. Poll (check) gmFC1 to ensure at least one valid measurement has been completed:
READ (Register 01 bit 10) MEAS_VALID = 1
3. Poll gmFC1 for a VS pulse (MEAS_RESULT registers are continuously updated) :
READ (Register 01 bit 08) IPRGB_VS = 1 [ or READ (Register 01 bit 07) IPYUV_VS = 1 for YUV inputs ]
4. Program gmFC1 to measure VS period (this guarantees no more updates to the MEAS_RESULT registers until the next VS, giving the microcontroller one frame period to read the correct HS measurement results) :
WRITE WRITE (Register 03 bit 09) MEAS_VS_nHS = 1 (Register 03 bit 10) PERIOD_nACTIVE =1 (measure VS) (measure full VS period)
5. Read the ` captured' HS measurement value (this must be completed prior to next VS) :
READ (Register 1A) MEAS_RESULTL
Similarly, when reading VS measurement values from MEAS_RESULTL register, wait for a VS pulse and read the registers immediately to guarantee the read will not occur during an update.
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gmFC1 Data Sheet
` psuedo-code for the HS measurement and read procedure is given below: C'
/* HS Period Measurement Procedure * MeasureHSPeriod: * { * SelectMeasurement (HS_Period); * WaitForValidMeasurement; * WaitForVSYNC; * SelectMeasurement (VS_Period); * ReadMeasurementResult; * } */ uint MeasHSPeriod () { int hostctrl; int status; uint result; hostctrl = gmFC1_Rd (fc1_HOSTCTRL); /* read contents of HOSTCTRL register to the hostctrl variable */ hostctrl = hostctrl & (~MEAS_VS_nHS); /* select HS */ hostctrl = hostctrl | (PERIOD_nACTIVE); /* period */ gmFC1_Wr (fc1_HOSTCTRL, hostctrl); /* write new value of HOSTCTRL register */ while (1) { /* * wait for measurement to be valid */ status = gmFC1_Rd (fc1_STATUS); if ((status & MEAS_VALID) != 0) { break; /* measurement is valid and ready */ } } /* * once the horizontal measurement is valid, wait for VSYNC rising edge, * switch to VSYNC measurement, and immediately read the result. */ status = gmFC1_Rd (fc1_STATUS); /* read STATUS register to clear VSYNC bit */ while (1) { /* * wait for VSYNC */ status = gmFC1_Rd (fc1_STATUS); if ((status & IPRGB_VS) != 0) { break; /* VSYNC detected */ } } /* switch to VSYNC measurement - prevents updates to the previously measured HSYNC value for 1 frame */ hostctrl = hostctrl | (MEAS_VS_nHS); /* select VS */ gmFC1_Wr (fc1_HOSTCTRL, hostctrl); /* read correct value of HSYNC measurement */ result = (gmFC1_Rd (fc1_MEAS_RESULTL) & 0xFFF); return (result); }
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gmFC1 Data Sheet
InGVS InGVS is the RGB port vertical sync input. The active edge of InGVS is sampled synchronously to InGCLK, and resets line counters used in determining the active data region. The active polarity of InGVS is programmable through the IPCTRL register control bit IPVS_INV. InRed [7:0], InGreen [7:0], InBlue [7:0] These are the 24-bit RGB data inputs. INVADC INVADC is an output signal provided by the gmFC1 to support horizontal interlacing. If the data source is an analog to digital converter (ADC), INVADC may be used to invert the ADC sampling clock at the end of every field, effectively shifting the sample points by half a clock period. When the IPCTRL register bit IP_HINTLC_EN =1, the gmFC1 will change the state of INVADC after the final pixel of a field is captured (before InGVS). INVADC may be tied directly to the ADC clock driver (e.g. the INV pin of the Philips TDA8752 ADC). Inverting the ADC sampling clock using INVADC may cause the sampling clock to momentarily glitch. The gmFC1 InGClk is internally gated to filter these glitches within approximately 16 fsCLK periods prior to and after a toggled INVADC. CLAMP CLAMP is a gmFC1 output signal provided to aid the input ADC in DC restoration of the source analog RGB signal. The CLAMP pulse has programmable start and end points referenced from the input InGHS signal. The active polarity is also programmable from the host register bit IP_CLAMP_INV. CLAMP is programmed to frame a short period within the horizontal back porch. The DC restoration circuit in the ADC then modifies the DC offset value to bring the clamping level to the required voltage. The CLAMP pin is shared with the mode select pin MSBFIRST.
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gmFC1 Data Sheet
InGClk (with InGCRef) InGHS CLAMP
IP_CLAMP_START IP_CLAMP_END
Figure 11. CLAMP Signal
5.4 Video (YUV) Input Port Signals
The Video (YUV) Data Input Port signals are active when the gmFC1 is operating with this port selected by the host programmed register bit IP_RGB_nYUV. Otherwise, this port is ignored. All Video Input Port signals are provided with internal pull-down resistors. InVCLK InVCLK provides the timing reference for the YUV port signals. The active edge is programmable though the IPCTRL register control bit IPCLK_INV. InVCREF InVCREF further qualifies InVCLK. InVCREF must be asserted during an active InVCLK edge to validate the InVCLK cycle, i.e., InVCREF can be considered an InVCLK clock enable. In most designs, the CREF signals may be hard-wired to either VCC or GND to validate all clocks. The asserting (active) polarity of InVCREF is programmable through the IPCTRL register control bit IPCREF_INV. If the CREF qualifier signals InVCREF / InGCREF are left floating or not connected, the gmFC1 may operate incorrectly. It is recommended that any unused input clock reference signals (InVCREF or InGCREF) be tied either HIGH or LOW. When the clock reference is tied HIGH, program the gmFC1 IPCTRL register bit IPCREF_INV (Register 05, bit 1) = 1. When the clock reference is tied LOW, program IPCREF_INV = 0.
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gmFC1 Data Sheet
InVClk (i) InVCRef (i)
InY/UV (i)
captured InY/UV data [control signals shown active high]
Figure 12. Video Input Data Handshaking InVHS InVHS is the YUV port horizontal sync input. The active edge of InVHS resets clock counters used in determining the active data region. The active polarity of InVHS is programmable through the IPCTRL register control bit IPHS_INV. InVVS InVVS is the YUV port vertical sync input. The active edge of InVVS resets line counters used in determining the active data region. The active polarity of InVVS is programmable through the IPCTRL register control bit IPVS_INV. InY [7:0], InUV [7:0] These are the 16-bit YUV data inputs.
5.5 Graphics / Video Common Port Signals
INDATAACTIVE INDATAACTIVE is common to both graphics and video ports and is driven based on the active clock input. The INDATAACTIVE output signal indicates when the gmFC1 is expecting valid data based on the host programmed active data region registers.
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gmFC1 Data Sheet
INDATAACTIVE is not predictive. The INDATAACTIVE pin is physically shared with the IRQ interrupt pin of the host interface; the IRQ_OUT_EN bit in the IRQMASK register controls the function. Note that the output is open-drain, and requires a pull-up resistor. InODD InODD is the odd/even field indicator when operating in vertical interlace mode. It must be valid prior to the first line of active input data. When asserted, InODD indicates the current input field contains odd lines. The active polarity of InODD is programmable through the IPCTRL register control bit IPODD_INV. The gmFC1 has the capability to auto-detect odd/even fields in certain graphics interlaced modes. The gmFC1 distinguishes fields by monitoring InGVS and InGHS. If this feature is disabled by setting the IPCTRL register bit EXTGODD_EN=1, the InODD signal is used to determine the current field state. InODD is provided with an internal pull-down resistor.
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gmFC1 Data Sheet
5.6 Data Output
5.6.1 Output Formats The gmFC1 will produce a Progressive Scan output format if the input format is Progressive Scan. If the input format is vertically interlaced, the gmFC1 may output vertically interlaced data, or it may be configured to perform static mesh de-interlacing and output a Progressive Scan format. Static mesh de-interlacing weaves together alternating odd and even lines of data as illustrated in Figure 13 below.
NTSC Odd Input Field gmFC1 Proscan Output
NTSC Even Input Field
Figure 13: Vertical De-Interlacing If the input format is horizontally interlaced, the gmFC1 will weave together alternating odd and even pixel data fields, and produce a Progressive Scan output. Horizontal interlacing allows an ADC to effectively sample a signal at twice the maximum ADC clock rate (e.g., a 160 MHz signal may be sampled using a 80 MHz ADC, assuming the full power bandwidth of the ADC is >= 160 MHz). See Figure 14 below.
Horz. Interlaced Even Field Input Line Horz. Interlaced Odd Field Input Line
gmFC1 Meshed Proscan Output Line
Figure 14: Horizontal De-Interlacing
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gmFC1 Data Sheet
5.6.2 Output Interface Overview The operational parameters of both the gmFC1 and the Genesis gmZ1/Z2/Z3 zoom scaler are closely related. In Free Run Mode, the gmFC1 depends on the gmZ1/Z2/Z3 to set the output frame rate, and to request data required to maintain the data rate. (In Frame Sync Mode, the gmFC1 input source sets the frame rate.) Output interface handshaking is shown in Figure 15 below. See Figure 16 for interface details.
gmFC1 FRAMERESET (i)
OutVS (o)
gmZ1 / Z2 / Z3 OVSYNC (o)
VGBVS (i)
LREQ (i)
OutHS (o)
VCLREQ (o)
VGBHS (i)
VCBLNK (o)
OutRGB (o) VGBRGB (i)
Figure 15: Output Timing (to gmZ1/2/3)
The gmFC1 is programmed to provide active output data a specified number of clock cycles (OPH_ACTIV_START) after the gmFC1 asserts OutHS. The gmZ1/Z2/Z3 is programmed to receive active single pixel RGB input data occupying the same active window as the gmFC1 RGB output data. This is achieved by matching the gmFC1 Active Output Window parameters to the gmZ1/Z2/Z3 Active Input Window parameters. When the gmZ1/Z2/Z3 has completed displaying an image, the gmFC1 must be signaled to queue up data for the next frame. This is accomplished by tying a gmZ1/Z2/Z3 displayside VSYNC signal (ex: OVSYNC) to the gmFC1 FRAMERESET input. This resets the gmFC1' output circuitry, and produces a pulse on the OutVS signal. In response to this s the gmZ1/Z2/Z3 asserts VCLREQ, indicating internal line storage is available. VCLREQ is tied to the gmFC1' LREQ pin. s
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gmFC1 Data Sheet
RefOutCLK OutClk VGBCLK VGBCREF VGBVS VGBHS VCODD
OUTSTALL
OutVS OutHS
X-tal Oscillator
OutODD
LREQ
OutRGB
VCLREQ 24
VGBRGB OVSYNC
FRAMERESET OUTDFSYNC
DFSYNC gmZ1/2/3
gmFC1
Figure 16: gmFC1 - gmZ1/2/3 Interface In applications where the gmFC1 must provide data on demand from a source other than the gmZ1 / gmZ2 / gmZ3, the DATAREQ signal may be used. By programming the MISC register control bit OP_HANDSH = 0, the gmFC1 will slave to requests for data at the DATAREQ input pin and provide data three clock cycles after DATAREQ is asserted. In this mode, the latency to data from DATAREQ (three clock cycles) differs from the gmZ1 / gmZ2 / gmZ3' VCBLNK data latency requirement (two clock cycles). Therefore, in s applications where the gmFC1 is interfacing to the gmZ1 / gmZ2 / gmZ3, the gmFC1 control bit OP_HANDSH must be programmed to ` . This enables the gmFC1 to 1' provide data a fixed number of clock cycles after asserting OutHS. The gmZ1/Z2/Z3 must be programmed to expect data at the same point. OUTSTALL is used by the gmFC1 to indicate it does not have the requested data available. Because of internal buffering within the gmZ1 / gmZ2 / gmZ3, momentary data transfer stalls are acceptable. If prolonged data transfer stalls occur (ex: because the I/O data rates through the gmFC1 exceed its frame store capabilities) the gmZ1/Z2/Z3 will underflow.
5.6.3 Output Active Size The gmFC1 may be programmed to output a region of data smaller than the active sampled input region. The parameters of the output region are set through host programmed registers. This feature allows zooming of a captured freeze frame input image. The location of the output region within the input data is restricted to multiples of two pixels. To position the output image an offset Y_OFFSET lines from the captured input start, and an offset X_OFFSET pixels from the captured image left edge: Progressive Scan Images: OP_MEM_START= IPH_MEM_WIDTH * Y_OFFSET + int (X_OFFSET / 2) Vertical Interlaced Images: November 1998 29 DAT-0005-D
gmFC1 Data Sheet
OP_MEM_START= IPH_MEM_WIDTH * int (Y_OFFSET/2) + int (X_OFFSET / 2) Horizontal Interlaced Images: OP_MEM_START= IPH_MEM_WIDTH * Y_OFFSET + int (X_OFFSET / 4) where the function int (x) returns the nearest integer not greater than (x).
IPH_MEM_WIDTH
Y_OFFSET
Sampled Input Region
OP_MEM_START OPV_LENGTH Output Image Region IPV_ACTIV_LNGTH
OPH_MEM_WIDTH X_OFFSET
Figure 17: Output Sub-Region of Captured Input Image 5.6.4 Output Synchronization Because of the close relationship between gmFC1 output and gmZ1/Z2/Z3 input sections, care must be taken to ensure they remain synchronized. This is particularly true in applications where the operational parameters are modified dynamically. The gmFC1 host programmed registers associated with the output interface incorporate an Active and a Pending Register Set. When modified by the host, only the Pending Register Set is affected. The Active Register Set is the set actually used by the output circuitry. The Pending Register contents are copied to the Active Set only after the OUT_UPDATE_EN register bit is set, and the FRAMERESET signal becomes asserted. This is at a point where no active data is being transferred to the gmZ1 / gmZ2 / gmZ3. The gmZ1/Z2/Z3 has a similar scheme, with Pending and Active Register sets. For the gmZ1 / gmZ2 / gmZ3, the transfer to the Active Register Set also occurs at approximately this same point. For a more detailed description of gmFC1 - gmZ1/Z2/Z3 interfacing, see the Genesis Application Note MSD-0016, ` Interfacing the Genesis gmFC1 and gmZ1, gmZ2 and gmZ3' included with this data sheet. , When parameters are modified dynamically (i.e., while active data is flowing), the host microcontroller is responsible to ensure gmFC1 and gmZ1/Z2/Z3 Active Register sets are synchronized. This may be achieved by enabling the Pending to Active set transfers for both the gmFC1 and the gmZ1/Z2/Z3 within a short period after the FRAMERESET has
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DAT-0005-D
gmFC1 Data Sheet
occurred. This ensures the transfer for one device will not happen while the host is enabling the transfer for the other device. 5.6.5 Reverse Scanning The image may be scanned out of memory from bottom to top, effectively flipping the output image. To enable this feature, OP_MEM_START must be set to the bottom of the image, using one of the following basic formulas: For Progressive Scan and Horizontal Interlaced images: OP_MEM_START = (IPV_ACTIV_LNGTH-1)* IPH_MEM_WIDTH For Vertical Interlaced images: OP_MEM_START = int((IPV_ACTIV_LNGTH-1)/2) * IPH_MEM_WIDTH Note that the above formulas assume that no image cropping is taking place. With the REV_SCAN bit enabled, IPH_MEM_WIDTH is subtracted from OP_MEM_START when addressing the SDRAM. Therefore, the image is read out from bottom to top. Note that correct Double Buffering is not guaranteed when reverse scanning, and frame tear may result.
5.6.6 Bypass Mode To aid in system development, the gmFC1 provides a Bypass Mode. In Bypass Mode, the selected input port signals are routed unmodified to the corresponding output signals, although there is a two-clock pipeline delay. The programmable polarity functions are still available. The following table illustrates the mapping of gmFC1 input to output signals. Table 3: Corresponding Input/Output Signals in Bypass Mode gmFC1 Input Signal
In[GV]CLK In[GV]CRef InODD In[GV]VS In[GV]HS InRED [7:0] / InY [7:0] InGREEN [7:0] InBLUE [7:0] / InUV [7:0]
Corresponding Output Signal
OutCLK OUTSTALL OutODD OutVS OutHS OutRED [7:0] / OutY [7:0] OutGREEN [7:0] OutBLUE [7:0] / OutUV [7:0]
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DAT-0005-D
gmFC1 Data Sheet
5.6.7 Frame Lock Mode In normal operation, the input frame rate is set by the input data source, and the output frame rate is set by the gmZ1 / gmZ2 / gmZ3. In many applications, these rates differ, and frame rate conversion is required. However, there are instances where the input