Text preview for : Yamaha Receiver RX-530 Schematic.pdf part of Yamaha RX-V630 (RDS), RX-V730 (RDS) Schematic Diagram 6.1 Channel Receiver - (5.127Kb) Part 1/3 - pag. 8



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A B C D E F G H I J K L
RX-V530/RX-V530RDS/HTR-5550/HTR-5550RDS/DSP-AX530
SCHEMATIC DIAGRAM (FUNCTION 1/2) # All voltages are measured with a 10M/V DC electric volt meter. RX-V430/RX-V430RDS/HTR-5540/HTR-5540RDS/DSP-AX430
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
1 # Schematic diagram is subject to change without notice. IC302: BD3811K1
Sound Processor
Page 70 F1 Page 69 A6 CD-R L/R 71, 72 73, 74 VCR L/R
to OPERATION (1)


TUNER L/R 77, 78
47k
CD L/R 1, 2 MASTER
47k OUTPUT TREBLE BASS




AUDIO INPUT
VOLUME ±14dB ±14dB BASS
CD-R L/R 79, 80 0 - 100dB GAIN BOOST
47k + 1dB step 0.5 - 18dB 2dB step 2dB step 0, 4, 8, 12dB
V-AUX L/R 9, 10 ­ + 2dB step
47k ­
55 L OUT
VCR L/R 7, 8
6.7 12.0 47k CH2 +
D-TV L/R 5, 6 ­ +
47k
7.4 ­
57 R OUT
DVD L/R 3, 4
12.0 47k
+
7.4 0 5 8 ­ +
0 6 ­ 37 RL OUT
7 0
L 22 +
2 0 R 24
47k ­ +
38 RR OUT




6 CH INPUT
­
47k
RL 14 +
-7.4 47k ­




0
0
0
0
+




0
0
0
0
0
0
0
0
0
0
0 RR 13 ­ 36 C OUT
47k
0
C 15 +
0 0 -7.4 47k
­
SOUND
+
0 0 -6.7 12.1 0 2 W 16 ­ 35 SW OUT
0 0 1 0 47k INPUT ATT




TO DSP
0 3 0, -6, -12, -18dB
0
0 PROCESSOR 0

-12.0
4 L 19
R 17 -1
47k 47k 47k 47k 47k 47k
DIGITAL
CONTROL
0 0
0 0
0 0 21 24 26 25 27 28 46 47 48
0
0 0 Hi Level >2.2V
0 L R RL RR C SW
0 µ-COM Low Level <1.0V




A4
A4
0 0 FROM DSP
0 0
0
L




RX-V530/RX-V530RDS/HTR-5550/HTR-5550RDS/
DSP-AX530/HTR-5540RDS/RX-V430RDS: Page 72
RX-V430/HTR-5540/DSP-AX430: Page 73
0 0
0 0
0 0
0 IC305: MM74HC4053SJX
MAIN L 0 Triple 2-Channel Analog Multiplexer IN/OUT
3 0 0 0 0
0
0 VCC CY CX BY BX AY AX
0 0
0
16 3 5 1 2 13 12
0
0 0
0 0 TO
OUT/IN
5.6 Logic Binary to 1 AX or AY




4.9
4.9
0
0
0
0
0
0
0
0
0
0
0
0
A 11 Level




0
5.6
of 2 Decoders YG
Conversion with INHBIT
0
0
0
0
0




Logic TG
0
B 10 Level OUT/IN
Conversion Binary to 1 BX or BY
of 2 Decoders TB




0
-5.6
0
-5.6 with INHBIT
Logic
C 4 Level
Conversion TC
OUT/IN
Logic Binary to 1 CX or CY
12.0 INH 9 Level of 2 Decoders TG
0 5 8 Conversion with INHBIT
7
0 6 0