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Intel (R) 845E Interactive Client Reference Design
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Revision X2 Last Change : 2002-09-26
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Schematic Page
COVER SHEET BLOCK DIAGRAM BLOCK-POWER MECH-ROUTE NOTES CPU-P4 BUS CPU-P4 POWER CPU-ITP MCH-SYSBUS & CLOCK MCH-AGP & DDR MCH-POWER CLK-ICS950201 DDR-DIMM 0 DDR-DIMM 1 ICH4-SYSBUS & PCI ICH4-LPC & IDE & USB ICH4-POWER GLUE LOGIC SIO0-LPC47M107 SIO1-LPC47N227 CONN-COM1/COM2/LPT CONN-COM3/COM4/KBC AC97-AD1885 LAN-10/100/1000 BUS LAN-10/100/1000 CONN VGA-COUGAR-01 VGA-COUGAR-02 VGA-COUGAR-03 CONN-PCI CONN-01 IDE-FLOPPY USB0-USB1-LAN0 USB2-USB5 SYSTEM CONTROL DDR-POWER POWER
Prefix
A_ AC_ APIC_ AUD_ CK_ EEn_ EN_ F_ FWH_ G_ GND_ GND H_ I2C_ IDE_ INT_ KB_ L_ LANn_ LP_ M_ MIDI_ MS_ P_ SPn_ USB_ V_ ZV_
Netobject
CRITICAL ANALOG TRACES AC97 SIGNAL APIC SIGNAL ANALOG AUDIO SIGNAL CLOCK SIGNAL SERIAL EEPROM LANn ENABLE FOR POWER SOURCES FLOPPY DISK SIGNAL FIRMWARE HUB SIGNAL AGP BUS SIGNAL GND SIGNAL DERIVED GND POWER P4 HOSTBUS SIGNAL I2C BUS SIGNAL IDE SIGNAL INTERRUPT SIGNAL KEYBOARD SIGNAL LPC BUS SIGNAL LAN CONTROLLER n SIGNAL LPT1284 SIGNAL MEMORY BUS SIGNAL MIDI SIGNAL MOUSE SIGNAL PCI BUS SIGNAL SERIAL PORT n SIGNAL USB PORT SIGNAL POWER ZV VIDEO PORT SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Changes from X1 to X2
All BAT54A (0-0031-1261) changed to BAT54 (0-0031-1104) due to wrong polarity R712 changed from 10k to 15k to adjust voltage PU R756 and R757 added @ U38.15 (PG_VDDR) and U38.16 (PG_V1V5) Net on pins U3.54 and U3.55 separated (BSEL[0..1]) due to naming error PU R758 added at CN34.7 (SYS_RESET#) PU R759 added at U39.4 (VIDPWRGD) C717 changed from 4u7 to 1u R607 not populated R571 and R572 not populated (FWH Test Pins) R585 and R586 not populated (for LVDS 18 Bit) R760 and C741 added to U7.50 to generate a V_3V3SB input delay for resume reset R501 and R494 not populated due to PCI config of LAN 82540 U36 FWH symbol changed due to wrong pinout (Pin 23, 24 and 25) R496 changed to 4k7 and set to GND (PD M66EN) R525 and R499 is now populated R530 not populated due to wrong V_2V5LAN voltage U20.G4 is now 51R Pulldown to GND U20.H4 is now 33R Pullup to V_3V3LAN AC97 Fixup (AC_SDIN0 -> Changed to AC_SDIN2 on ICH4) Swap ICH4 Pin N20 and P21 (H_HISTB+ / H_HISTB-) due to wrong info in yellow cover LAN 82540 Fixup (R519 populated with 0R, R517 changed to 2K49 and R513 changed to 330R) R615 changed to 4K32 due to Cougar Bug HW Rev changed to 2 at Glue Logic R373 is now populated with 10M CN12.4 must be isolated cause of shortcut of AUD_MIC_BIAS to GND PU R761-R765 added to VID[0:4] PU R766 added to U23.15, PD R767 added to U23.14 (Panellink strapping options) HD-LED-power connected to V_5V0 instead of V_5V0SB PD R768 added to PS_ON PU R769 added to U3.28 (PGOOD408#) PD R770, R771, R772 added to power enables (default off, if CPLD not configured) PD R773-R776 added to serial port shut down pins Splitted SMI# and PME# signals of SIO0 and SIO1 on ICH4-GPIOs Removed R383, R384, R385 Added D25 to avoid crossvoltages from VGA Monitor Added D26 to avoid crossvoltages LPT Port Alternative population of L7 to L12 with resistors (0R) PME# Signal of Cougar (PinB7) is set to V_3V3 via 0R U29 (LP3965EMP) can be replaced by an 0R_1206 to power 3V3 on Cougar Possibility to PullDown Pin D8(MD24) on Cougar to enable SDRAM CN41 (JUMPER 3x1) added to connect to MPCI Pins (TIP and RING) V_5V0 input at V_DDR supply is now controlled by XILINX CPLD (Pin 25) Delay of PWRGOOD# (LAN 82540EM Pin A9) to enable correct EEPROM detection
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26 27 28 29 30 31 32 33 34 35
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THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLE.
A
General Note: All Parts marked 'XXX1' will not be assembled in V1. All Parts marked 'XXX2' will not be assembled in V2.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. Intel does not warrant or represent that such use will not infringe such rights. THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE OR THE MISUSE OF THIS INFORMATION. * Other names and brands may be claimed as the property of others.
Intel (R) 845E Interactive Client Reference Design
Title Size
A
COVER SHEET
Document Number
C
Date
B444B-W
Sheet
1
Rev
2.00
1 of 35
Friday, September 26, 2003
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Block Diagram
D D
CPU VRM
Pg. 35
CPU
Clocking
ICS950201 CK 408
Pg. 12
Glue Logic
Xilinx * Coolrunner
Pg. 18 - Postcode decoding - Speedstep logic - Powerup sequencing
ITP
Pg. 8
Pentium(R) 4 Processor FCPGA478
Pg. 6, 7
FSB 133MHz x4, 64b (4.3 GB/s)
1280x1024 @ 18Bit
LVDS
Pg. 27 planar
C
max. 2 GB
DDR-DIMM
Cougar 3DR *
DVI/VGA
845E MCH
C
DVI-I
Pg. 27 I/O panel
BGA385 16 MB int. mem.
Pg. 26, 27, 28
AGP 1.5V, 66MHz x4, 32b (1.1 GB/s)
i82845-E BGA593
DDR SDRAM 2.5V, 266MHz, 64b (2.1 GB/s)
DDR VR
Pg. 34
TV-OUT
Pg. 27 I/O panel
Pg. 9, 10, 11
PHY RJ45
Pg. 31 I/O panel PCI, 33MHz, 32b (132 MB/s)
Pg. 13 Pg. 14 Hub Interface 66MHz x4, 8b (266 MB/s)
i82562
Pg. 31
ICH4
i82801 BGA421
LPC 3.3V, 33MHz
B
B
5V PCI-Slot
Pg. 29
miniPCI-Slot
Pg. 29
LAN
i82540 (optional i82551/i82559)
Pg. 24, 25 Pg. 15, 16, 17
SMB
SYSMON
LM87 Pg. 33 FAN PHOTO DIODE
FWH
8 Mbit i82802AC PLCC32 Pg. 33
SIO
LPC47N227
SIO
LPC47M107
RJ45
Pg. 25 I/O panel
ATA66/100
Pg. 20
Pg. 19
USB2.0
AC'97 Pg. 22 SERIAL2 SERIAL0 SERIAL1 FDD PARALLEL K/B MOUSE I/O panel I/O panel planar I/O panel planar planar Pg. 21 Pg. 21 Pg. 30 Pg. 21 Pg. 22 Pg. 22
A
IDE0
Pg. 30 planar
USB
Pg. 31, 32
AC97
AD1885
LINE-IN LINE-OUT HEADPHONE MICRO
I/O panel planar I/O panel I/O panel planar
Pg. 22 SERIAL3 Pg. 20 FIR 3 * planar
IDE1
Pg. 30 planar
A
2 * I/O panel 2 * I/O panel, powered 2 * planar
Pg. 23
CD-ROM
Intel (R) 845E Interactive Client Reference Design
Title Size
BLOCK-DIAGRAM
Document Number
C
Date
5 4 3 2
B444B-W
Sheet
1
Rev
2.00
2 of 35
Friday, September 26, 2003
5
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SLP_S3#
ATX POWER
D
ATX 12V
12V
D
12V
5V 5VSB 3V3
CPU VRM MODULE MIC5284
VCCP VCC_1V2VID
CLK
VCC_CLK
MCH
VTT
C
ISL6225 A LTC1117
VCC_1V5 VCC_1V8 VCC_DDR
C
DIMM ISL6225 A
SLP_S4# VCC_REF SLP_S3# VCC_DDR
B
VCC_TERM
B
ICH4
VCC_5V0SUS
B
LTC1117 LTC1117
VCC_3V3SUS VCC_1V5SUS VCC_1V8S VCC_1V5S VCC_3V3S VCC_5V0S
A
A
COUGAR *
ISL6225
B
V_3V3AGP
Intel (R) 845E Interactive Client Reference Design
Title Size
BLOCK-POWER
Document Number
C
Date
5 4 3 2
B444B-W
Sheet
1
Rev
2.00
3 of 35
Friday, September 26, 2003
5
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1
Mx
Mx
Mx
B1 BOHR4.0
B4 BOHR4.0
B7 BOHR4.0
M29
M10 M7
M1
Mx
Mx
1
2
3
MACADRESS B3 BOHR4.0 B9 BOHR4.0 82802AC M30 BRD1
BIOS IN Firmware-Hub
P4_RETENT M2 M23 SM02/RD M24 SM02/RD M25 SM02/RD M26 SM02/RD
Mx
Mx
MACADRESS XXX1 XXX2
V_CORE V_CORE V_CORE V_CORE V_CORE
B444B
PCB
M31
M E C H
DK1 DK2 DK3 DK4 DK5 DK204060 DK204060 DK204060 DK204060 DK204060 BAT_CR2032 M11 M32
V_CORE V_CORE V_CORE V_CORE V_CORE
M E C H
JMP_2mm54
HS_MCH_PIN_FIN XXX1 XXX2 M15 HS_MCH_LEVER XXX1 XXX2
HS_MCH_INTERFACE XXX1 XXX2 M16
1 2 3 4 5 6 7 8
BGA593A/COOL
M12
4
D
Mx
B2 BOHR4.0
B5 BOHR4.0
B8 BOHR4.0
FWH
B4441000.01
D
M17
DK6 DK7 DK8 DK9 DK10 DK204060 DK204060 DK204060 DK204060 DK204060
HS_MCH_CLIP HS_MCH_PORON XXX1 XXX1 XXX2 XXX2
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
C
C
DK11 DK12 DK13 DK14 DK15 DK204060 DK204060 DK204060 DK204060 DK204060
V_CORE
V_CORE
V_CORE
DK16 DK17 DK18 DK204060 DK204060 DK204060
MARKE1 MARKETOP MARKE2 MARKETOP MARKE3 MARKETOP
MRKF1 MARKFPIT
B
B
TP1
TP2
TP3
TP4
GND
GND
GND
GND
A
A
Intel (R) 845E Interactive Client Reference Design
Title 6..8,11,17,33,35 V_CORE
V_CORE
MECH-ROUTE
Document Number
Size
C
Date
5 4 3 2
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INPUT VOLTAGES V_12V0VRM V_12V0
D
DERIVED VOLTAGES --> V_12V0VRMF V_FAN1 V_FAN1S V_FAN1SF V_FAN2 V_FAN2S V_FAN2SF V_3V3SB V_1V5SB V_KB V_KBF V_DDR V_USB0 V_USB1 V_USB2 V_USB3 V_USB4 V_USB5 V_1V5 V_USB0X V_USB1X V_USB2X V_USB3X V_USB4X V_USB5X V_DDRVTT V_DDRREF V_12USB2 V_12USB2F V_12USB2S V_12USB3 V_12USB3F V_12USB3S V_12VAUD V_AUDOUT V_5VAUD V_BLI V_CORE V_VCCA V_VCCIOPLL
I2C DEVICES DEVICE CLOCK GENERATOR SO-DIMM0 SO-DIMM1 ICH4 SLAVE LAN CONTROLLER LM87 HW MONITOR ADDRESS 1101001x 1010000x 1010001x 1000100x N/A 0101110x BUS SM SM SM SM SM SM BUS BUS BUS LINK LINK BUS
D
V_5V0SB
V_3V3LAN V_3V3LAN0
V_1V5LAN V_2V5LAN
PCI/AGP DEVICES DEV 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 IDSEL AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 DEVICE COUGAR AGP LAN10/100/1000T IRQ A G REQ/GNT AGP 4
V_5V0
C
V_1V5A1 V_1V5A2 V_2V5_LVD
V_HVDD V_ICHPLL V_2V5_LVD1 V_PLLVDD V_2V5_LVD2 V_LVDD1 V_CVDD V_LVDD2 V_VDD1
INTERNAL LAN MINI PCI SLOT STD PCI SLOT RISER SLOT1 RISER SLOT2 RISER SLOT3
N/A E-F A-B-C-D B-C-D-A C-D-A-B D-A-B-C
N/A 3 0 0 1 2
C
V_3V3AGP
V_2V0_2V5 V_2V5_VDD V_VCC1 V_AVCC1 V_PVCC1 V_VREF_SII V_DBL V_5DVI V_PIDE V_SIDE V_FIR V_IR V_3V3 V_1V2VID V_1V8 V_CLK V_5V0CF V_5DVIF V_IOLAN V_GAME V_GAMEF V_AMP V_AMPIN V_AMPINX V_AMPOUT V_5V0REF V_DL_CL V_DL_CLF V_AVDD V_FPVDD V_TVDD V_VPVDD
ICH4 GPIOs V_VDD2 V_VDD3 GPIO GPI6 GPI7 GPI8 GPI12 GPI13 GPIO25 GPIO27 GPIO28 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 DEVICE SUPER I/O 0 SUPER I/O 1 SUPER I/O 0 SUPER I/O 1 CPLD LAN0 KINNERETH MINI PCI CPLD PRIMARY IDE SECONDARY IDE POWERED USB POWERED USB FIRMWARE HUB FIRMWARE HUB PCI RISER PCI RISER AUDIO AMPLIFIER PCI RISER PCI SLOT PCI SLOT SIGNAL NAME SIO0_SMI# SIO1_SMI# SIO0_PME# SIO1_PME# XC_GPIO2 LAN0_ENA MPCI_ACT# XC_GPIO1 IDE_PPDIAG# IDE_SPDIAG# USB_PWR2ENA# USB_PWR3ENA# FWH_WP# FWH_TBL# RISER_ID1 RISER_ID2 AMP_SHDN NOGO P_PRSNT1# P_PRSNT2#
B
B
V_3V3SB V_RTC V_BAT V_RTCBIAS V_-12V0 V_-5V0
POWER STATES
A A
ON IN STATE S5 (SOFT OFF) S3 (SUS. TO RAM) S0 (FULL ON)
5
POWER PLANE V_*SB, V_KB, V_*LAN, V_USB*
Intel (R) 845E Interactive Client Reference Design
V_DDR, V_DDRREF
Title
OTHERS
4 3 2
NOTES
Document Number
Size
C
Date
B444B-W
Sheet
1
Rev
2.00
5 of 35
Friday, September 26, 2003
5
4
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1
H_D[0..63]
H_D[0..63]
9
U1A
9 H_A#[3..31] H_A#[3..31] SPAREPIN SPAREPIN SPAREPIN SPAREPIN H_A#31 H_A#30 H_A#29 H_A#28 H_A#27 H_A#26 H_A#25 H_A#24 H_A#23 H_A#22 H_A#21 H_A#20 H_A#19 H_A#18 H_A#17 H_A#16 H_A#15 H_A#14 H_A#13 H_A#12 H_A#11 H_A#10 H_A#9 H_A#8 H_A#7 H_A#6 H_A#5 H_A#4 H_A#3 H_REQ#4 H_REQ#3 H_REQ#2 H_REQ#1 H_REQ#0 H_ADSTB#1 H_ADSTB#0 H_ADS# SPAREPIN SPAREPIN SPAREPIN IERR# SPAREPIN 9 H_BR0# H_BR0# H_BPRI# H_BNR# H_LOCK# H_HIT# H_HITM# H_DEFER# H_RS#[0..2] H_RS#2 H_RS#1 H_RS#0 SPAREPIN H_TRDY# 62RA 62RA 62RA R6 R7 R8 H_A20MX# H_FERR# H_IGNNEX# H_SMIX# PWRGOOD 62RA 62RA 62RA 62RA 62RA R9 R10 R11 R12 R13 STPCLKY# CPUSLPY# H_INTRX H_NMIX PROCHOT# CK_CPU+ CK_CPUF4 G5 F1 AB2 J6 C6 B6 B2 B5 AB23 Y4 AB26 D1 E5 C3 AF22 AF23 AB1 Y1 W2 V3 U4 T5 W1 R6 V2 T4 U3 P6 U1 T2 R3 P4 P3 R2 T1 N5 N4 N2 M1 N1 M4 M3 L2 M6 L3 K1 L6 K4 K2 H3 J3 J4 K5 J1 R5 L5 G1 V5 AC1 AA3 AC3 V6 H6 D2 G2 G4 F3 E3 E2 A35# A34# A33# A32# A31# A30# A29# A28# A27# A26# A25# A24# A23# A22# A21# A20# A19# A18# A17# A16# A15# A14# A13# A12# A11# A10# A9# A8# A7# A6# A5# A4# A3# REQ4# REQ3# REQ2# REQ1# REQ0# ADSTB1# ADSTB0# ADS# AP1# AP0# BINIT# IERR# MCERR# BR0# BPRI# BNR# LOCK# HIT# HITM# DEFER#
SW478/S1
D63# D62# D61# D60# D59# D58# D57# D56# D55# D54# D53# D52# D51# D50# D49# D48# D47# D46# D45# D44# D43# D42# D41# D40# D39# D38# D37# D36# D35# D34# D33# D32# D31# D30# D29# D28# D27# D26# D25# D24# D23# D22# D21# D20# D19# D18# D17# D16# D15# D14# D13# D12# D11# D10# D9# D8# D7# D6# D5# D4# D3# D2# D1# D0# AA24 AA22 AA25 Y21 Y24 Y23 W25 Y26 W26 V24 V22 U21 V25 U23 U24 U26 T23 T22 T25 T26 R24 R25 P24 R21 N25 N26 M26 N23 M24 P21 N22 M23 H25 K23 J24 L22 M21 H24 G26 L21 D26 F26 E25 F24 F23 G23 E24 H22 D25 J21 D23 C26 H21 G22 B25 C24 C23 B24 D22 C21 A25 A23 B22 B21 H_D63 H_D62 H_D61 H_D60 H_D59 H_D58 H_D57 H_D56 H_D55 H_D54 H_D53 H_D52 H_D51 H_D50 H_D49 H_D48 H_D47 H_D46 H_D45 H_D44 H_D43 H_D42 H_D41 H_D40 H_D39 H_D38 H_D37 H_D36 H_D35 H_D34 H_D33 H_D32 H_D31 H_D30 H_D29 H_D28 H_D27 H_D26 H_D25 H_D24 H_D23 H_D22 H_D21 H_D20 H_D19 H_D18 H_D17 H_D16 H_D15 H_D14 H_D13 H_D12 H_D11 H_D10 H_D9 H_D8 H_D7 H_D6 H_D5 H_D4 H_D3 H_D2 H_D1 H_D0
D
D
9
H_REQ#[0..4]
H_REQ#[0..4]
9
H_ADSTB#[0..1]
H_ADSTB#[0..1]
V_CORE
V_CORE
R2
R3
R4
301RA
62RA
51RA
C
9
H_ADS#
62RA
R5
C
9 H_BPRI# 9 H_BNR# 9 9 9 9 9 H_LOCK# H_HIT# H_HITM# H_DEFER#
H_DBI#[0..3]
H_RS#[0..2]
H_DBI#[0..3]
9
9
H_TRDY#
RS2# RS1# RS0# RSP# TRDY# A20M# FERR# IGNNE# SMI# PWRGOOD STPCLK# CPUSLP# LINT0 LINT1 PROCHOT# BCLK0 BCLK1 THERMTRIP# THERMDC THERMDA
DBI3# DBI2# DBI1# DBI0# DBSY# DRDY# DP3# DP2# DP1# DP0# DSTBN3# DSTBN2# DSTBN1# DSTBN0#
V21 P26 G25 E21 H5 H2 L25 K26 K25 J26 W22 R22 K22 E22
H_DBI#3 H_DBI#2 H_DBI#1 H_DBI#0 H_DBSY# H_DRDY# SPAREPIN SPAREPIN SPAREPIN SPAREPIN H_DSTBN#3 H_DSTBN#2 H_DSTBN#1 H_DSTBN#0 H_DSTBN#[0..3]
15 H_A20M# 15 H_FERR# 15 15 H_IGNNE# 15 H_SMI# PWRGOOD
H_DBSY# H_DRDY#
9 9 9
H_DSTBN#[0..3]
15 STPCLK# 15,18 CPUSLP#
B
H_DSTBP#[0..3]
H_DSTBP#[0..3]
9
B
15 H_INTR 15 H_NMI
V_CORE
V_3V3
12 CK_CPU+ 12 CK_CPU-
DSTBP3# DSTBP2# DSTBP1# DSTBP0# BSEL1 BSEL0 SKTOCC#
W23 P23 J23 F21 AD5 AD6 AF26
H_DSTBP#3 H_DSTBP#2 H_DSTBP#1 H_DSTBP#0 SPAREPIN
R14 4k7A
15 8,9
H_INIT#
H_INIT# H_CPURST#
W5 AB25
INIT# RESET#
BSEL0 SKTOCC#
10,12 18
H_CPURST#
SKTOCC#
C4
B3
A2
V_CORE
THERMDC
THERMDA
R17 62RA
33 33
THERMDA THERMDC THERMTRIP# 16
A
A
7,9,11,15,16,24..27 8,12,15..17,19,20,23,26..29,33,35 4,7,8,11,17,33,35 4,7,8,10..35
SPAREPIN V_3V3 V_CORE GND
SPAREPIN
V_3V3 V_CORE GND
Intel (R) 845E Interactive Client Reference Design
Title Size
CPU BUS
Document Number
C
Date
5 4 3 2
B444B-W
Sheet
1
Rev
2.00
6 of 35
Friday, September 26, 2003
5
4
3
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1
V_CORE
R47
R18 R19 R20 R21 R22 R23
V_CORE
150RA
51RA 51RA 51RA 51RA 51RA 51RA
8
D
BPM#[0..5]
BPM#[0..5]
U1C U1B
BPM#5 BPM#4 BPM#3 BPM#2 BPM#1 BPM#0 AB4 AA5 Y6 AC4 AB5 AC6 AE25 D4 C1 D5 F7 E6 SPAREPIN A22 SPAREPIN A7 SPAREPIN AD2 SPAREPIN AD3 SPAREPIN AE21 SPAREPIN AF3 SPAREPIN AF24 SPAREPIN AF25 SPAREPIN AC26 SPAREPIN AD26 BPM5# BPM4# BPM3# BPM2# BPM1# BPM0# DBR# TCK TDI TDO TMS TRST# RESEVED_0 RESEVED_1 RESEVED_2 RESEVED_3 RESEVED_4 RESEVED_5 RESEVED_6 RESEVED_7 ITP_CLK0 ITP_CLK1 ITPCLKOUT0 ITPCLKOUT1
SW478/S1
VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 P2 P5 P22 P25 R1 R4 R23 R26 T3 T6 T21 T24 U2 U5 U22 U25 V1 V4 V23 V26 W3 W6 W21 W24 Y2 Y5 Y22 Y25 AA1 AA4 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA23 AA26 AB3 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB21 AB24 AC2 AC5 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC22 AC25 AD1 AD4 AD8 AD10 AD12 AD14 AD16 AD18 AD21 AD23 AE7 AE9 AE11 AE13 AE15 AE17 AE19 AE22 AE24 AE26 AF1 AF6 AF8 AF10 AF12 AF14 AF16 AF18 AF20
V_CORE
V_CORE
V_CORE
SW478/S1
VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_59 VCC_57 VCC_58 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_75 VCCSENSE VSSSENSE A8 A10 A12 A14 A16 A18 A20 B7 B9 B11 B13 B15 B17 B19 C8 C10 C12 C14 C16 C18 C20 D7 D9 D11 D13 D15 D17 D19 E8 E10 E12 E14 E16 E18 E20 F9 F11 F13 F15 F17 F19 AA8 AA10 AA12 AA14 AA16 AA18 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AC8 AC10 AC12 AC14 AC16 AC18 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AF5 AF7 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF2 A5 A4
GND
8,18
ITP_DBR# 8 H_TCK
8
8 H_TDI 8 H_TDO 8 H_TMS H_TRST#
V_CORE V_CORE
1KA 1KA
R24 R25
ITP_CKO0 AA20 ITP_CKO1 AB22
C
GND GND
51RA 51RA
R26 R27
COMP0 COMP1
L24 P1
COMP0 COMP1
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
VID4 VID3 VID2 VID1 VID0
V_CORE
AE1 AE2 AE3 AE4 AE5
VID4 VID3 VID2 VID1 VID0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
14x 1206 ker
Place : Northside of P4
ESR max = 3.5mR each
ESL typ = 1.15nH each
C27
GND
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
51RA 51RA 51RA 51RA 51RA 51RA 51RA 51RA 51RA
R28 R29 R30 R31 R32 R33 R34 R35 R37
TSTHI0 TSTHI1 TSTHI2 TSTHI3 TSTHI4 TSTHI5 TSTHI8 TSTHI9 TSTHI10
AD24 AA2 AC21 AC20 AC24 AC23 U6 W4 Y3
TESTHI0 TESTHI1 TESTHI2 TESTHI3 TESTHI4 TESTHI5 TESTHI8 TESTHI9 TESTHI10
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
10x 1206 ker Place : Inside P4 Socket
100nA R36 270RA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
ESR max = 9.28mR each ESL max = 6.4nH each
GND
0RA
R38
GHI#
18
DPSLP# L1 V_VCCAX 4uH7/SB
A6 AD25
GHI#/TESTHI11 DPSLP#/TESTHI12
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V_VCCA
+
AD20
VCCA
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
C39 33u/TA GND_ACPU C56 33u/TA V_VCCIOPLL AE23 VCCIOPLL AD22 VSSA
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
B
V_CORE V_1V2VID
0RA 0RA XXX1 XXX2
R39 R40
C54
10u/CA
18,33
VID[0..4]
VID[0..4]
L2 4uH7/SB
V_1V2VID
AF4 F6 F20 AA6 AA21
VCCVID GTLREF_3 GTLREF_2 GTLREF_1 GTLREF_0
A3 A9 A11 A13 A15 A17 A19 A21 A24 A26 B4 B8 B10 B12 B14 B16 B18 B20 B23 B26 C2 C5 C7 C9 C11 C13 C15 C17 C19 C22 C25 D3 D6 D8 D10 D12 D14 D16 D18 D20 D21 D24 E1 E4 E7 E9 E11 E13 E15 E17 E19 E23 E26 F2 F5 F8 F10 F12 F14 F16 F18 F22 F25 G3 G6 G21 G24 H1 H4 H23 H26 J2 J5 J22 J25 K3 K6 K21 K24 L1 L4 L23 L26 M2 M5 M22 M25 N3 N6 N21 N24
3x Al Electrolytic 3300uF Place : Northside of P4
D
VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90
+ C1
+ C2
+ C3
3300u/EA
3300u/EA
3300u/EA
ESR max = 12mR each ESL max = 5nH each
GND
GND
GND
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
9x Oscon 560uF Place : Northside of P4
+ C4
+ C5
+ C6
+ C7
+ C8
+ C9
+ C10
+ C11
+ C12
680u/PA
680u/PA
680u/PA
680u/PA
680u/PA
680u/PA
680u/PA
680u/PA
680u/PA
ESR max = 9.28mR each ESL max = 6.4nH each Iripple = 4.080 each
GND
GND
GND
GND
GND
GND
GND
GND
GND
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
V_CORE
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C41
C
GND
B
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
10u/CA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
14x 1206 ker
Place : Southside of P4
ESR max = 3.5mR each
ESL typ = 1.15nH each
GND
V_CORE
V_CORE
6x 0603 ker to eliminate 133MHz x N Freqs Place : Between 1206 ker
V_CORE
49R9A C65 10nA
R41
GTLREF R42 100RA C66 1u/CA C67 220pA
GND
C59 47pA
C60 47pA
GND
GND
GND
GND
GND
A
10u/CA
GND
35 35
VSSSENSE VCCSENSE
5
+
A
6,9,11,15,16,24..27
SPAREPIN
SPAREPIN
V_CORE V_1V2VID GND
Intel (R) 845E Interactive Client Reference Design
Title Size
4,6,8,11,17,33,35 V_CORE 35 V_1V2VID 4,8,10..35 GND
CPU POWER
Document Number
C
Date
4 3 2
B444B-W
Sheet
1
Rev
2.00
7 of 35
Friday, September 26, 2003
5
4
3
2
1
D
D
V_CORE
V_3V3
V_3V3
V_CORE
V_CORE
R731 R732 R733 R734 R735 R736
R1
R45
R46
R48
54R9A
C
51RA 51RA 51RA 51RA 51RA 51RA
7
BPM#[0..5]
BPM#[0..5]
R49
C
220RA
220RA
54R9A
BPM#5 BPM#4 BPM#3 BPM#2 BPM#1 BPM#0
13 15 17 19 21 23 6 4
BPM#5 BPM#4 BPM#3 BPM#2 BPM#1 BPM#0 NC2 NC1 VTAP VTT VTT RESET# BCLK+ BCLKSW28/FD XXX1 XXX2
FBO TCK TRST# TDI TDO TMS DBA# DBR# GND GND GND GND GND GND
11 5 3 1 7 2 24 25 22 20 18 16 14 10
39RA
CN1
H_TDOITP
22R6A
R754
H_TCK 7 H_TRST# 7 H_TDI 7 H_TDO 7 H_TMS 7 ITP_DBA# ITP_DBR# 7,18
V_CORE
26 28 27 12 9 8 C738 C739
6,9
H_CPURST# 12 CK_ITP+ 12 CK_ITP-
22R6A
R755
H_CPURSTX#
R52
GND GND
100nA
GND
100nA
GND
B
680RA
GND
27RA
R53
B
A
A
Intel (R) 845E Interactive Client Reference Design
6,12,15..17,19,20,23,26..29,33,35 4,6,7,11,17,33,35 4,7,10..35 V_3V3 V_CORE GND
V_3V3 V_CORE GND
Title Size
CPU-ITP
Document Number
C
Date
5 4 3 2
B444B-W
Sheet
1
Rev
2.00
8 of 35
Friday, September 26, 2003
5
4
3
2
1
H_HISTB+ H_HISTB-
15 15
H_HI[0..10] H_HISTB+ H_HISTB-
H_HI[0..10]
15
D
H_HI10 H_HI9 H_HI8 H_HI7 H_HI6 H_HI5 H_HI4 H_HI3 H_HI2 H_HI1 H_HI0
D
H_D[0..63]
6
H_REQ#[0..4]
H_REQ#[0..4]
H_A#31 H_A#30 H_A#29 H_A#28 H_A#27 H_A#26 H_A#25 H_A#24 H_A#23 H_A#22 H_A#21 H_A#20 H_A#19 H_A#18 H_A#17 H_A#16 H_A#15 H_A#14 H_A#13 H_A#12 H_A#11 H_A#10 H_A#9 H_A#8 H_A#7 H_A#6 H_A#5 H_A#4 H_A#3 H_REQ#4 H_REQ#3 H_REQ#2 H_REQ#1 H_REQ#0 H_RS#2 H_RS#1 H_RS#0
M24 N28 M27 L27 L28 M25 M26 P23 N27 P24 P25
N25 N24
6
H_A#[3..31]
H_A#[3..31] L7 M6 G2 N5 H4 L2 J3 M5 J2 K3 L5 L3 M3 M4 K4 N3 N7 N2 P3 P5 R6 P4 R2 P7 R3 U3 T3 T5 T4 U2 U5 R7 T7 U6 W6 W7 W2 AD15 AH9 AG4 AD5 N6 R5 V3 U7 Y4 W5 Y7 V7 W3 V5 V4 Y5 Y3 P22 J8 K8 J27
H_D[0..63]
6
HA#31 HA#30 HA#29 HA#28 HA#27 HA#26 HA#25 HA#24 HA#23 HA#22 HA#21 HA#20 HA#19 HA#18 HA#17 HA#16 HA#15 HA#14 HA#13 HA#12 HA#11 HA#10 HA#9 HA#8 HA#7 HA#6 HA#5 HA#4 HA#3 HREQ#4 HREQ#3 HREQ#2 HREQ#1 HREQ#0 RS#2 RS#1 RS#0 DBI#3 DBI#2 DBI#1 DBI#0 HADSTB1# HADSTB0# ADS# HTRDY# DEFER# HLOCK# BPRI# BR0# BNR# DBSY# DRDY# HIT# HITM# 66IN BCLK+ BCLKRSTIN# CPURST#
U2A 82845E
C
6
H_RS#[0..2]
H_RS#[0..2]
6
H_DBI#[0..3]
H_DBI#[0..3]
6
H_ADSTB#[0..1]
H_ADSTB#[0..1]
H_DBI#3 H_DBI#2 H_DBI#1 H_DBI#0 H_ADSTB#1 H_ADSTB#0 H_ADS# H_TRDY# H_DEFER# H_LOCK# H_BPRI# H_BR0# H_BNR# H_DBSY# H_DRDY# H_HIT# H_HITM# CK_MCH66 CK_MCH+ CK_MCHP_RST0#
6 6 6
H_ADS#
6
H_TRDY# H_DEFER# H_LOCK#
6 H_BPRI# 6 H_BR0# H_BNR# 6 H_DBSY# 6 H_DRDY# 6 6
B
6
HD#63 HD#62 HD#61 HD#60 HD#59 HD#58 HD#57 HD#56 HD#55 HD#54 HD#53 HD#52 HD#51 HD#50 HD#49 HD#48 HD#47 HD#46 HD#45 HD#44 HD#43 HD#42 HD#41 HD#40 HD#39 HD#38 HD#37 HD#36 HD#35 HD#34 HD#33 HD#32 HD#31 HD#30 HD#29 HD#28 HD#27 HD#26 HD#25 HD#24 HD#23 HD#22 HD#21 HD#20 HD#19 HD#18 HD#17 HD#16 HD#15 HD#14 HD#13 HD#12 HD#11 HD#10 HD#9 HD#8 HD#7 HD#6 HD#5 HD#4 HD#3 HD#2 HD#1 HD#0
AE16 AD17 AH17 AE15 AF16 AC17 AH15 AG17 AG16 AG15 AE14 AG14 AF14 AC14 AH13 AG13 AF12 AE13 AG12 AH11 AG10 AG11 AF10 AE12 AC10 AG9 AD9 AE10 AC9 AE9 AC12 AC11 AH5 AF8 AG6 AG7 AG8 AF4 AH3 AH7 AE5 AG3 AF3 AH2 AF6 AE8 AG2 AG5 AE2 AC8 AC3 AC6 AC7 AD7 AB7 AE3 AA6 AA3 AC5 AB4 AB3 AA5 AB5 AA2
H_D63 H_D62 H_D61 H_D60 H_D59 H_D58 H_D57 H_D56 H_D55 H_D54 H_D53 H_D52 H_D51 H_D50 H_D49 H_D48 H_D47 H_D46 H_D45 H_D44 H_D43 H_D42 H_D41 H_D40 H_D39 H_D38 H_D37 H_D36 H_D35 H_D34 H_D33 H_D32 H_D31 H_D30 H_D29 H_D28 H_D27 H_D26 H_D25 H_D24 H_D23 H_D22 H_D21 H_D20 H_D19 H_D18 H_D17 H_D16 H_D15 H_D14 H_D13 H_D12 H_D11 H_D10 H_D9 H_D8 H_D7 H_D6 H_D5 H_D4 H_D3 H_D2 H_D1 H_D0
HI_STB+ HI_STB-
HI_10 HI_9 HI_8 HI_7 HI_6 HI_5 HI_4 HI_3 HI_2 HI_1 HI_0
C
H_DSTBP#[0..3]
H_DSTBP#[0..3]
6
H_HIT# H_HITM#
H_DSTBN#[0..3] HDSTBP#3 HDSTBP#2 HDSTBP#1 HDSTBP#0 AC16 AD11 AE7 AD3 H_DSTBP#3 H_DSTBP#2 H_DSTBP#1 H_DSTBP#0
H_DSTBN#[0..3]
6
B
12
CK_MCH66
12 CK_MCH+ 12 CK_MCH15,18,33 6,8 P_RST0#
H_CPURST#
H_CPURST# AE17 SPAREPIN H26
HDSTBN#3 HDSTBN#2 HDSTBN#1 HDSTBN#0 SCK5+ SCK4+ SCK3+ SCK2+ SCK1+ SCK0+ SCK5SCK4SCK3SCK2SCK1SCK0-
AC15 AE11 AE6 AD4
H_DSTBN#3 H_DSTBN#2 H_DSTBN#1 H_DSTBN#0
TESTIN#
H5 E24 G15 G6 J24 E14 CK_SCK+2 CK_SCK+0 CK_SCK+1 CK_SCK+5 CK_SCK+3 CK_SCK+4
CK_SCK-2 CK_SCK-0 CK_SCK-1 CK_SCK-5 CK_SCK-3 CK_SCK-4
F5 G24 G14 G7 G25 F15
CK_SCK-[0..5]
CK_SCK-[0..5]
13,14
CK_SCK+[0..5]
CK_SCK+[0..5]
13,14
A
A
Intel (R) 845E Interactive Client Reference Design
6,7,11,15,16,24..27 4,7,8,10..35 SPAREPIN GND SPAREPIN
GND
Title Size
MCH-SYSBUS & CLOCK
Document Number
C
Date
5 4 3 2
B444B-W
Sheet
1
Rev
2.00
9 of 35
Friday, September 26, 2003
5
4
3
2
1
26
G_AD[0..31]
G_AD[0..31]
M_D[0..63]
U2B
G_AD31 G_AD30 G_AD29 G_AD28 G_AD27 G_AD26 G_AD25 G_AD24 G_AD23 G_AD22 G_AD21 G_AD20 G_AD19 G_AD18 G_AD17 G_AD16 G_AD15 G_AD14 G_AD13 G_AD12 G_AD11 G_AD10 G_AD9 G_AD8 G_AD7 G_AD6 G_AD5 G_AD4 G_AD3 G_AD2 G_AD1 G_AD0 AD24 AC22 AC24 AC25 AB24 AA25 AA24 AB23 Y23 AB26 AA27 AB27 AB25 AA28 Y26 Y27 V24 U25 U24 T24 U23 T23 V27 V26 U28 U27 T27 T26 R25 T25 R28 R27 G_AD31 G_AD30 G_AD29 G_AD28 G_AD27 G_AD26 G_AD25 G_AD24 G_AD23 G_AD22 G_AD21 G_AD20 G_AD19 G_AD18 G_AD17 G_AD16 G_AD15 G_AD14 G_AD13 G_AD12 G_AD11 G_AD10 G_AD9 G_AD8 G_AD7 G_AD6 G_AD5 G_AD4 G_AD3 G_AD2 G_AD1 G_AD0
82845E
SDQ63 SDQ62 SDQ61 SDQ60 SDQ59 SDQ58 SDQ57 SDQ56 SDQ55 SDQ54 SDQ53 SDQ52 SDQ51 SDQ50 SDQ49 SDQ48 SDQ47 SDQ46 SDQ45 SDQ44 SDQ43 SDQ42 SDQ41 SDQ40 SDQ39 SDQ38 SDQ37 SDQ36 SDQ35 SDQ34 SDQ33 SDQ32 SDQ31 SDQ30 SDQ29 SDQ28 SDQ27 SDQ26 SDQ25 SDQ24 SDQ23 SDQ22 SDQ21 SDQ20 SDQ19 SDQ18 SDQ17 SDQ16 SDQ15 SDQ14 SDQ13 SDQ12 SDQ11 SDQ10 SDQ9 SDQ8 SDQ7 SDQ6 SDQ5 SDQ4 SDQ3 SDQ2 SDQ1 SDQ0 SCB7 SCB6 SCB5 SCB4 SCB3 SCB2 SCB1 SCB0 SCS#3 SCS#2 SCS#1 SCS#0 SMA12 SMA11 SMA10 SMA9 SMA8 SMA7 SMA6 SMA5 SMA4 SMA3 SMA2 SMA1 SMA0 SDQS8 SDQS7 SDQS6 SDQS5 SDQS4 SDQS3 SDQS2 SDQS1 SDQS0 SCKE3 SCKE2 SCKE1 SCKE0 SBS1 SBS0 SRAS# SCAS# SWE# G5 E2 C2 B2 F3 F4 D3 C3 E5 C4 B5 E6 B3 D4 D6 C6 C7 B7 B9 E11 E8 D8 C9 E10 D10 C11 C13 B13 C10 B11 C12 E13 E17 C18 E19 C20 D18 C19 D20 C21 B21 D22 B23 C24 E21 C22 E23 D24 E25 D26 D27 B27 C25 B25 C27 E27 B28 F25 G27 H25 E28 C28 F27 G28 D14 C15 C17 B17 C14 B15 D16 C16 E7 F9 F7 E9 G22 E20 F13 F21 G20 G21 F19 E18 G19 G18 E16 F17 E12 E15 E3 C5 C8 D12 B19 C23 C26 F26 F23 H23 E22 G23 G13 G12 F11 G8 G11 M_DX63 M_DX62 M_DX61 M_DX60 M_DX59 M_DX58 M_DX57 M_DX56 M_DX55 M_DX54 M_DX53 M_DX52 M_DX51 M_DX50 M_DX49 M_DX48 M_DX47 M_DX46 M_DX45 M_DX44 M_DX43 M_DX42 M_DX41 M_DX40 M_DX39 M_DX38 M_DX37 M_DX36 M_DX35 M_DX34 M_DX33 M_DX32 M_DX31 M_DX30 M_DX29 M_DX28 M_DX27 M_DX26 M_DX25 M_DX24 M_DX23 M_DX22 M_DX21 M_DX20 M_DX19 M_DX18 M_DX17 M_DX16 M_DX15 M_DX14 M_DX13 M_DX12 M_DX11 M_DX10 M_DX9 M_DX8 M_DX7 M_DX6 M_DX5 M_DX4 M_DX3 M_DX2 M_DX1 M_DX0 M_SCBX7 M_SCBX6 M_SCBX5 M_SCBX4 M_SCBX3 M_SCBX2 M_SCBX1 M_SCBX0 M_SCS#1 M_SCS#0 M_SCS#3 M_SCS#2 M_SMAX12 M_SMAX11 M_SMAX10 M_SMAX9 M_SMAX8 M_SMAX7 M_SMAX6 M_SMAX5 M_SMAX4 M_SMAX3 M_SMAX2 M_SMAX1 M_SMAX0 M_SDQSX8 M_SDQSX7 M_SDQSX6 M_SDQSX5 M_SDQSX4 M_SDQSX3 M_SDQSX2 M_SDQSX1 M_SDQSX0 M_SCKE1 M_SCKE0 M_SCKE3 M_SCKE2 M_SBSX1 M_SBSX0 M_SRASX# M_SCASX# M_SWEX# 0RA 0RA 0RA 0RA 0RA R745 R746 R747 R748 R749 0RA 0RA 0RA 0RA 0RA 0RA 0RA 0RA 0RA 0RA 0RA 0RA 0RA 33RA 33RA 33RA 33RA 33RA 33RA 33RA 33RA 33RA R138 R141 R139 R142 R144 R145 R148 R146 R149 R150 R737 R738 R739 R740 R741 R742 R743 R744 R147 R140 R137 R127 M_SMA12 M_SMA11 M_SMA10 M_SMA9 M_SMA8 M_SMA7 M_SMA6 M_SMA5 M_SMA4 M_SMA3 M_SMA2 M_SMA1 M_SMA0 M_SDQS8 M_SDQS7 M_SDQS6 M_SDQS5 M_SDQS4 M_SDQS3 M_SDQS2 M_SDQS1 M_SDQS0 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 33RX4 4 2 4 2 8 6 8 6 4 2 8 6 8 6 4 2 8 6 6 2 4 2 8 4 6 4 8 4 8 2 6 2 8 4 8 4 6 2 6 2 8 4 8 2 6 2 6 4 4 2 8 4 8 6 6 2 6 2 6 4 8 4 8 2 8 4 4 2 6 2 8 6 3 1 3 1 7 5 7 5 3 1 7 5 7 5 3 1 7 5 5 1 3 1 7 3 5 3 7 3 7 1 5 1 7 3 7 3 5 1 5 1 7 3 7 1 5 1 5 3 3 1 7 3 7 5 5 1 5 1 5 3 7 3 7 1 7 3 3 1 5 1 7 5 RN1B RN1A RN2B RN2A RN1D RN1C RN2D RN2C RN3B RN3A RN4D RN4C RN3D RN3C RN4B RN4A RN5D RN5C RN7C RN7A RN5B RN5A RN7D RN7B RN8C RN8B RN9D RN9B RN8D RN8A RN9C RN9A RN13D RN13B RN14D RN14B RN13C RN13A RN14C RN14A RN15D RN15B RN16D RN16A RN15C RN15A RN16C RN16B RN17B RN17A RN18D RN18B RN17D RN17C RN18C RN18A RN19C RN19A RN20C RN20B RN19D RN19B RN20D RN20A RN10D RN10B RN12B RN12A RN10C RN10A RN12D RN12C M_D63 M_D62 M_D61 M_D60 M_D59 M_D58 M_D57 M_D56 M_D55 M_D54 M_D53 M_D52 M_D51 M_D50 M_D49 M_D48 M_D47 M_D46 M_D45 M_D44 M_D43 M_D42 M_D41 M_D40 M_D39 M_D38 M_D37 M_D36 M_D35 M_D34 M_D33 M_D32 M_D31 M_D30 M_D29 M_D28 M_D27 M_D26 M_D25 M_D24 M_D23 M_D22 M_D21 M_D20 M_D19 M_D18 M_D17 M_D16 M_D15 M_D14 M_D13 M_D12 M_D11 M_D10 M_D9 M_D8 M_D7 M_D6 M_D5 M_D4 M_D3 M_D2 M_D1 M_D0 M_SCB7 M_SCB6 M_SCB5 M_SCB4 M_SCB3 M_SCB2 M_SCB1 M_SCB0
M_D[0..63]
13,14
D
D
26
G_C/BE#[0..3]
G_C/BE#[0..3]
26
G_SBA[0..7]
G_SBA[0..7]
26
G_ST[0..2]
G_ST[0..2]
G_C/BE#3 G_C/BE#2 G_C/BE#1 G_C/BE#0
AA23 Y25 V23 V25
G_C/BE3# G_C/BE2# G_C/BE1# G_C/BE0#
C
V_1V5
R106 1KA G_ST1X 3 6,12 BSEL0 1K5A R117 BSELX0 R121 1K5A 1 Q1 BC847/B
V_1V5
G_SBA7 G_SBA6 G_SBA5 G_SBA4 G_SBA3 G_SBA2 G_SBA1 G_SBA0 R111 1KA
AE25 AE24 AE27 AE28 AG27 AG28 AH27 AH28
SBA7 SBA6 SBA5 SBA4 SBA3 SBA2 SBA1 SBA0
C
G_ST2 G_ST1 G_ST0 R123 2KA XXX1 XXX2
GND GND
AG26 AF24 AG25
ST2 ST1 ST0
M_SCB[0..7]
M_SCB[0..7]
13,14
2 R128
R124 2KA
GND
GND
M_SCS#[0..3]
M_SCS#[0..3]
13,14
SET=ENABLE DDR MODE
W28 Y24 W27 W24 W23 AG24 AH25 W25 0RA R143 G_WBF# AE23 AE22 AF22 AC27 AC28 R24 R23 AF27 AF26 GDEVSEL# GFRAME# GIRDY# GTRDY# GSTOP# GREQ# GGNT# GPAR WBF# RBF# PIPE# AD_STB1+ AD_STB1AD_STB0+ AD_STB0SB_STB+ SB_STB-
26
G_DEVSEL#
6K8A
M_SMA[0..12]
M_SMA[0..12]
13,14
26 G_FRAME# 26 G_IRDY# 26 G_TRDY# 26 G_STOP#
B
26 G_REQ# 26 G_GNT# 26 G_PAR
GND
B
26 26
G_RBF# G_PIPE#
M_SDQS[0..8]
M_SDQS[0..8]
13,14
26 G_ADSTB1+ 26 G_ADSTB126 G_ADSTB0+ 26 G_ADSTB026 G_SBSTB+ 26 G_SBSTB-
M_SCKE[0..3]
M_SCKE[0..3]
13,14
GND
40R2A
R160 GRCOMP
AD25
GRCOMP
RCVEN#
G3 H3
RCVENIN# RCVENOUT#
M_SBS1 M_SBS0
13,14 13,14
M_SRAS# 13,14 M_SCAS# 13,14 M_SWE# 13,14
A
A
Intel (R) 845E Interactive Client Reference Design
11,17,28,33,34 4,7,8,11..35 V_1V5 GND
V_1V5 GND
Title Size
MCH-AGP & DDR
Document Number
C
Date
5 4 3 2
B444B-W
Sheet
1
Rev
2.00
10 of 35
Friday, September 26, 2003
5
4
3
2
1
V_1V5
V_1V5
V_1V8
SPAREPIN SPAREPIN
V_CORE
R22 R29 U22 U26 W22 W29 AA22 AA26 AB21 AC29 AD21 AD23 AE26 AF23 AG29 AJ25
AD27 AD26
VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5
VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5
V_1V8
HLRCOMP AGPREF VCC1_5
VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8
NC2 NC1
40R2A
R162
HLRCOMP
P27 AA21
L25 L29 M22 N23 N26
N14 N16 P13 P15 P17 R14 R16 T15 U14 U16
R161 49R9A
28
D
AGP_REF
V_1V5
V_1V5A1 L3 4uH7/SB
+
T17
C70 100nA
C72 33u/TA GND_AMCH U17 U13 C75 VSS VSS
HVREF1 HVREF2 HVREF3 HVREF4 HVREF5 VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM
AB11 AB17 M7 R8 Y8 A5 A9 A13 A17 A21 A25 C1 C29 D7 D11 D15 D19 D23 D25 F6 F10 F14 F18 F22 G1 G4 G29 H8 H10 H12 H14 H16 H18 H20 H22 H24 J5 J7 K6 K22 K24 K26 L23
HVREF_MCH C69 100nA R163 100RA
D
U2C 82845E
GND
GND
GND
V_1V5
15
HI_REF
V_CORE
C77
C78
C79
C80
C83
C84
C85
GND GND V_DDRREF
24R9A 24R9A
R165 R166
HRCOMP1 HRCOMP0
AC13 AC2 J21 J9
HRCOMP1 HRCOMP0 SDREF2 SDREF1 SMRCOMP VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
+
+
100nA
100nA
100nA
100nA
100nA
100u/BP
V_DDRVTT
30R1A C91 100nA
R167
SMRCOMP C90 100nA
J28 AJ23 AG23 AJ21 AG21 AF20 AE21 AD20 AB20 AJ19 AG19 AE19 AC19 AF18 AD18 AB18 AA9 AB8 U8 M8 A3 A7 A11 A15 A19 A23 A27 D5 D9 D13 D17 D21 E1 E4 E26 E29 F8 F12 F16 F20 F24 G26 H9 H11 H13 H15 H17 H19 H21 J1 J4 J6 J22 J26 J29 K5 K7 K27 L1 L4 L6 L8 L22 L24 L26 M23 N1 N4 N8 N13 N15 N17 N22 N29 P6 P8
R168 150RA
C88 10nA
C89 10nA
GND
GND
100u/BP
GND
GND
GND
GND
GND
GND
Between MCH and DIMM
All VCCSM Balls of MCH 0603 / X7R
C
GND
GND
GND
GND
GND
C
100nA
C86
301RA
R164
C100
V_CORE
GND
GND
GND
GND
GND
GND
GND
1206 / X7R
1206 / X5R
B
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
P14 P16 R1 R4 R13 R15 R17 R26 T6 T8 T14 T16 T22 U1 U4 U15 U29 V6 V8 V22 AJ3 W1 W4 W8 W26 Y6 Y22
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
GND
GND
H27 K25 K23 J23 J25 G9 G10 G16 G17 H6 H7
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11
AA1 AA4 AA8 AA29 AB6 AB9 AB10 AB12 AB13 AB14 AB15 AB16 AB19 AB22 AC1 AC4 AC18 AC20 AC21 AC23 AC26 AD6 AD8 AD10 AD12 AD14 AD16 AD19 AD22 AE1 AE4 AE18 AE20 AE29 AF5 AF7 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF25 AG1 AG18 AG20 AG22 AH19 AH21 AH23 AJ5 AJ7 AJ9 AJ15 AJ13 AJ11 AJ17 AJ27
+
+
100nA
100nA
100nA
100nA
100nA
100u/TA
100u/TA
10u/CA
C102
C103
C104
C105
C106
C109
C110
10u/CA
10u/CA
GND
GND
GND
GND
10u/CA
GND
GND
GND
GND
GND
GND
100n
100n
100n
100n
100n
1206 / X7R
0603 / X7R
100nA
C101
C92
C93
C94
C95
C96
C97
C98
C99
C112
C113
C114
C115
100nA
100nA
GND
10u/CA
GND
GND
GND
1206 / X7R
0603 / X7R
SPAREPIN
GND
A
100nA
5
4
+
L4 4uH7/SB
33u/TA V_1V5A2 T13 P26 HSWNG AD13 AA7 VCC1_5 HI_REF HSWNG1 HSWNG0
WIRED
V_DDR
V_1V5
V_1V8
B
A
6,7,9,15,16,24..27
SPAREPIN
SPAREPIN
V_DDR V_DDRREF V_DDRVTT V_CORE V_1V8 V_1V5 GND
13,14,33,34 V_DDR 13,14,34 V_DDRREF 14,34 V_DDRVTT 4,6..8,17,33,35 15,17,33,35 10,17,28,33,34 4,7,8,10,12..35
3 2
Intel (R) 845E Interactive Client Reference Design
Title Size
V_CORE V_1V8 V_1V5 GND
MCH-POWER
Document Number
C
Date
B444B-W
Sheet
1
Rev
2.00
11 of 35
Friday, September 26, 2003
5
4
3
2
1
D
D
V_3V3 V_CLK
FB1 BLM21B601S C126 10u/CA C117 100nA C118 100nA C119 100nA C120 100nA C121 100nA C122 100nA U3
GND GND GND GND GND GND GND
ICS950201GT CPUCLK0+ CPUCLK0CPUCLK1+ CPUCLK1CPUCLK2+ CPUCLK23V66_0 3V66_1/VCH_CLK 66M_OUT0/3V66_2 66M_OUT1/3V66_3 66M_OUT2/3V66_3 66M_IN/3V66_5 48M_DOT 48M_USB PCICLK_F0 PCICLK_F1 PCICLK_F2 PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 14MREF 52 51 49 48 45 44 33 35 21 22 23 24 38 39 5 6 7 10 11 12 13 16 17 18 56
V_3V3 V_CLKA
50 46 32 19 14 8 37 26 1
VDDCPU VDDCPU VDD3V66 VDD3V66 VDDPCI2 VDDPCI1 VDDA48 VDDA VDDAREF GND GND GND GND GND GND GND GND GNDA FS2 FS1 FS0 CPU_STOP# PCI_STOP# PWRDN# SDATA SDCLOCK MULTESEL0 IREF VTT_PWRGD# XTAL_IN
CK_CPUX+ CK_CPUXCK_ITPX+ CK_ITPXCK_MCHX+ CK_MCHXCK_MCH66X CK_ICH66X CK_AGP66X CK_RESX0 CK_RESX1 CK_RESX2 CK_ICH48X CK_ICH33X CK_CPLDX CK_FWHX CK_LPC0X CK_LPC1X CK_LANX CK_MPCIX CK_SLOT1X CK_SLOT2X CK_SLOT3X CK_14MX
R169 R170 R171 R172 R173 R174 R175 R176 R177 R178 R179 R180 R185 R186 R187 R189 R191 R192 R193 R194 R195 R196 R197 R199
27RA 27RA 27RA 27RA 27RA 27RA 33RA 33RA 33RA 33RA 33RA 33RA 33RA 33RA 33RA 33RA 33RA 33RA 33RA 33RA 33RA 33RA 33RA 33RA
CK_CPU+ CK_CPU-
6 6
CK_ITP+ 8 CK_ITP- 8 CK_MCH+ CK_MCH9 9
FB2 BLM21B601S C116 10u/CA
V_CLK V_3V3 V_3V3 V_3V3 V_3V3
C124 10nA
C125 10nA
C123 10nA
GND
C
1KA
1KA
1KA
1KA
1KA
GND
GND
GND
GND
4 9 15 20 31 36 41 47 27 BSEL2 FS0 40 55 54 53 34 25 29 30
CK_RES0 CK_RES1 CK_RES2
CK_MCH66 9 CK_ICH66 16 CK_AGP66 26
C
CK_ICH48
16
GND V_CLK
1KA 1KA
R188 R190
6,10
BSEL0
CK_ICH33 15 CK_CPLD 18 CK_FWH 33 CK_LPC0 19 CK_LPC1 20 CK_LAN 24 CK_MPCI 29 CK_SLOT1 29 CK_SLOT2 29 CK_SLOT3 29 CK_14M 16,19,20,27
R181
R182
R183
R184
18 CPU_STOP# 18 PCI_STOP# 18 PWRDWN# 13..15 13..15 SMBISOD SMBISOC
V_3V3
R769
10KA
R198
MULTISEL IREF_CK
43 42 28 2
18
PGOOD408#
XTAL_OUT
3 A_CLKX2
R15
R16
R55
R54
R56 49R9A
C127
C128
C129
C130
C131
C132
C133
C134
C135
C136
C137
C139
C140
C141
C142
14MHZ3181/QA C144
B
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
10pA
C145 10pA
C143
C138
49R9A
49R9A
49R9A
49R9A
49R9A
R57
R200 1KA
R201 475RA
A_CLKX1
XT1
10pA
B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
GND GND
GND GND
A
A
Intel (R) 845E Interactive Client Reference Design
6,8,15..17,19,20,23,26..29,33,35 4,7,8,10,11,13..35 V_CLK V_3V3 GND
V_CLK V_3V3 GND
Title Size
CLK ICS950201
Document Number
C
Date
5 4 3 2
B444B-W
Sheet
1
Rev
2.00
12 of 35
Friday, September 26, 2003
5
4
3
2
1
DIMM 0
V_DDR
D
D
15 22 30 54 62 77 96 104 112 128 136 143 156 164 172 180
M_SMA0 M_SMA1 M_SMA2 M_SMA3 M_SMA4 M_SMA5 M_SMA6 M_SMA7 M_SMA8 M_SMA9 M_SMA10 M_SMA11 M_SMA12 M_SBS0 M_SBS1 M_SCS#[0..3] M_SCS#1 M_SCS#0
48 43 41 130 37 32 125 29 122 27 141 118 115 103 59 52 113 163 71 158 157 97 107 119 129 149 159 169 177 140 63 65 154
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 BA0 BA1 BA2
VDD VDD VDD VDD VDD VDD VDD VDD VDD
7 38 46 70 85 108 120 148 168
10,14
M_SMA[0..12]
M_SMA[0..12]
M_D[0..63]
M_D[0..63]
10,14
CN2 SW184/D1
10,14 10,14 10,14
M_SBS0 M_SBS1
M_SCS#[0..3]
CS3#/NC CS2#/NC CS1# CS0# DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8 WE# CAS# RAS#
GND
C
10,14 M_SWE# 10,14 M_SCAS# 10,14 M_SRAS# 10,14 9,14 9,14 M_SCKE[0..3] CK_SCK+[0..5] CK_SCK-[0..5] M_SCKE[0..3] CK_SCK+[0..5] CK_SCK-[0..5]
M_SWE# M_SCAS# M_SRAS#
M_SCKE0 M_SCKE1 CK_SCK+0 CK_SCK+1 CK_SCK+2 CK_SCK-0 CK_SCK-1 CK_SCK-2
21 111 16 137 76 17 138 75
CKE0 CKE1 CK0/DNU CK1 CK2/DNU CK0#/DNU CK1# CK2#/DNU
10,14
M_SDQS[0..8]
M_SDQS[0..8]
M_SDQS0 M_SDQS1 M_SDQS2 M_SDQS3 M_SDQS4 M_SDQS5 M_SDQS6 M_SDQS7 M_SDQS8
5 14 25 36 56 67 78 86 47 9 10 101 102 173 167
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 NC1 NC/RESET# NC2 NC3 NC4 NC/FETEN SDA SCL SA0 SA1 SA2 VDDID VDDSPD VREF GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 WP
2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88 174 175 178 179 44 45 49 51 134 135 142 144 90
M_D0 M_D1 M_D2 M_D3 M_D4 M_D5 M_D6 M_D7 M_D8 M_D9 M_D10 M_D11 M_D12 M_D13 M_D14 M_D15 M_D16 M_D17 M_D18 M_D19 M_D20 M_D21 M_D22 M_D23 M_D24 M_D25 M_D26 M_D27 M_D28 M_D29 M_D30 M_D31 M_D32 M_D33 M_D34 M_D35 M_D36 M_D37 M_D38 M_D39 M_D40 M_D41 M_D42 M_D43 M_D44 M_D45 M_D46 M_D47 M_D48 M_D49 M_D50 M_D51 M_D52 M_D53 M_D54 M_D55 M_D56 M_D57 M_D58 M_D59 M_D60 M_D61 M_D62 M_D63 M_SCB0 M_SCB1 M_SCB2 M_SCB3 M_SCB4 M_SCB5 M_SCB6 M_SCB7
C
B
B
12,14,15 12,14,15
SMBISOD SMBISOC
GND
91 92 181 182 183 82 184 1 C146 100nA
V_DDR V_DDRREF
M_SCB[0..7]
M_SCB[0..7]
10,14
GND
A
3 11 18 26 34 42 50 58 66 74 81 89 93 100 116 124 132 139 145 152 160 176
GND
A
Intel (R) 845E Interactive Client Reference Design
11,14,34 V_DDRREF 11,14,33,34 V_DDR 4,7,8,10..12,14..35 GND
V_DDRREF V_DDR GND
Title Size
DDR DIMM 0
Document Number
C
Date
5 4 3 2
B444B-W
Sheet
1
Rev
2.00
13 of 35
Friday, September 26, 2003
5
4
3
2
1
DIMM 1
V_DDR
M_D[0..63]
M_D[0..63]
10,13
V_DDR V_DDR
15 22 30 54 62 77 96 104 112 128 136 143 156 164 172 180
D
7 38 46 70 85 108 120 148 168
10,13
M_SMA[0..12]
M_SMA[0..12] M_SMA0 M_SMA1 M_SMA2 M_SMA3 M_SMA4 M_SMA5 M_SMA6 M_SMA7 M_SMA8 M_SMA9 M_SMA10 M_SMA11 M_SMA12 M_SBS0 M_SBS1 M_SCS#[0..3] M_SCS#3 M_SCS#2 48 43 41 130 37 32 125 29 122 27 141 118 115 103 59 52 113 163 71 158 157 97 107 119 129 149 159 169 177 140 63 65 154
V_DDRVTT
D
C147
C148
C149
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 BA0 BA1 BA2
VDD VDD VDD VDD VDD VDD VDD VDD VDD
C150
C151
C152
C153
C154
C155
C156
C157
C158
C159
C160
C161
C162
C163
C164
C165 100nA
CN3 SW184/D1
10,13 10,13 10,13
M_SBS0 M_SBS1
M_SCS#[0..3]
CS3#/NC CS2#/NC CS1# CS0# DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8 WE# CAS# RAS#
GND
C
10,13 9,13 9,13
M_SCKE[0..3] CK_SCK+[0..5] CK_SCK-[0..5]
M_SCKE[0..3] CK_SCK+[0..5] CK_SCK-[0..5] M_SCKE2 M_SCKE3 CK_SCK+3 CK_SCK+4 CK_SCK+5 CK_SCK-3 CK_SCK-4 CK_SCK-5 21 111 16 137 76 17 138 75 CKE0 CKE1 CK0/DNU CK1 CK2/DNU CK0#/DNU CK1# CK2#/DNU
6 4 2 8 4 6 8 2 6 4 2 6 8 4 2 6 4 8 2 4 8 2 6 2 4 6 8 6 2 4 6 2
5 3 1 7 3 5 7 1 5
220u/PB
10u/CA
10u/CA
10u/CA
10,13 M_SWE# 10,13 M_SCAS# 10,13 M_SRAS#
M_SWE# M_SCAS# M_SRAS#
C172
C173
C174
C175
C176
C177
C178
C179
C180
C181
C182
C183
C184
C185
C186
C187
C188
C189
C190
M_SDQS0 M_SDQS1 M_SDQS2 M_SDQS3 M_SDQS4 M_SDQS5 M_SDQS6 M_SDQS7 M_SDQS8
5 14 25 36 56 67 78 86 47 9 10 101 102 173 167
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 NC1 NC/RESET# NC2 NC3 NC4 NC/FETEN SDA SCL SA0 SA1 SA2 VDDID VDDSPD VREF GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
M_SBS0 M_SBS1 M_SCKE0 M_SCKE1 M_SCKE2 M_SCKE3 M_SCS#0 M_SCS#1 M_SCS#2 M_SCS#3 M_SDQS0 M_SDQS1 M_SDQS2 M_SDQS3 M_SDQS4 M_SDQS5 M_SDQS6 M_SDQS7 M_SDQS8
56RX4 56RA 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4
1 RN41A R752 5 3 7 1 3 7 1 5 1 3 5 7 5 1 3 5 1 RN38C RN38B RN38D RN38A RN26B RN26D RN26A RN26C RN44A RN40B RN37C RN34D RN29C RN6A RN24B RN22C RN30A
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
GND
V_DDRVTT
12,13,15 12,13,15
B
SMBISOD SMBISOC
V_DDR GND
91 92 181 182 183 82 184 1 C212 100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
WP
90
V_DDR V_DDRREF
3 11 18 26 34 42 50 58 66 74 81 89 93 100 116 124 132 139 145 152 160 176
M_SCB[0..7]
M_SCB[0..7]
10,13
GND
V_DDRVTT GND
GND
C213
C214
C215
C216
C217
C218
C219
C220
C221
C222
C223
C224
C225
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
GND
A
100nA
C226
100nA
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
44 45 49 51 134 135 142 144
M_SCB0 M_SCB1 M_SCB2 M_SCB3 M_SCB4 M_SCB5 M_SCB6 M_SCB7
M_SCB0 M_SCB1 M_SCB2 M_SCB3 M_SCB4 M_SCB5 M_SCB6 M_SCB7
47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4
6 8 4 8 2 4 6 4
5 7 3 7 1 3 5 3
RN31C RN31D RN30B RN30D RN31A RN31B RN30C RN11B
C192
C193
C194
C195
C196
C197
C198
C199
C200
C201
C202
C203
C204
C205
C206
C207
C208
C209
C210
C211
100nA
C191
10,13
M_SDQS[0..8]
M_SDQS[0..8]
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63
2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88 174 175 178 179
M_D0 M_D1 M_D2 M_D3 M_D4 M_D5 M_D6 M_D7 M_D8 M_D9 M_D10 M_D11 M_D12 M_D13 M_D14 M_D15 M_D16 M_D17 M_D18 M_D19 M_D20 M_D21 M_D22 M_D23 M_D24 M_D25 M_D26 M_D27 M_D28 M_D29 M_D30 M_D31 M_D32 M_D33 M_D34 M_D35 M_D36 M_D37 M_D38 M_D39 M_D40 M_D41 M_D42 M_D43 M_D44 M_D45 M_D46 M_D47 M_D48 M_D49 M_D50 M_D51 M_D52 M_D53 M_D54 M_D55 M_D56 M_D57 M_D58 M_D59 M_D60 M_D61 M_D62 M_D63
M_D0 M_D1 M_D2 M_D3 M_D4 M_D5 M_D6 M_D7 M_D8 M_D9 M_D10 M_D11 M_D12 M_D13 M_D14 M_D15 M_D16 M_D17 M_D18 M_D19 M_D20 M_D21 M_D22 M_D23 M_D24 M_D25 M_D26 M_D27 M_D28 M_D29 M_D30 M_D31 M_D32 M_D33 M_D34 M_D35 M_D36 M_D37 M_D38 M_D39 M_D40 M_D41 M_D42 M_D43 M_D44 M_D45 M_D46 M_D47 M_D48 M_D49 M_D50 M_D51 M_D52 M_D53 M_D54 M_D55 M_D56 M_D57 M_D58 M_D59 M_D60 M_D61 M_D62 M_D63
47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RA 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4 47RX4
2 8 6 2 4 6 4 8 4 8 2 4 6 2 6 8 8 2 2 6 6 4 4 8 4 2 6 2 6 4 8 6 2 8 6 8 4 2 4 2 6 4 6 8 4 8 2 4 6 2 4 8 2 6 8 2 4 4 6 6 8 8 2
1 7 5 1 3 5 3 7 3 7 1 3 5 1 5 7 7 1 1 5 5 3 3 7 3 1 5 1 5 3 7 5 1 7 5 7 3 1 3 1 5 3 5 7 3 7 1 3 5 1 3 7 1 5 7 1 3 3 5 5 7 7 1
RN45A RN45D RN44C RN43A RN45B RN45C RN44B RN44D RN43B RN43D RN39A RN39B RN43C RN40A RN40C RN40D RN39D RN37A RN36A RN36C RN39C RN37B RN36B RN36D R238 RN34B RN33A RN33C RN34A RN34C RN33B RN33D RN11C RN29A RN29D RN28C RN11D RN29B RN28A RN28B RN27A RN27C RN6B RN6C RN28D RN27B RN6D RN25A RN25B RN25C RN23A RN23B RN25D RN24A RN24C RN24D RN22A RN22B RN21B RN21C RN23C RN23D RN22D RN21A
+
+
+
+
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100nA
100u/TA
100u/TA
100u/TA
GND
At Corner of DIMMS
100u/TA
GND
Between DIMMS
V_DDRVTT
C167
C169
C170
V_DDRVTT
+
M_SMA0 M_SMA1 M_SMA2 M_SMA3 M_SMA4 M_SMA5 M_SMA6 M_SMA7 M_SMA8 M_SMA9 M_SMA10 M_SMA11 M_SMA12 M_SWE# M_SCAS# M_SRAS#
56RA 56RX4 56RX4 56RX4 56RX4 56RX4 56RX4 56RX4 56RX4 56RX4 56RA 56RX4 56RX4 56RX4 56RX4 56RX4
R750 RN32C RN32B RN32A RN35D RN35B RN35C RN42D RN35A RN42C R751 3 RN42B 1 RN42A 5 RN41C 7 RN41D 3 RN41B
C171
100nA
C166
C
GND
V_DDRVTT
B
A
V_DDRVTT
47RX4 56RX4 47RX4 47RX4 47RX4
8 8 8 8 2
7 7 7 7 1
RN37D RN32D RN27D RN21D RN11A
Intel (R) 845E Interactive Client Reference Design
11,34 V_DDRVTT 11,13,34 V_DDRREF 11,13,33,34 V_DDR 4,7,8,10..13,15..35 GND
V_DDRVTT V_DDRREF V_DDR GND
Title Size
DDR DIMM 1
Document Number
C
Date
5 4 3 2
B444B-W
Sheet
1
Rev
2.00
14 of 35
Friday, September 26, 2003
5
4
3
2
1
V_3V3SB
V_3V3
V_3V3SB
V_3V3SB
V_3V3SB
V_RTC
R309 1K5A
R310 8K2A SMBDATA
R311 10KA
R312 10KA
R313 10KA
R314 10KA
SMBDATA
24,29,33
V_12V0
24,29
D
P_AD[0..31] P_AD0 P_AD1 P_AD2 P_AD3 P_AD4 P_AD5 P_AD6 P_AD7 P_AD8 P_AD9 P_AD10 P_AD11 P_AD12 P_AD13 P_AD14 P_AD15 P_AD16 P_AD17 P_AD18 P_AD19 P_AD20 P_AD21 P_AD22 P_AD23 P_AD24 P_AD25 P_AD26 P_AD27 P_AD28 P_AD29 P_AD30 P_AD31 H5 J3 H3 K1 G5 J4 H4 J5 K2 G2 L1 G4 L2 H2 L3 F5 F4 N1 E5 N2 E3 N3 E4 M5 E2 P1 E1 P2 D3 R1 D2 P4 J2 K4 M4 N4 C1 E6 A7 B7 D6 C5 B1 A2 B3 C7 B6 A6 P5 M3 F1 L5 F2 F3 G1 L4 PCIRSTX# U5 M2 K5 W2 B5 E8 R357 8K2A XXX1 XXX2
GND V_3V3SB
D
D
24,29
P_CBE#[0..3] P_CBE#0 P_CBE#1 P_CBE#2 P_CBE#3
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE0# C/BE1# C/BE2# C/BE3# GNT0# PCI GNT1# GNT2# GNT3# GNT4# GNT5#/GNTB#/GPIO17 REQ0# REQ1# REQ2# REQ3# REQ4# REQ5#/REQB#/GPIO1 PCICLK DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR# PCIRST# PLOCK# SERR# PME# REQA#/GPIO0 GNTA#/GPIO16
U4A ICH4
SM
INTRUDER# SMLINK0 SMLINK1 I/F SMBDATA SMBCLK GPIO11/SMBALERT#
W6 AC3 AB1 AB4 AC4 AA5
INTRUDER# SMBDATA SMBCLK SMBALERT#
INTRUDER#
33
G
Q2 2N7002/B
S
SMBISOD SMBISOD 12..14
SMBALERT#
24
CPU I/F
A20GATE A20M# DPSLP#/NC FERR# IGNNE# INIT# INTR NMI CPUPWRGD RCIN# CPUSLP# SMI# STPCLK#
Y22 AB23 U23 AA21 W21 V22 AB22 V21 Y23 U22 U21 W23 V23
A20GATE H_A20M# SPAREPIN H_FERR# H_IGNNE# H_INIT# H_INTR H_NMI PWRGOOD KB_RST# CPUSLP# H_SMI# STPCLK#
A20GATE H_A20M#
19 6
V_3V3SB
V_3V3
H_FERR# 6 H_IGNNE# 6 H_INIT# 6 H_INTR 6 H_NMI 6 PWRGOOD 6 KB_RST# 19 CPUSLP# 6,18 H_SMI# 6 STPCLK# 6 H_HI[0..10] 9
R315 1K5A
R316 8K2A SMBCLK
SMBCLK
24,29,33
V_12V0
D
G
Q3 2N7002/B
S
SMBISOC SMBISOC 12..14
Hublink I/F
C
HI0 HI1 HI2 HI3 HI4 HI5 HI6 HI7 HI8 HI9 HI10 HI11
L19 L20 M19 M21 P19 R19 T20 R20 P23 L22 N22 K21 P21 N20 R23 M23 R22
H_HI0 H_HI1 H_HI2 H_HI3 H_HI4 H_HI5 H_HI6 H_HI7 H_HI8 H_HI9 H_HI10 SPAREPIN H_HISTB+ H_HISTBHI_COMP R318 40R2A
GND
V_1V8
V_3V3
29 29 29 29 24 8K2A 8K2A 8K2A 8K2A 8K2A 8K2A P_REQ#0 P_REQ#1 P_REQ#2 P_REQ#3 P_REQ#4 LM87INT# 29 29 29 29 24 33 12
P_GNT#0 P_GNT#1 P_GNT#2 P_GNT#3 P_GNT#4 P_REQ#0 P_REQ#1 P_REQ#2 P_REQ#3 P_REQ#4 LM87INT#
HI_STBS/HI_STB HI_STBF/HI_STB#
H_HISTB+ H_HISTB-
9 9
I/F
R317 150RA
Hubinterface reference voltages
HI_REF 11
C
HICOMP HIREF HI_VSWING
SPAREPIN
R320 R321 R322 R324 R326 R328
R319 150RA APICCLK APICD0 APICD1 R323 R325 R327 0RA 10KA 10KA
C227 100nA
C228 10nA
APICCLK APICD0 APICD1 PIRQA# PIRQB# PIRQC# PIRQD# GPIO2/PIRQE# GPIO3/PIRQF# GPIO4/PIRQG# GPIO5/PIRQH# IRQ14 IRQ15 SERIRQ
J19 H19 K20 D5 C2 B4 A3 C8 D7 C3 C4 AC13 AA19 J22
GND GND
CK_ICH33 P_DEVSEL# P_FRAME# P_IRDY# P_TRDY# P_STOP# P_PAR
R329 R330 R331 R333 R336
8K2A P_DEVSEL# 8K2A P_FRAME# 8K2A P_IRDY# 8K2A P_TRDY# 8K2A P_STOP#
24,29 24,29
INT I/F
INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH# INT_IRQ14 INT_IRQ15 SERIRQ U5 1 2 3 4
GND
INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH# INT_IRQ14 INT_IRQ15 SERIRQ
26,29 29 29 29 29 29 24 30 30
V_3V3
24,29 24,29 24,29 24,29
18..20,29
V_3V3SB V_3V3SB
R341
8K2A P_PERR#
24,29
P_PERR#
EEPROM
R346
B
V_3V3SB
8K2A P_LOCK# 8K2A P_SERR# 8K2A P_PME# 8K2A P_REQA#
29 24,29 24,29 29 29
P_LOCK# P_SERR# P_PME# P_REQA# P_GNTA# populate for "top block swap"
EE_CS EE_SHCLK EE_TODIN EE_TODOUT
D10 C12 A8 D11
R349 R351
EE0_CS EE0_CK EE0_DI EE0_DO R347 XXX1 10KA XXX2
CS CK DI DO
VCC NC 16/8# GND
8 7 6 5
INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH# INT_IRQ14 INT_IRQ15 SERIRQ
R332 R334 R335 R337 R338 R339 R340 R342 R344 R345 R348
8K2A 8K2A 8K2A 8K2A 8K2A 8K2A 8K2A 8K2A 8K2A 8K2A 8K2A
B
EE0_8#_16
R343 10KA XXX1 XXX2
C229 100nA
B
AT93LC46-2V7 R350 R352 R354 R355 R356 R358 R359 R360 22RA 22RA 22RA 22RA 22RA 22RA 22RA 22RA
GND
LAN_CLOCK LAN_RST# LAN_RSTSYNC
C11 Y5 B11 A10 A9 A11 B10 C10 A12
CK_ICHLANX XC_LAN0RST# LAN_RSCX LAN_XRXD0 LAN_XRXD1 LAN_XRXD2 LAN_XTXD0 LAN_XTXD1 LAN_XTXD2
CK_ICHLAN
31
GND
V_3V3
R353
XC_LAN0RST# 18 LAN_RSTSYNC 31 LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 31 31 31 31 31 31
LAN I/F
LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2
A
V_3V3
U6A 1 R365 0RA C230 10pA XXX1 XXX2
GND V_3V3SB
OE# IN
PCIRST#
INITB#
2
VCC OUT GND
14 3 7
XRST_SLOTS#
R364 P_RST_SLOTS# 33RA
GND
R361 29 10KA
Level Shifter for Firmware Hub INIT#
R362 470RA
R363 301RA
74LVT125 U6B 4 5 OE# IN VCC OUT GND 14 6 7 P_RSTX0# R366 P_RST0# 33RA R368 P_RST1# 33RA 19,20,24,26 9,18,33
3 1 3 Q4 BC847/B
FWH_INIT#
33
74LVT125 U6C 10 9 OE# IN VCC OUT GND 14 8 7 P_RSTX1#
H_INIT#
R367 470RA
INITB 1
2 Q5 BC847/B 2
GND
74LVT125 U6D C231
A
13 12
OE# IN
100nA
VCC OUT GND
14 11 7
IDE_RSTX#
R369 IDE_RST# 33RA C232 C233 C234 C235 10pA XXX1 XXX2
GND
30
A
74LVT125
GND GND GND
10pA XXX1 XXX2
10pA 10pA XXX1 XXX1 XXX2 XXX2
GND
6,7,9,11,16,24..27 11,17,33,35 6,8,12,16,17,19,20,23,26..29,33,35 16..20,24,25,29,31..33,35 16,17 23,27,29,32..35 4,7,8,10..14,16..35
SPAREPIN V_1V8 V_3V3 V_3V3SB V_RTC V_12V0 GND
2
SPAREPIN
V_1V8 V_3V3 V_3V3SB V_RTC V_12V0 GND
GND
GND
Intel (R) 845E Interactive Client Reference Design
Title Size
ICH4-SYSBUS & PCI
Document Number
C
Date
B444B-W
Sheet
1
Rev
2.00
15 of 35
Friday, September 26, 2003
5
4
3
5
4
3
2
1
V_RTC
delay RTCRST# for 10-20ms R370 10KA NRMRTCRST#
V_3V3SB
JP1 1 2 3 SM03/RA
D
R371 C236
D
CLRRTCRST#
1-2 2-3
normal (default) clear CMOS
100RA
GND
R372 8K2A
GND
1u/CA
V_RTCBIAS
19 18
SIO0_SMI# XC_GPIO3 SPAREPIN
R2 AC2 V20 AA1 Y1 AA6 TP0 SPAREPIN AB6 AB2 W18 Y4 Y2 AA2 T3 W19 Y21 AA4 AB3 V1 W20
GPIO6/AGPBUSY# GPIO24/CLKRUN# NC/DPRSLPVR PWRBTN# RI# RSMRST# PWROK TP0/BATLOW# GPIO19/SLP_S1# SLP_S3# SLP_S4# SLP_S5# GPIO21/C3_STAT# GPIO20/STPCPU# GPIO18/STPPCI# SUSCLK SUS_STAT#/LPCPD# THRM# THRMTRIP#
U4B ICH4
CLOCK I/F
CLK14 CLK48 CLK66 RTCRST# RTCX1 RTCX2
J23 F19 T21 W7 AC7 AC6
CK_14M CK_ICH48 CK_ICH66 RTCRST# RTCX1 RTCX2
CK_14M 12,19,20,27 CK_ICH48 12 CK_ICH66 12
R373 10MA XT2 RTCX1 R374 10MA RTCX2 32KHZ768/QT 10pA 10pA
GND
33
PWRBTN# 18,24 RI#
C237
GND
V_3V3SB
18 8K2A 18
RSMRST#
IDE_PDA[0..2] PDA0 PDA1 PDA2 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 PIORDY PDIOR# PDIOW# PDDREQ PDDACK# PDCS1# PDCS3# AA13 AB13 W13 AB11 AC11 Y10 AA10 AA7 AB8 Y8 AA8 AB9 Y9 AC9 W9 AB10 W10 W11 Y11 AB12 AC12 W12 AA11 Y12 Y13 AB14 IDE_PDA0 IDE_PDA1 IDE_PDA2 IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15 IDE_PIORDY IDE_PDIOR# IDE_PDIOW# IDE_PDDREQ IDE_PDDACK# IDE_PDCS1# IDE_PDCS3#
30
R375
PWRGD_ICH
C238 IDE_PDD[0..15] 30
GND
PM I/F
18,31,32 18 18
SLP_S3# SLP_S4# SLP_S5# SPAREPIN SPAREPIN SPAREPIN
18,19
CK_32KSUS 19,20 6 LPCPD# 33 THERM# THERMTRIP#
R376
33RA
CK_32KSUSX
Primary
V_3V3
R377 4K7A
C
C
V_3V3
18
XC_GPIO4 SPAREPIN
J21 Y20 V19
GPIO23/SSMUXSEL CPUPERF#/GPIO22 VRMPWRGD/VGATE
R378 8K2A AC_SDOUTY 1
18
VRMPWRGD_ICH
Speedstep
23,29
CK_ACBITCLK AC_RST#
V_3V3
B8 C13 XXX2 R381 10KA AC_SDIN0X XXX1 R380 33RA AC_SDIN1X R379 33RA AC_SDIN2X D13 A13 B13 C9 AC_SDOUTX D9
AC_BIT_CLK AC_RST# AC_SDIN0 AC_SDIN1 AC_SDIN2 AC_SYNC AC_SDOUT
IDE I/F
IDE_PIORDY IDE_PDIOR# IDE_PDIOW# IDE_PDDREQ IDE_PDDACK# IDE_PDCS1# IDE_PDCS3#
30 30 30 30 30 30 30
23,29 JP2 SM02/RA XXX1 XXX2 29 23 23,29
short for SAFE MODE
2 R382 33RA
IDE_SDA[0..2]
IDE_SDA[0..2]
30
AC_SDIN1 AC_SDIN2 AC_SYNC
AC'97 I/F
SDA0 SDA1 SDA2 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 SIORDY SDIOR# SDIOW# SDDREQ SDDACK# SDCS1# SDCS3#
AA20 AC20 AC21 W17 AB17 W16 AC16 W15 AB15 W14 AA14 Y14 AC15 AA15 Y15 AB16 Y16 AA17 Y17 AC19 Y18 AA18 AB18 AB19 AB21 AC22
IDE_SDA0 IDE_SDA1 IDE_SDA2 IDE_SDD0 IDE_SDD1 IDE_SDD2 IDE_SDD3 IDE_SDD4 IDE_SDD5 IDE_SDD6 IDE_SDD7 IDE_SDD8 IDE_SDD9 IDE_SDD10 IDE_SDD11 IDE_SDD12 IDE_SDD13 IDE_SDD14 IDE_SDD15 IDE_SIORDY IDE_SDIOR# IDE_SDIOW# IDE_SDDREQ IDE_SDDACK# IDE_SDCS1# IDE_SDCS3#
IDE_SDD[0..15]
IDE_SDD[0..15]
30
23,29
AC_SDOUT
18..20,33
L_AD[0..3] L_AD0 L_AD1 L_AD2 L_AD3 T2 R4 T4 U2 T5 U3 U4 LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 LFRAME#/FWH4 LDRQ0# LDRQ1#
Secondary LPC I/F
V_3V3
18..20,33 19 20
L_FRAME# L_DRQ#0 L_DRQ#1
B
31 31 31 31 32 32 32 32 32 32 32 32 31 31 32 32 32 32 R388 1KA XXX1 XXX2 SPKR 33
USB_P0+ USB_P0USB_P1+ USB_P1USB_P2+ USB_P2USB_P3+ USB_P3USB_P4+ USB_P4USB_P5+ USB_P5-
C20 D20 A21 B21 C18 D18 A19 B19 C16 D16 A17 B17 B15 C14 A15 B14 A14 D14 R387 22RA USB_RBIAS USB_RBIAS# A23 B23
R386
4K7A
USBP0P USBP0N USBP1P USBP1N USBP2P USBP2N USBP3P USBP3N USBP4P USBP4N USBP5P USBP5N OC0# OC1# OC2# OC3# OC4# OC5# USBRBIAS USBRBIAS#
IDE_SIORDY IDE_SDIOR# IDE_SDIOW# IDE_SDDREQ IDE_SDDACK# IDE_SDCS1# IDE_SDCS3#
30 30 30 30 30 30 30
B
USB I/F
V_3V3
USB_P0OC# USB_P1OC# USB_P2OC# USB_P3OC# USB_P4OC# USB_P5OC#
GND
GPIO
C
23,33 SPKR
H23 SYS_RESET# Y3
SPKR SYS_RESET#
MISC
GPI7 GPI8 GPI12 GPI13 GPIO25 GPIO27 GPIO28 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43
R3 V4 V5 W3 V2 W1 W4 J20 G22 F20 G20 F21 H20 F23 H22 G23 H21 F22 E23
SIO1_SMI# 20 SIO0_PME# 19 SIO1_PME# 20 XC_GPIO2 18 LAN0_ENA 31 MPCI_ACT# 29 XC_GPIO1 18 IDE_PPDIAG# 30 IDE_SPDIAG# 30 USB_PWR2ENA# 32 USB_PWR3ENA# 32 FWH_WP# 33 FWH_TBL# 33 RISER_ID1 29 RISER_ID2 29 AMP_SHDN 23 NOGO 29 P_PRSNT1# 29 P_PRSNT2# 29
A
A
ICH4 Strapping Options
R A B C JP Signal P_GNTA# EE_DOUT SPKR AC_SDOUTX Function top block swap reserved no reboot mode safe mode Default NO STUFF NO STUFF NO STUFF OPEN
6,7,9,11,15,24..27 6,8,12,15,17,19,20,23,26..29,33,35 15,17..20,24,25,29,31..33,35 15,17 17 4,7,8,10..15,17..35
SPAREPIN V_3V3 V_3V3SB V_RTC V_RTCBIAS GND
2
SPAREPIN
V_3V3 V_3V3SB V_RTC V_RTCBIAS GND
Intel (R) 845E Interactive Client Reference Design
Title Size
ICH4-LPC & IDE & USB
Document Number
C
Date
B444B-W
Sheet
1
Rev
2.00
16 of 35
Friday, September 26, 2003
5
4
3
5
4
3
2
1
V_5V0
V_3V3
V_3V3
V_5V0SB
V_RTC
Battery circuitry for RTC and CMOS AB5
V_RTCBIAS
V_3V3SB
V_RTC
C239 R389 1KA 100nA 1 D1 3 2 BAT54C
GND
VCCRTC VBIAS VCC5REFSUS
U4C ICH4
Y6 E15
2 D2 BAT54C 3 C240 1u/CA
D
1 V_BAT R390 1KA
V_5V0REF C241 1u/CA
V_3V3SB
V6 E7 C242 100nA V9 V8 V7 K14 F18 F17 F16 F15 F10 E11
VCC5REF VCC5REF
GND
GND
C243 V_BATX R391 1KA V_RTCBIASX 47nA
V_RTCBIAS
+ C244
C245 100nA
C246 100nA
C247 100nA
22u/TA BAT1 SM02/BA
GND
VCCSUS3V3 VCCSUS3V3 VCCSUS3V3 VCCSUS3V3 VCCSUS3V3 VCCSUS3V3 VCCSUS3V3 VCCSUS3V3 VCCSUS3V3 VCCSUS3V3
F9 E9
VCCLAN3V3/VCCSUS3V3 VCCLAN3V3/VCCSUS3V3
GND
V_3V3
+ C251 + C252
C253 100nA
C254 100nA
C255 100nA
C256 100nA
C257 100nA
C258 100nA
C259 100nA
22u/TA
22u/TA
C
GND
V_1V8
V18 V16 V10 U1 P6 P12 M10 K6 J18 J1 H6 H18 B2 AC8 AC17 A5
VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3
+ C265
C266 100nA
C267 100nA T22 P18 M14 L23 VCCHI VCCHI VCCHI VCCHI
4u7/TA
GND V_CORE
U18 P14 AA23 C271 100nA F7 F6
VCC_CPUIO VCC_CPUIO VCC_CPUIO
+ C270
4u7/TA
VCCLAN1V5/VCCSUS1V5 VCCLAN1V5/VCCSUS1V5
V_1V5SB
GND
GND
+ C274
C275 100nA
C276 100nA
C277 100nA
22u/TA
B
U6 T6 R6 G18 F14 E20 E13 E12
VCCSUS1V5 VCCSUS1V5 VCCSUS1V5 VCCSUS1V5 VCCSUS1V5 VCCSUS1V5 VCCSUS1V5 VCCSUS1V5
GND V_1V5
+ C282
C284 100nA
C285 100nA
C286 100nA
V_1V5
22u/TA
V14 U19 T18 P10 K22 K18 K12 K10
VCC1V5 VCC1V5 VCC1V5 VCC1V5 VCC1V5 VCC1V5 VCC1V5 VCC1V5
GND
C22 C740 10nA C292 100nA
VCCPLL
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Y7 Y19 W8 W5 W22 V3 V17 V15 U20 T23 T19 T1 R5 R21 R18 P3 P22 P20 P13 P11 N5 N23 N21 N19 N14 N13 N12 N11 N10 M22 M20 M13 M12 M11 M1 L21 L14 L13 L12 L11 L10 K3 K23 K19 K13 K11 J6 H1 G6 G3 G21 G19 F8 E22 E21 E19 E18 E17 E16 E14 E10 D22 D8 D4 D23 D21 D19 D17 D15 D12 D1 C6 C23 C21 C19 C17 C15 B9 B22 B20 B18 B16 B12 AC5 AC23 AC18 AC14 AC10 AC1 AB7 AB20 AA9 AA3 AA22 AA16 AA12 A4 A22 A20 A18 A16 A1
D
+
C
B
GND
GND
GND
A
A
35 10,11,28,33,34 11,15,33,35 15,16,18..20,24,25,29,31..33,35 6,8,12,15,16,19,20,23,26..29,33,35 19,21,22,31..35 19..21,23,25..27,29..35 4,6..8,11,33,35 15,16 16 4,7,8,10..16,18..35
5 4 3
V_1V5SB V_1V5 V_1V8 V_3V3SB V_3V3 V_5V0SB V_5V0 V_CORE V_RTC V_RTCBIAS GND
2
V_1V5SB V_1V5 V_1V8 V_3V3SB V_3V3 V_5V0SB V_5V0 V_CORE V_RTC V_RTCBIAS GND
Intel (R) 845E Interactive Client Reference Design
Title Size
INTEL ICH4 - 03
Document Number
C
Date
B444B-W
Sheet
1
Rev
2.00
17 of 35
Friday, September 26, 2003
5
4
3
2
1
DPSLP#
V_3V3SB
7
3 R392 470RA CPUSLP 3 R394 6,15 CPUSLP# 470RA 2
GND
DPSLP
R393 470RA
DPSLPX
1
Q6 BC847/B 2
D
GND
D
CPUSLPX#
1
Q7 BC847/B
V_3V3SB
V_3V3SB
R395 10KA CN4
R396 10KA
R397 10KA
R398 10KA
V_3V3SB V_3V3SB
C293 100nA
1 3 5 8 2
VCC NC1 TCK NC2 TDO NC3 TDI GND TMS SM09/RA
4 6 7 9
GND
R399
10KA
XCTCK XCTDO XCTDI XCTMS PORT_EN
U7 62 73 4 15 11 87 88 89 90 72 71 70 69 68 67 65 64 63 75 76 77 78 79 80 81 83 84 85 TCK/C1 TDO/A1 TDI/F1 TMS/H1 PORT_EN/PE CLK3/IN3 CLK2/IN2 CLK1/IN1 CLK0/IN0 A2 A3 A4 A5 A6 A10 A12 A13 A14 B0 B1 B2 B3 B4 B5 B6 B10 B11 B12 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 E0 E1 E2 E3 E4 E5 E6 E12 E13 E14 3 18 34 39 51 66 82 91 2 1 100 99 98 97 96 94 93 92 C294 100nA C295 100nA C296 100nA C297 100nA
12
C
V_3V3SB
16,19 16,19,20,33
CK_CPLD CK_32KSUS L_AD[0..3]
GND
V_3V3SB
R400 R401
10KA 10KA
XC_CK1 XC_CK0 L_AD0 L_AD1 L_AD2 L_AD3
GND
C
R402 10KA 16,19,20,33 L_FRAME# 15,19,20,29 SERIRQ 9,15,33 P_RST0# 6 SKTOCC# 7,33 VID[0..4]
NW_MOBILE# VID0 VID1 VID2 VID3 VID4 PWMVID0 PWMVID1 PWMVID2 PWMVID3 PWMVID4
VRMPWRGD_ICH 16 PWRGD_ICH 16 VRMOUTEN 35 EN_VDDR 34 EN_V1V5 34 EN_1V2VID 35 SD_DDRVTT# 34 XC_GPIO1 16 XC_GPIO2 16 RI# 16,24 R403
V_3V3SB
R404 10KA
SET = Mobile NORTHWOOD
JP3 SM02/RA XXX1 XXX2 2
10KA
V_3V3SB
GND V_3V3SB GND
HW REV 2
SW_REV2 SW_REV1 SW_REV0
10KA
35
PWMVID[0..4]
GND
R406 10KA
F2 F3 F4 F5 F6 F10 F13 F14 F15
5 6 7 8 9 10 12 13 14
XC_LAN0RST# 15 XC_GPIO3 16 XC_GPIO4 16
1
R405
SW REV 0
20,24,29 CLKRUN# 12 CPU_STOP# 12 PCI_STOP# 12 PWRDWN# 12 PGOOD408# 16 RSMRST# 16,31,32 SLP_S3# 16 SLP_S4# 16 SLP_S5#
B
61 60 58 57 56 55 54 53 52 40 41 42 44 45 46 47 48 49 50 95 86 74
GND
C2 C3 C5 C6 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D10 D11 D12 D13 GND7 GND6 GND5 XCR3128XL
G1 G2 G3 G4 G5 G6 G10 G11 G12 G13
37 36 35 33 32 31 30 29 28 27
CPUSLP DPSLP 7SEG0AX 7SEG0BX 7SEG0CX 7SEG0DX 7SEG0EX 7SEG0FX 7SEG0GX 7SEG0DPX
0RA
0RA R408
R410 R411 R412 R413 R414 R415 R416 R417
150RA 150RA 150RA 150RA 150RA 150RA 150RA 150RA
7SEG0A 7SEG0B 7SEG0C 7SEG0D 7SEG0E 7SEG0F 7SEG0G 7SEG0DP
7 6 4 2 1 10 9 5
A B C D E F G DP
R407
AN1 AN2
3 8
U8 TDSR1150
R409
0RA
V_3V3SB
B
GND
7,8 ITP_DBR# 35 PWROK_VRM 35 PWROK_ATX 35 VIDPWRGD 34 PG_VDDR 34 PG_V1V5 35 PS_ON R768 10KA DELAY3V3
H2 H3 H5 H6 H10 H11 H12 H13 H14 GND1 GND2 GND3 GND4
16 17 19 20 21 22 23 24 25 26 38 43 59
7SEG1AX 7SEG1BX 7SEG1CX 7SEG1DX 7SEG1EX 7SEG1FX 7SEG1GX 7SEG1DPX
R418 R419 R420 R421 R422 R423 R424 R425
150RA 150RA 150RA 150RA 150RA 150RA 150RA 150RA
7SEG1A 7SEG1B 7SEG1C 7SEG1D 7SEG1E 7SEG1F 7SEG1G 7SEG1DP
7 6 4 2 1 10 9 5
A B C D E F G DP
AN1 AN2
3 8
U9 TDSR1150
GND V_3V3SB
EN_DDRSUP#
GND
34
R760 10KA
+ C741
4u7/TA
A
GND
A
Intel (R) 845E Interactive Client Reference Design
15..17,19,20,24,25,29,31..33,35 6,8,12,15..17,19,20,23,26..29,33,35 4,7,8,10..17,19..35 V_3V3SB V_3V3 GND
V_3V3SB V_3V3 GND
Title Size
GLUE LOGIC
Document Number
C
Date
5 4 3 2
B444B-W
Sheet
1
Rev
2.00
18 of 35
Friday, September 26, 2003
5
4
3
2
1
V_3V3SB
V_3V3
C298 100nA
D
V_3V3SB
+ C299
C300 100nA
C301 100nA
C302 100nA
C303 100nA
D
4u7/TA
18
53 65 93
VTR
VCC VCC VCC
R426 10KA 12 15,20,24,26 16 16 16,20 CK_LPC0 P_RST1# 29 26 17 25 27 30 L_AD0 L_AD1 L_AD2 L_AD3 20 21 22 23 24 50 55 52 54 51 28 64 63 57 56 59 58 XJ1X XJ1Y 36 37 32 33 38 39 34 35 48 49 21 SP2_SD# I/O base address at 0x02E MIDI_IN MIDI_OUT R436 R437 R435
GND
VREF
44
GND
GND
PCI_CLOCK PCI_RESET# IO_PME#/GPIO42 LDRQ# LPCPD# SER_IRQ LAD0 LAD1 LAD2 LAD3 LFRAME# IO_SMI#/GPIO27 FAN1/GPIO33 FAN_TACH1/GPIO31 FAN2/GPIO32 FAN_TACH2/GPIO30 GPIO43/DDRC A20M/GPIO37 KBDRST#/GPIO36 KCLOCK KDAT MCLOCK MDAT J1X/GPIO14 J1Y/GPIO15 J1B1/GPIO10 J1B2/GPIO11 J2X/GPIO16 J2Y/GPIO17 J2B1/GPIO12 J2B2/GPIO13 LED1/GPIO60 LED2/GPIO61 GPIO20/P17 GPIO24/SYSOPT MIDI_IN/GPIO25 MIDI_OUT/GPIO26 CLOCKI CLOCKI32 AGND GND GND GND GND U10 LPC47M107
SIO0_PME# L_DRQ#0 LPCPD#
RXD1 TXD1 DTR1# DSR1# SYSOP/RTS1# CTS1# RI1# DCD1# GPIO52/IRRX/RXD2 GPIO53/IRTX/TXD2 GPIO57/DTR2# GPIO54/DSR2# GPIO55/RTS2# GPIO56/CTS2# GPIO50/RI2# GPIO51/DCD2# GP35/IRTX2 GP34/IRRX2
84 85 89 86 87 88 90 91 95 96 100 97 98 99 92 94 62 61 IRTX_IR IRRX_IR
SP1_RXD 21 SP1_TXD 21 SP1_DTR# 21 SP1_DSR# 21 SP1_RTS# 21 SP1_CTS# 21 SP1_RI# 21 SP1_DCD# 21 SP2_RXD 21 SP2_TXD 21 SP2_DTR# 21 SP2_DSR# 21 SP2_RTS# 21 SP2_CTS# 21 SP2_RI# 21 SP2_DCD# 21
15,18,20,29 SERIRQ 16,18,20,33 L_AD[0..3]
16,18,20,33 16
L_FRAME# SIO0_SMI#
IR PORT
V_5V0SB
27 PWM_BL 33 FAN1_SENSE 33 FAN2_PWM 33 FAN2_SENSE
C
V_5V0
CN5 LP_D[0..7] PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 STB# AFD# INIT# SLCTIN# ACK# ERR# SLCT BUSY PE 68 69 70 71 72 73 74 75 83 82 66 67 80 81 77 79 78 LP_D0 LP_D1 LP_D2 LP_D3 LP_D4 LP_D5 LP_D6 LP_D7 LP_D[0..7] 21 FB5 BLM21B601S V_IR
+ C304
1 3 5
2 4 6 SM06/SA XXX1 XXX2
KEY
21
SP1_SD#
C
R427 R428 R429 R430
15 A20GATE 15 KB_RST# 22 KB_CLK 22 KB_DAT 22 22 2KA 2KA MS_CLK MS_DAT
4u7/TC
GND
IRTX_IR LP_STB# 21 LP_AFD# 21 LP_INIT# 21 LP_SLIN# 21 LP_ACK# 21 LP_ERR# 21 LP_SLCT 21 LP_BUSY 2