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PRELIMINARY

Maestro-1TM AudioDrive® Solution Product Brief

DESCRIPTION
The Maestro-1TM PCI audio accelerator is part of ESS Technology's new generation of architecture that not only meets the demands of advanced PC audio applications, but also enables the integration of a complete multimedia subsystem on either a single adapter or motherboard. Maestro-1's functionality and interfaces are compliant with all major industry standards, including the Audio Subsystem Specification of PC97, Windows® 95 DirectSoundTM, Windows® Sound System® , AC'97 CODEC Interface, and PCI 2.1 Bus Specification. The dual audio-engine Maestro-1 architecture consists of a 64voice, pipelined, wavetable synthesizer and a proprietary programmable audio signal processor. Together they can simultaneously and efficiently handle multiple audio streams of different data types, high-quality music synthesis, and voice compression and decompression. The Maestro-1 provides a high-performance PCI interface, while retaining full compatibility to existing DOS games through hardware emulation. The PCI bus is required for PC audio hardware to smoothly reproduce high-fidelity audio from Internet, MIDI, wave, and conferencing sources. The PCI bus achieves high-performance functionality by enabling the transfer of multiple, independent data streams. PCI improves data transfer efficiency by at least 20 times over the ISA bus. This is crucial for low-latency audio applications, such as Internet interactive audio. Microsoft's DirectSound API is accelerated by digitally mixing up to 32 PCM streams of any frequency down to a single output stream of 48 kHz. Hardware acceleration frees the CPU to perform other tasks, such as video processing. The Maestro-1's Wave Processor (WP) provides high-quality wavetable synthesis cost-effectively by storing the downloadable table samples in system memory. With ESS's WaveCacheTM technology, the samples are retrieved using the PCI bus during playback. Each channel/stream has an independent pan, tremolo, vibrato and tone filter. The synthesizer also performs advanced audio effects such as reverb, chorus, flange, echo and 3-D spatial enhancement. The Maestro-1 achieves complete DOS game compatibility through three major schemes: PC/PCI DMA, Distributed DMA, and Transparent DMA. Transparent DMA requires no sideband signals and is compatible with all Pentium® and Pentium Pro® chipsets with no constraints. The Maestro-1 audio accelerator is available in an industrystandard 208-pin Plastic Quad Flat Package (PQFP).

FEATURES
W

DOS game compatibility

System Interface
W W

32-bit PCI Bus master, PCI 2.1 compliant < 0.5% PCI Bus Bandwidth for playing 16-bit/stereo/44.1KHz

Wavetable Synthesis
W W W W

64-channel 50 MHz pipelined Wave Processor 1-8 MB Wavetable Memory downloadable in either system memory or local ROM/DRAM/FlashROM Programmable pan, tremolo, vibrato, rate conversion and tone filtering per channel Programmable effects including reverb, chorus, flange, echo

DirectSound Acceleration
W W

Digital mixing up to 32 data streams Hardware sample rate convert to 48 KHz from any sample rate

3-D Sound
W W W

3-D positional audio under DirectXTM 5.0 Enhanced effects (reverb, chorus, echo, vibrato, etc.) AC-3 decode acceleration External DSP for hardware AC-3 decode Active Movie AC-3 filter acceleration option

Software Compatibility
W W W W W W

Sound BlasterTM Pro Ad LibTM Windows Sound System Windows95 DirectSound Microsoft® Active XTM

Hardware Interfaces
W W W W W W

MPU-401 interface with FIFO High-performance game port General-Purpose I/O port 8-Bit peripheral interface I2S digital audio Input Programmable audio CODEC interface: PT-101 Audio CODEC AC'97 CODEC Interface Other 16-bit CODECs

ESS Technology, Inc.

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PRELIMINARY

MAESTRO-1 PRODUCT BRIEF

PINOUT
ROMD10 ROMD9 ROMD8 GND VCC YAD7 YAD6 YAD5 YAD4 YAD3 YAD2 YAD1 YAD0 GND RASn ROMA23 ROMA22 ROMA21 ROMA20 ROMA19 ROMA18 ROMA17 ROMA16 GND VCC CASn ROMD7 ROMD6 ROMD5 ROMD4 ROMD3 GND ROMD2 ROMD1 ROMD0 SRAMOEn SRAMWEn GND VCC ROMA15 ROMA14 ROMA13 ROMA12 ROMA11 ROMA10 ROMA9 ROMA8 ROMOEn GND VCC ROMA7 ROMA6 ROMD11 ROMD12 ROMD13 ROMD14 ROMD15 FLASHWEn VCC OSCI OSCO GND MCLK GD7 GD6 GD5 GD4 GD3 GD2 GD1 GD0 VCC MBCLK0 GND MBCLK1 GND MBCLK2 GSDO/YRSTn/GPIO0 GSDI / YALE / GPIO1 PCGNTn/YCS0n/GPIO2 PCREQn/YCS1n/GPIO3 PCSINn/YCS2n GSDFS0/YINTn/GPIO4/I2SLR GSDFS1/YWRn/GPIO5/I2SDATA GSCLK/YRDn/GPIO6/I2SCLK IRQ5 IRQ7 HCLK VCC SCLK PCOUTn / GPIO7 SDFS0 SDI SDO IRQ9 IRQ10 TxD RxD GND C24 HRSTn HINTn HGNTn HREQn 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105

Maestro-1 208-Pin PQFP Package

PIN DESCRIPTION
O = Output - 24mA (PCI output) Ob = Output - 4mA Oc = Output - 24mA (PCI sustain output driver) Od = Output - 24mA Open drain Oe = Output - 8mA Of = Output - 16mA Og = Output - 24mA
Name HAD[31:0] HCBE[3:0]n HRSTn HPAR HCLK HFRAMEn HIRDYn HTRDYn HSTOPn HLOCKn HIDSEL HDEVSELn HREQn HGNTn HINTn HSERRn HCLKRUNn Number 1:4,7:10,14:21,38:45,49:56 11,24,35,48 205 34 192 25 26 27 29 31 12 28 208 207 206 33 32 I/O I/O I/O Ic I/O I Definition Multiplexed address and data lines Multiplexed command/byte enable Reset Parity PCI bus clock Host Interface PCI Bus Pins (51)

I/Oc Cycle frame I/Oc Initiator ready I/Oc Target ready I/Oc Stop transaction I/Oc Lock I O I Od Od ID select Request Grant Interrupt request System error I/Oc Device select

I/Oc Clock running

2

HAD31 HAD30 HAD29 HAD28 VCC GND HAD27 HAD26 HAD25 HAD24 HCBE3n HIDSEL GND HAD23 HAD22 HAD21 HAD20 HAD19 HAD18 HAD17 HAD16 VCC GND HCBE2n HFRAMEn HIRDYn HTRDYn HDEVSELn HSTOPn GND HLOCKn HCLKRUNn HSERRn HPAR HCBE1n VCC GND HAD15 HAD14 HAD13 HAD12 HAD11 HAD10 HAD9 HAD8 VCC GND HCBE0n HAD7 HAD6 HAD5 HAD4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

ROMA5 ROMA4 ROMA3 ROMA2 ROMA1 ROMA0 GND VCC SRAMD15 SRAMD14 SRAMD13 SRAMD12 SRAMD11 SRAMD10 SRAMD9 SRAMD8 SRAMA14 SRAMA13 SRAMA12 GND SRAMWEn0 SRAMOEn0 VCC SRAMWEn1 SRAMOEn1 SRAMA11 SRAMA10 SRAMA9 SRAMA8 SRAMA7 SRAMA6 SRAMA5 SRAMA4 SRAMA3 GND SRAMA2 SRAMA1 SRAMA0 SRAMD7 SRAMD6 SRAMD5 SRAMD4 SRAMD3 SRAMD2 SRAMD1 SRAMD0 GND VCC HAD0 HAD1 HAD2 HAD3

Oh = output with slew rate -12 mA I = Input - TTL Ib = Input - CMOS Schmitt trigger Ic = Input - TTL Schmitt trigger Id = Input - CMOS Schmitt trigger with internal pull-up Ie = Input - TTL with internal pull-up If = Input - TTL Schmitt trigger with internal pull-up

ESS Technology, Inc.

MAESTRO-1 PRODUCT BRIEF

PRELIMINARY

Name YAD[7:0] ROMA[23:0] RASn CASn SRAMWEn ROMOEn ROMD[15:0]/ RAMD[15:0] SRAMOEn FLASHWEn MCLK MBCLK[2:0] SCLK AC'97 CODEC Interface (4)

Number 151:144 142:134,117:110,106:99 142 131 120 109 161:154,130:126,124:122 121 162 167 181,179,177 194

I/O I/O O O O O O I/O O O I O

Definition 8-Bit peripheral data: YAD[7:0] Either ROM or DRAM access. ROM = ROMA[23:0], or DRAM = Reserved[23:12], DRAMA[11:0] DRAM/SRAM control. DRAM/SRAM control. DRAM/SRAM control. ROM output enable. Either ROM (ROMD[15:0]: ROM data), or DRAM/SRAM (RAMD[15:0]: RAM data) access. SRAM control. Flash ROM control. MPCI bus clock Buffered MPCI bus clocks

DRAM/SRAM/ROM Interfaces (58)

I/Oe Serial clock. Default is output. Pull SRAMA[1] low to set to the input. Must be less than 24.576 Mhz. Tentatively, this frequency is set at 12.5 Mhz (should be within the range of 10-15 Mhz). Data is transmitted after a rising edge of SCLK, and sampled on a falling edge of SCLK. Oe Serial data frame sync. New data frames are marked by a LO to HIGH transition on SDFS0 one serial clock period before the frame begins. The transition back from HI to LO may occur at any time provided the HI and LO times of SDFS0 are at least one SCLK period in duration each. Serial data in Serial data out ISA IRQ5 ISA IRQ7 ISA IRQ9 ISA IRQ10 MIDI transmit data MIDI receive data Game port data

SDFS0

196

SDI SDO IRQ Pins (4) IRQ5 IRQ7 IRQ9 IRQ10 MPU-401 Interface (2) TxD RxD Game Port Interface (8) GD[7:4] GD[3:0] Clocks (3) OSCI OSCO C24 SRAM Interface (35) SRAMA[14:11]

197 198 190 191 199 200 201 202 168:171 172:175 164 165 204 88:86,79

I Oe Og Og Og Og Of Ic Id

Ib/Oh Game port data I Ob Ob 49.152 MHz crystal input 49.152 MHz crystal output 24.576 MHz clock output. For CODEC clock source.

Ie/Oe SRAM address. SRAMA[14:11] is at input state only during the Reset period. Inputs are latched during reset to define Bit [15:13] and Bit [8] of 16-bit Subsystem ID at the offset 2Eh of PCI Config. Space. Ie/Oe SRAM address. SRAMA10 is at input state only during the Reset period. If NC (with internal pull-up): second CODEC is disabled. If 0: Enable second CODEC. Ie/Oe SRAM address. SRAMA[9:2] is at input state only during the Reset period. Inputs are latched during reset to define Bit [7:0] of 16-bit Subsystem ID at the offset 2Eh of PCI Config. Space. Ie/Oe SRAM address. SRAMA1 is at input state only during the Reset period. If NC (with internal pull-up): SCLK = Output. If 0: SCLK = Input. Ie/Oe SRAM address. SRAMA0 is at input state only during the Reset period. Pull this pin low to enable local DRAM interface. I/Ob SRAM data. Ie/Oe SRAM output enable. SRAMOEn[1:0] is at input state only during the Reset period. Inputs are latched during reset to define Bit [9] and Bit [11] of 16-bit Subsystem ID at the offset 2Eh of PCI Config. Space. Ie/Oe SRAM write enable. SRAMWEn[1:0] is at input state only during the Reset period. Inputs are latched during reset to define Bit [10] and Bit [12] of 16-bit Subsystem ID at the offset 2Eh of PCI Config. Space. Oe Oe Multipurpose pin. GSCLK, YRDn, GPIO6, or I2SCLK. When used as GSCLK = serial clock. Must be less than 24.576 Mhz. Data is transmitted after a rising edge of SCLK. Multipurpose pin. GSDFS0, YINTn, GPIO4, or I2SLR. When used as GSDFS0 = serial data frame sync 0. New data frames are marked by a LO to HIGH transition on SDFS0 one serial clock period before the frame begins. The transition back from HI to LO may occur at any time provided the HI and LO times of SDFS0 are at least one SCLK period in duration each. Multipurpose pin. GSDFS1, YWRn, GPIO5, or I2SDATA. When used as GSDFS1 = serial data frame sync 1. New data frames are marked by a LO to HIGH transition on SDFS1 one serial clock period before the frame begins. The transition back from HI to LO may occur at any time provided the HI and LO times of SDFS1 are at least one SCLK period in duration each. Multipurpose pin. GSDI, YALE, or GPIO1. When used as GSDI = serial data in. Multipurpose pin. GSDO, YRSTn, or GPIO0. When used as GSDO = serial data out.

SRAMA[10]

78

SRAMA[9:2]

77:71,69

SRAMA[1]

68

SRAMA[0] SRAMD[15:0] SRAMOEn[1:0]

67 96:89,66:59 80,83

SRAMWEn[1:0]

81,84

Second CODEC Interface (5) GSCLK * GSDFS0 * 189 187

GSDFS1 *

188

Oe

GSDI * GSDO *

183 182

Ie Oe

ESS Technology, Inc.

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PRELIMINARY

MAESTRO-1 PRODUCT BRIEF

Name PC/PCI Interface (4) PCGNTn * PCREQn * PCSINn * PCOUTn *

Number 184 185 186 195 182 183 184 185 186 187 188 189

I/O Ie Oe

Definition Multipurpose pin. PCGNTn, YCS0n, or GPIO2. When used as PCGNTn = PC/PCI grant. Multipurpose pin. PCREQn, YCS1n, or GPIO3. When used as PCREQn = PC/PCI request.

Ie/Oe Multipurpose pin. PCSINn, or YCS2n. When used as PCSINn = PC/PCI serial IRQ input. COMPAQ: serial IRQ input/output Oe Oe Oe Oe Oe Oe Ie Oe Oe Multipurpose pin. PCOUTn, or GPIO7. When used as PCOUTn = PC/PCI serial IRQ output. Multipurpose pin. GSDO, YRSTn, or GPIO0. When used as YRSTn = reset. A "low" on this pin forces both LAPD and LAPB devices into reset state. The minimum pulse length is 1.8 µs. Multipurpose pin. GSDI, YALE, or GPIO1. When used as YALE = address latch enable. A "high" on this pin indicates an address valid on the multiplexed address/data bus (AD7-0). Multipurpose pin. PCGNTn, YCS0n, or GPIO2. When used as YCS0n = chip select 0. A "low" on this line selects LAPD device for read/write operation. Multipurpose pin. PCREQn, YCS1n, or GPIO3. When used as YCS1n = chip select 1. A "low" on this line selects LAPB device for read/write operation. Multipurpose pin. PCSINn, or YCS2n. When used as YCS2n = chip select 2. A "low" on this line selects U interface device for read/write operation. Multipurpose pin. GSDFS0, YINTn, GPIO4, or I2SLR. When used as YINTn = interrupt. This pin is shared by both LAPD and LAPB devices. Multipurpose pin. GSDFS1, YWRn, GPIO5, or I2SDATA. When used as YWRn = write. Active-low. This signal indicates a write operation. It is common to both LAPD and LAPB devices Multipurpose pin. GSCLK, YRDn, GPIO6, or I2SCLK. When used as YRDn = read. Active-low. This signal indicates a read operation. It is common to both LAPD and LAPB devices.

Peripheral/ISDN Interface (8) YRSTn * YALE * YCS0n * YCS1n * YCS2n * YINTn * YWRn * YRDn * General-Purpose I/O Pins (7) GPIO0 * GPIO1 * GPIO2 * GPIO3 * GPIO4 * GPIO5 * GPIO6 * GPIO7 * I2S Interface (3) I2SLR * I2SDATA * I2SCLK * Power Pins (34) VCC GND * These pins share more than one function. Pwr +5 volts Pwr Ground 187 188 189 Ie Ie Ie Multipurpose pin. GSDFS0, YINTn, GPIO4, or I2SLR. When used as I2SLR = I 2S left right latch. Multipurpose pin. GSDFS1, YWRn, GPIO5, or I2SDATA. When used as I2SDATA = I2S data input pin. Multipurpose pin. GSCLK, YRDn, GPIO6, or I2SCLK. When used as I2SCLK = I2S clock. 182 183 184 185 187 188 189 195 Ie/Oe Multipurpose pin. GSDO, YRSTn, or GPIO0. When used as GPIO0 = GPIO0. Ie/Oe Multipurpose pin. GSDI, YALE, or GPIO1. When used as GPIO1 = GPIO1. Ie/Oe Multipurpose pin. PCGNTn, YCS0n, or GPIO2. When used as GPIO2 = GPIO2. Ie/Oe Multipurpose pin. PCREQn, YCS1n, or GPIO3. When used as GPIO3 = GPIO3. Ie/Oe Multipurpose pin. GSDFS0, YINTn, GPIO4, or I2SLR. When used as GPIO4 = GPIO4. Ie/Oe Multipurpose pin. GSDFS1, YWRn, GPIO5, or I2SDATA. When used as GPIO5 = GPIO5. Ie/Oe Multipurpose pin. GSCLK, YRDn, GPIO6, or I2SCLK. When used as GPIO6 = GPIO6. Ie/Oe Multipurpose pin. PCOUTn, or GPIO7. When used as GPIO7 = GPIO7.

DIGITAL CHARACTERISTICS
Symbol VIH1 VIH2 VIL VOH VOL Parameters Input high voltage: all digital inputs except Xtal[2:1] Input high voltage: Xtal[2:1] Input low voltage: all digital inputs Output high voltage Output low voltage Input leakage current Output leakage current -10 -10 Min 2.4 2.4 -0.3 2.4 0.4 10 10 Max Vdd+0.3 Vdd+0.3 0.8 Unit V V V V V µA µA

BLOCK DIAGRAM
General-Purpose I/O Port 64-Voice Wavetable Synthesizer High Performance Game Port DirectSound Accelerator CODEC/Mixer Interface

Maestro-1
MPU-401 I2 S Digital Audio Signal Processor

Media Ring

Peripheral Interface FM Synthesis

Sound Blaster

PCI Bus Interface

(P) U.S. Patent 4,214,125 and others, other patents pending. All specifications are subject to change without prior notice. AudioDrive® is a registered trademark of ESS Technology, Inc. All other trademarks are owned by their respective holders. Document Number: SAM0049A May 1997

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ESS Technology, Inc.