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APPLICATION NOTE
APPLICATION INFORMATION FOR TV SIGNAL PROCESSOR+µP+TXT+STEREO SOUND DECODER TDA110XXH/TDA120XXH AN10236-01
Release 4.0
Philips Semiconductors
E
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Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
Application Note AN10236-01
Abstract This report gives a description of the TDA110xxH/TDA120xxH together with application aspects.
Purchase of Philips I2C components conveys a license under the I2C patent to use the components in the I2C system, provided the system conforms to the I2C specifications defined by Philips.
© Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. 2
Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
Application Note AN10236-01
APPLICATION NOTE
Application information for TV signal processor & µP & Teletext / Closed Captioning decoder TDA110xxH/TDA120xxH AN10236-01
Author(s): D. Allerton E. Arnold L. Bakema P. Beurskens F. Bongers F. Bremer T. Bruton G. Folmer T. Geurts T. Hummelink J.B. Jones J. Scholten P. Schöning D. Siersema System & Application, Consumer Businesses Innovation Center Nijmegen, The Netherlands Keywords Embedded micro-controller, OSD, Teletext, Closed Captioning, Alignment free IF-PLL, Sound PLL, Stereo Sound Decoder, Nicam, RDS, Synchronisation H/V, Geometry on vertical and E-W Switches and filters, PAL/NTSC/SECAM decoder, Delay line, Combfilter, Continuous Cathode Calibration, Scavem, I2C Date: March 2005
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Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
CONTENTS
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Application Note AN10236-01
INTRODUCTION...................................................................................................................................... 11 CONFIGURATION ................................................................................................................................... 12 2.1 PINNING DIAGRAMS FOR VARIOUS VERSIONS........................................................................................ 12 2.2 QIP90................................................................................................................................................... 15 2.2.1 General............................................................................................................................................ 15 2.2.2 Features (differences of QIP90 with respect to QFP128)............................................................... 15 2.2.3 Sound specification and Dolby........................................................................................................ 16
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IF.................................................................................................................................................................. 17 3.1 VIF & SIF INPUT ................................................................................................................................. 17 3.2 AGC..................................................................................................................................................... 18 3.2.1 IFAGC............................................................................................................................................. 18 3.2.2 SIFAGC........................................................................................................................................... 20 3.2.3 SIF2 AGC........................................................................................................................................ 20 3.3 TUNER AGC OUTPUT ........................................................................................................................... 20 3.3.1 Tuner AGC ...................................................................................................................................... 20 3.3.2 Alignment Tuner AGC..................................................................................................................... 21 3.4 IF DEMODULATOR ................................................................................................................................ 22 3.5 IFPLL .................................................................................................................................................. 22 3.5.1 Loop filter........................................................................................................................................ 22 3.5.2 Calibration ...................................................................................................................................... 23 3.5.3 Gating.............................................................................................................................................. 23 3.6 IF VIDEO OUT / SELECTED VIDEO OUT / CVBS INPUT (IFVO / SVO /CVBSI) ..................................... 25 3.7 IF AMPLITUDE ..................................................................................................................................... 26 3.8 VIDEO MUTE:........................................................................................................................................ 26 3.9 GROUPDELAY ....................................................................................................................................... 27 3.10 ALIGNMENT IFPLL OFFSET .................................................................................................................. 27 3.11 INTERMODULATION .............................................................................................................................. 28 3.12 SEARCH TUNING ................................................................................................................................... 30 3.13 AFC ..................................................................................................................................................... 32 3.14 DIGITAL VIDEO BROADCAST TERRESTRIAL ......................................................................................... 32
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SOUND I/0 .................................................................................................................................................. 35 4.1 4.2 4.3 INPUTS.................................................................................................................................................. 35 OUTPUTS .............................................................................................................................................. 38 AUDIO GAIN ......................................................................................................................................... 39
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SOUND MONO .......................................................................................................................................... 41 5.1 SOUND CONFIGURATION ....................................................................................................................... 41 5.2 THE NARROW BAND PLL...................................................................................................................... 41 5.3 AUDIO MUTE ........................................................................................................................................ 42 5.4 BANDPASS FILTERS .............................................................................................................................. 43 5.5 OVERMODULATION .............................................................................................................................. 43 5.6 FREQUENCY RESPONSE ......................................................................................................................... 44 5.6.1 Demodulator decoupling capacitor................................................................................................. 44 5.6.2 De-emphasis capacitor.................................................................................................................... 44 5.7 AUTOMATIC VOLUME LEVELLING ....................................................................................................... 45 5.8 FM RADIO ............................................................................................................................................ 46 5.8.1 FM radio eco................................................................................................................................... 47 5.8.2 FM radio 10.7MHz.......................................................................................................................... 48 5.8.3 RDS ................................................................................................................................................. 50
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STEREO SOUND PROCESSING............................................................................................................ 51 6.1 6.2 SYSTEM DESCRIPTION FOR SOUND ........................................................................................................ 51 UOCIII DIGITAL SOUND PART .............................................................................................................. 51
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Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
Application Note AN10236-01
6.3 BLOCK DIAGRAM ................................................................................................................................. 52 6.4 IIC-BUS USER INTERFACE DESCRIPTION ................................................................................... 53 6.4.1 Introduction..................................................................................................................................... 53 6.4.2 Overview address space .................................................................................................................. 53 6.4.3 Power-up state ................................................................................................................................ 54 6.4.4 Overview Control Register Table.................................................................................................... 54 6.4.5 Slave receiver mode ........................................................................................................................ 55 6.4.6 Slave transmitter mode.................................................................................................................... 56 6.4.7 Control Register Table .................................................................................................................... 57 6.4.8 Refresh cycle ................................................................................................................................... 57 6.5 HARDWARE APPLICATION .................................................................................................................... 58 6.5.1 Power supply application per pin ................................................................................................... 58 6.5.2 Application example for the SDACs supply..................................................................................... 58 6.6 DIGITAL AUDIO INTERFACE I2S ........................................................................................................... 59 6.6.1 Digital audio interface application per pin..................................................................................... 59 6.6.2 General Description of the digital audio interface ......................................................................... 59 6.6.3 Possible Formats............................................................................................................................. 60 6.7 USE CASES ........................................................................................................................................... 61 6.7.1 B/G, D/K and I applications............................................................................................................ 62 6.7.2 NICAM L and AM applications....................................................................................................... 62 6.7.3 BTSC application ............................................................................................................................ 63 6.7.4 FM radio application ...................................................................................................................... 63 6.8 LEVELLING INSIDE THE UOCIII SOUND PATH ...................................................................................... 63 6.8.1 Hints for the overall level plan........................................................................................................ 64 6.9 UOCIII STEREO SOUND DEMODULATION AND DECODING .................................................................. 65 6.9.1 DDEP in short................................................................................................................................. 65 6.9.2 History and design considerations .................................................................................................. 67 6.10 DDEP BASICS AND USAGE ................................................................................................................... 68 6.10.1 DEMDEC hardware blocks ........................................................................................................ 68 6.10.2 Signal processing in DSP software............................................................................................. 69 6.10.3 The DDEP control register......................................................................................................... 70 6.10.4 NICAM configuration ................................................................................................................. 74 6.10.5 Automute function ....................................................................................................................... 75 6.10.6 Amplitude and noise threshold registers..................................................................................... 75 6.10.7 Status registers............................................................................................................................ 79 6.10.8 Using DDEP in a set design ....................................................................................................... 84 6.10.9 NICAM and DCXO control......................................................................................................... 87 6.11 DETAILS OF OPERATION ....................................................................................................................... 93 6.11.1 Search procedures (ASD mode).................................................................................................. 93 6.11.2 Using the SSS mode .................................................................................................................. 101 6.11.3 Automatic signal switching and routing ................................................................................... 102 6.11.4 Overmodulation Adaptation...................................................................................................... 103 6.11.5 Other details ............................................................................................................................. 103 6.12 REGISTER MAP AND ABBREVIATIONS ................................................................................................. 105 6.12.1 DEMDEC Register map............................................................................................................ 105 6.12.2 Terminology and Acronyms ...................................................................................................... 106 6.13 BASE BAND AUDIO PROCESSING INSIDE THE UOCIII ......................................................................... 107 6.14 FUNCTIONAL OVERVIEW .................................................................................................................... 107 6.15 SOUND MODES OF THE LOUDSPEAKER CHANNELS ............................................................................. 110 6.16 REMARKS TO FUNCTION CONTROL .................................................................................................... 112 6.16.1 AVL ........................................................................................................................................... 112 6.16.2 Virtual Dolby Surround ............................................................................................................ 112 6.16.3 SRS TruSurround ...................................................................................................................... 112 6.16.4 Noise Sequencer for DPL.......................................................................................................... 113 6.16.5 The Dolby Pro Logic Function (DPL) ...................................................................................... 114 6.16.6 Bass / Treble ............................................................................................................................. 115 6.16.7 Loudness ................................................................................................................................... 118 6.16.8 Extended Spatial Stereo (ESS) .................................................................................................. 119
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Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
Application Note AN10236-01
6.16.9 Bass Management ..................................................................................................................... 120 6.16.10 Equalizers ................................................................................................................................. 122 6.16.11 Volume and Trim ...................................................................................................................... 125 6.16.12 Beeper ....................................................................................................................................... 125 6.16.13 Mono Signal for Cancellation in the Voice Control IC ............................................................ 125 6.16.14 Audio Monitor........................................................................................................................... 125 6.16.15 Digital Output Crossbar ........................................................................................................... 125 6.16.16 Clip Management...................................................................................................................... 125 6.17 AUDIO FEATURE SPECIFICATION ............................................................................................... 128 6.17.1 Power On / Reset Specification................................................................................................. 128 6.17.2 Sound Feature Specification ..................................................................................................... 128 6.17.3 DVB/DBB Address/coefficient tables........................................................................................ 155 6.18 REFERENCES ...................................................................................................................................... 157 7 COLOUR .................................................................................................................................................. 158 7.1 BLOCK DIAGRAM ................................................................................................................................ 158 7.2 FUNCTIONAL DESCRIPTION OF THE COLOR DECODER.......................................................................... 159 7.2.1 Input processing ............................................................................................................................ 159 7.2.2 ACC............................................................................................................................................... 159 7.2.3 ACL ............................................................................................................................................... 160 7.2.4 Y/C detector................................................................................................................................... 161 7.2.5 Chroma Bandpass Filter ............................................................................................................... 161 7.2.6 SECAM Cloche Filter ................................................................................................................... 162 7.2.7 Colour decoder PAL/NTSC........................................................................................................... 163 7.2.8 SECAM decoder ............................................................................................................................ 165 7.2.9 Baseband delay line ...................................................................................................................... 165 7.2.10 ASM .......................................................................................................................................... 165 7.3 DCXO ALIGNMENT VIA COLOUR DECODER ...................................................................................... 169 7.4 I2C ..................................................................................................................................................... 172 7.4.1 Input bits ....................................................................................................................................... 172 7.4.2 Output bits..................................................................................................................................... 173 7.5 SOFTWARE ALGORITMS ..................................................................................................................... 174 8 CVBS I/O & FILTERS ............................................................................................................................ 175 8.1 INTRODUCTION ................................................................................................................................... 176 8.2 SWITCHES........................................................................................................................................... 176 8.2.1 Input Switching.............................................................................................................................. 176 8.2.2 Video Identification....................................................................................................................... 178 8.2.3 Output switch ................................................................................................................................ 178 8.2.4 SVO function ................................................................................................................................. 179 8.3 FILTERS .............................................................................................................................................. 179 8.3.1 Chromatrap................................................................................................................................... 179 8.3.2 Combfilter ..................................................................................................................................... 180 8.3.3 Y-delay .......................................................................................................................................... 184 8.4 I2C ..................................................................................................................................................... 185 8.4.1 Input bits ....................................................................................................................................... 185 8.4.2 Output bits..................................................................................................................................... 185 9 SYNCHRONISATION. ........................................................................................................................... 186 9.1.1 9.1.2 9.1.3 9.1.4 10 10.1.1 10.1.2 10.1.3 Block diagram. .............................................................................................................................. 186 Sync functional description. .......................................................................................................... 187 Software algorithms. ..................................................................................................................... 200 Miscellaneous................................................................................................................................ 201 Block diagram........................................................................................................................... 204 Geometry functional description............................................................................................... 204 Geometry alignment.................................................................................................................. 212
GEOMETRY........................................................................................................................................ 204
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Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
11
Application Note AN10236-01
RGB/YPRPB/YUV INPUT SWITCHING......................................................................................... 218 11.1 GENERAL............................................................................................................................................ 218 11.2 EXTERNAL RGB/YPRPB/YUV SOURCE INSERTION ........................................................................... 220 11.2.1 Input pins .................................................................................................................................. 220 11.2.2 How to insert external RGB/YPrPb/YUV signals ..................................................................... 221 11.2.3 Full insertion ............................................................................................................................ 223 11.2.4 Fast insertion ............................................................................................................................ 223 11.2.5 Fast insertion before or after the digital interface: FINM bit .................................................. 225 11.3 EXTRA CVBS OR YC INPUT ............................................................................................................... 225 11.4 OVERVIEW OF POSSIBLE RGB/YPRPB/YUV INPUT CONFIGURATIONS ............................................... 226 11.4.1 Mode A: 2 x RGB input (YUV2..0=000, YC=0)........................................................................ 227 11.4.2 Mode B: RGB input + YUV loop interface (YUV2..0=001)...................................................... 228 11.4.3 Mode C: RGB input + YUV input (YUV2..0=010, YC=0)........................................................ 229 11.4.4 Mode D: RGB input + YPrPb input (YUV2..0=011, YC=0)..................................................... 230 11.4.5 Mode E: 2 x YPrPb input (YUV2..0=100) ................................................................................ 231 11.4.6 Mode F: RGB and YPrPb input (YUV2..0=101, YC=0)........................................................... 232 11.4.7 Mode G: YPrPb input + YUV loop interface (YUV2..0=110, YC=0)...................................... 233 11.4.8 Mode H: YPrPb input + YUV input (YUV2..0=111) ............................................................... 234 11.4.9 Mode I: RGB input + CVBS or YC input (YUV2..0=000, YC=1)............................................ 235 11.4.10 Mode J: YPrPb input + CVBS or YC input (YUV2..0=111, YC=1)......................................... 236 11.5 YUV LOOP INTERFACE ....................................................................................................................... 237 11.5.1 Purpose ..................................................................................................................................... 237 11.5.2 Standard: YPrPb or YUV.......................................................................................................... 237 11.5.3 YPrPb/YUV output pins ............................................................................................................ 237 11.5.4 Compensating delay.................................................................................................................. 238 11.5.5 Fast RGB insertion before or after YUV loop interface............................................................ 238 11.5.6 Application with TDA9178 ....................................................................................................... 238 11.6 PICTURE-IN-PICTURE (PIP) APPLICATION ........................................................................................... 240 11.7 GENERAL PURPOSE IN & OUTPUT PORTS............................................................................................. 240 11.8 DIGITAL INTERFACE ........................................................................................................................... 240 11.8.1 Double window and linear/non-linear scaling ......................................................................... 240 11.8.2 RDS (Radio Data System)......................................................................................................... 244 11.9 VBI DATA SOURCE SWITCHING .......................................................................................................... 245 11.9.1 Introduction .............................................................................................................................. 245 11.9.2 Circuit description .................................................................................................................... 247 11.10 OSD/TEXT/CC ON YPRPBOUT....................................................................................................... 249 11.10.1 Introduction .............................................................................................................................. 249 11.10.2 Method 1: Insert OSD just before YPrPb output ...................................................................... 250 11.10.3 Method 2: Insert OSD directly after YPrPb output .................................................................. 250
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YUV PROCESSING............................................................................................................................ 251 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 12.13 INTRODUCTION ................................................................................................................................... 251 PEAKING............................................................................................................................................. 252 BLACK STRETCH ................................................................................................................................. 255 WHITE STRETCH ................................................................................................................................. 258 GAMMA .............................................................................................................................................. 259 LUMA DEPENDENT BRIGHTNESS REDUCTION (DC TRANSFER RATIO OR TFR) .................................... 259 HISTOGRAM FUNCTION (COMBINATION OF FEATURES) ....................................................................... 260 BLACK LEVEL OFFSET CONTROL ......................................................................................................... 260 TINT CONTROL ................................................................................................................................... 260 DYNAMIC SKIN TONE CONTROL...................................................................................................... 261 SATURATION .................................................................................................................................. 262 COLOUR DIFFERENCE MATRIX ........................................................................................................ 262 SCAVEM ...................................................................................................................................... 263
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RGB PROCESSING............................................................................................................................ 270 13.1 FUNCTIONAL DESCRIPTION RGB PROCESSING ................................................................................... 270 13.1.1 General ..................................................................................................................................... 270
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Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
Application Note AN10236-01
13.1.2 Blue stretch ............................................................................................................................... 270 13.1.3 Contrast multiplier.................................................................................................................... 271 13.1.4 Beam current limiter (BCL) ...................................................................................................... 271 13.1.5 Peak white limiter ..................................................................................................................... 275 13.1.6 Soft clipper................................................................................................................................ 276 13.1.7 Brightness control..................................................................................................................... 276 13.1.8 OSD/teletext/CC insertion ........................................................................................................ 276 13.1.9 Black level offset adjustment..................................................................................................... 276 13.1.10 White point adjustment ............................................................................................................. 277 13.1.11 Cathode drive............................................................................................................................ 277 13.1.12 RGB outputs.............................................................................................................................. 278 13.2 CCC LOOP INTRODUCTION (CCC = CONTINUOUS CATHODE CALIBRATION) ...................................... 279 13.2.1 Basic offset and gain loop operation ........................................................................................ 279 13.2.2 Implementation in UOC-III....................................................................................................... 280 13.2.3 Current feedback circuit ........................................................................................................... 280 13.3 CCC OFFSET LOOP ............................................................................................................................. 281 13.3.1 Purpose ..................................................................................................................................... 281 13.3.2 Operating range........................................................................................................................ 281 13.3.3 Black current failure indication (BCF)..................................................................................... 282 13.3.4 How to increase the black level at UOC outputs (for tubes with high cut-off voltages) ........... 283 13.3.5 How to decrease the black level at UOC outputs ..................................................................... 284 13.3.6 Application of discrete RGB amplifiers .................................................................................... 284 13.4 CCC GAIN LOOP ................................................................................................................................. 285 13.4.1 Purpose ..................................................................................................................................... 285 13.4.2 How to divide the gain over the different controls.................................................................... 291 13.4.3 Application of discrete RGB amplifiers .................................................................................... 291 13.5 START-UP PROCEDURE CCC LOOP ..................................................................................................... 292 13.6 FOUR WAYS TO OPERATE THE GAIN LOOP ........................................................................................... 296 13.7 CRT DISCHARGE ................................................................................................................................ 300 13.8 ADJUSTMENTS .................................................................................................................................... 302 13.8.1 Adjustment Vg2 ......................................................................................................................... 302 13.8.2 Determining the preset gain settings ........................................................................................ 307 13.8.3 White balance adjustment ......................................................................................................... 308 14 POWER MANAGEMENT ................................................................................................................. 309 14.1 POWER SUPPLY INPUTS ....................................................................................................................... 309 14.2 POWER MODES ................................................................................................................................... 310 14.3 POWER & PROTECTION RELATED BITS ................................................................................................ 310 14.4 +3.3V SUPPLY PROTECTION PROCEDURES .......................................................................................... 311 14.5 +5V SUPPLY PROTECTION PROCEDURES (+5V FROM MAIN SUPPLY)................................................... 311 14.6 +5V SUPPLY PROTECTION PROCEDURES (+5V FROM LOT) ................................................................ 312 14.7 CLOCK STRATEGY .............................................................................................................................. 313 14.7.1 Control of peripherals clocks.................................................................................................... 314 14.7.2 Preferred start-up sequence...................................................................................................... 315 14.8 LOADING OF VERSIONING DATA ......................................................................................................... 316 14.9 RELATION WITH THE SLEEP MODE CONTROLLER ................................................................................ 317 14.9.1 Introduction .............................................................................................................................. 317 14.9.2 Relation to bits in the CLK_CONFIG SFR register.................................................................. 318 14.9.3 What to do when leaving standby mode.................................................................................... 318 15 SOFTWARE ADC (SWADC)............................................................................................................. 320 15.1 GENERAL............................................................................................................................................ 320 15.2 PORT CONNECTION ........................................................................................................................... 320 15.3 SWADC INPUT VOLTAGE .................................................................................................................. 321 15.3.1 SWADC Input voltage for the ES7.2D ...................................................................................... 321 15.3.2 SWADC Input voltage for the ES10.3B..................................................................................... 322 15.4 LOCAL KEYBOARD FOR ES7.2D ......................................................................................................... 323 15.5 LOCAL KEYBOARD FOR ES10.3B ....................................................................................................... 325
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Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
16
Application Note AN10236-01
LCD APPLICATION .......................................................................................................................... 328 16.1 INTRODUCTION ................................................................................................................................... 328 16.2 I2C BIT SETTINGS FOR LCD APPLICATION .......................................................................................... 328 16.2.1 Hardware for LCD application ................................................................................................ 329
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SOFTWARE......................................................................................................................................... 332 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9 17.10 INTRO ................................................................................................................................................. 332 GTV................................................................................................................................................... 332 WIC32 ............................................................................................................................................... 333 WISP ................................................................................................................................................. 333 PROMT ............................................................................................................................................. 333 DDS ................................................................................................................................................... 333 WORKFLOW ....................................................................................................................................... 334 USER MANUALS ................................................................................................................................. 334 SUPPORT............................................................................................................................................. 334 GLOSSARY ..................................................................................................................................... 335
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PCB LAYOUT RECOMMENDATIONS.......................................................................................... 336 18.1 DESIGN PHILOSOPHY .......................................................................................................................... 336 18.2 DESIGN FLOW ..................................................................................................................................... 336 18.3 THE GUARD RING APPROACH ............................................................................................................. 337 18.4 UOC III SPECIFIC RULES: STEP BY STEP ............................................................................................ 340 18.4.1 Create one reference ground plane .......................................................................................... 340 18.4.2 Power supply ............................................................................................................................ 341 18.4.3 Short ground for IF-PLL loop filter.......................................................................................... 341 18.4.4 Bandgap and SECAM-PLL decoupling .................................................................................... 343 18.4.5 Digital decoupling .................................................................................................................... 344 18.4.6 One connection of reference ground to guard ring................................................................... 345 18.4.7 CRT-panel ground to Guard ring ............................................................................................. 346 18.4.8 Phi-1 and phi-2 loop grounding ............................................................................................... 347 18.4.9 Vertical oscillator reference components ................................................................................. 348 18.4.10 Vertical drive lines.................................................................................................................... 349 18.4.11 SAW filters and IF leads ........................................................................................................... 350 18.4.12 IF Path ...................................................................................................................................... 352 18.4.13 Asymmetrical tuners ................................................................................................................. 353 18.4.14 SAW filter Switch ...................................................................................................................... 354 18.4.15 Careful supply decoupling ........................................................................................................ 355 18.5 LAY-OUT RULES FOR PCB'S WITH 1, 2 OR 4 LAYERS.......................................................................... 356 18.5.1 Ground structure Single Layer Board ...................................................................................... 356 18.5.2 Ground structure Bi-Layer board ............................................................................................. 357 18.5.3 Ground and Power structure on a 4 layer board...................................................................... 358 18.6 SUMMARY OF GROUNDING: ................................................................................................................ 359 18.7 CONCLUSION ...................................................................................................................................... 359
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REFERENCE APPLICATION .......................................................................................................... 360 19.1 INTRODUCTION ................................................................................................................................... 360 19.2 QFP128 REFERENCE APPLICATION .................................................................................................... 360 19.2.1 QFP128Circuit Diagram .......................................................................................................... 360 19.2.2 QFP128Layout ......................................................................................................................... 360 19.3 QIP90 REFERENCE APPLICATION ....................................................................................................... 360 19.3.1 QIP90Circuit Diagram ............................................................................................................. 360 19.3.2 QIP90Layout............................................................................................................................. 360 19.4 GTV REFERENCE APPLICATION ......................................................................................................... 360 19.4.1 QFP128..................................................................................................................................... 360 19.4.2 QIP90........................................................................................................................................ 360 19.4.3 EurAsia ..................................................................................................................................... 360 19.4.4 LatAm........................................................................................................................................ 360
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Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
20 20.1 20.2 20.3 20.4 20.5 20.6 21
Application Note AN10236-01
UNUSED PINS ..................................................................................................................................... 361 IF ....................................................................................................................................................... 361 SOUND................................................................................................................................................ 361 RGB/YPRPB/YUV INPUT SWITCHING ............................................................................................... 361 YUV PROCESSING .............................................................................................................................. 361 RGB PROCESSING .............................................................................................................................. 362 CHROMA ............................................................................................................................................ 362 BLOCK DIAGRAMS.......................................................................................................................... 363
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Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
1 INTRODUCTION
Application Note AN10236-01
This manual gives hardware, software and system application information for the UOC-III "Hercules" television IC. This IC integrates micro-, video-, sound-processing and Flash-ROM into a single QFP128 encapsulation. It includes an integrated audio DSP offering stereo decoding for all terrestrial stereo standards. Audio processing includes Dolby Pro-Logic, Virtual Dolby and many other features to enhance the TV sound. The "truly-global" TV capabilities makes it possible to cover several 1fH (50/60 Hz) market areas with less chassis designs. The QFP128 package allows a single layer PCB technology to be used, while the external component count for minimum up to maximum featured IC-versions stays low. Since software is a substantial part of the total design effort, the on-board Flash-ROM allows InSystem-(re-)Programming. Besides detailed technical information, this manual also describes basic algorithms of how to drive functions.
Embedded software runs on an enhanced 80c51-micro controller, to drive: - TV-control, - OSD, Closed Captioning, 10p-Teletext, RDS and OSD, - Stereo decoding/featuring via a convenient command interface to firmware, running on the internal audio DSP
The video-processor includes: - Extensive audio/video switching (CVBS, Y/C, YUV, RGBF, DVD), - IF for Video, sound and FM-radio (QSS or Inter Carrier), - Sync and geometry processing for CRT (also usable for LCD) - Complete colour decoding (PAL 4.4/3.6, NTSC 4.4/3.6, PAL 60Hz, SECAM, SECAM 60Hz), - RGB generation and processing of signals.
Note: This Application Note is common to all the version of the Hercules IC. There may be options presented in this book, which may not be available to the version you may be using. Please refer to the specification for options that are available for your version.
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Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
2 2.1 CONFIGURATION Pinning diagrams for various versions
VDDP(3.3V) VDDC1(1.8) P2.5/PWM4 P2.4/PWM3 P2.3/PWM2 P2.2/PWM1 P2.1/PWM0 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 P2.0/PWM DECV1V8
Application Note AN10236-01
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n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. XTALIN XTALOUT VSSA1 VGUARD/SWIO DECDIG VP1 PH2LF PH1LF GND1 SECPLL DECBG AVL/EWD VDRB VDRA VIFIN1 VIFIN2 VSC IREF GNDIF DVBIN1/SIFIN1 DVBIN2/SIFIN2 AGCOUT EHTO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
o
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INT0/P0.5
P1.2/INT2
P1.0/INT1
P1.7/SDA
P1.6/SCL
VSSC1/P
P1.4/RX
P1.5/TX
P1.3/T1
P1.1/T0
P0.0
P0.1
P0.2
P0.3
P0.4
n.c.
n.c.
n.c.
n.c.
VDDadc(1.8) VSSadc n.c. n.c. n.c. n.c. n.c. n.c. VDDA1(3.3V) BO GO RO BLKIN BCLIN VP3 GND3 B/Pb-3 G/Y-3 R/Pr-3 INSSW3 VOUT(SWO1) UOUT(INSW-2) YOUT YSYNC YIN(G/Y-2/CVBS/Y-X) UIN(B/Pb-2) VIN(R/Pr-2/C-X) VDDcomb VSScomb HOUT FBISO/CSY SVM
TDA 1100x/01x/02x H
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n.c.
n.c.
n.c.
n.c.
DVBO/IFVO/FMRO
DVBO/FMRO
GND2
VP2
n.c.
CVBS4/Y4
CVBS2/Y2
AMOUT/QSSO/AUDEEM
SIFAGC/DVBAGC
AVL/SWO/SSIF/REFIN/ REFOUT
DECSDEM
AUDIOIN5
AUDIOIN2
SVO/IFOUT/CVBSI
AUDIOIN3
AUDIOIN4
CVBS3/Y3
VCC8V
PLLIF
C2/C3
n.c.
C4
Fig2. Pin configuration of TDA 1100x/01x/02x H [Mono versions]
Figure 1: Pin configuration of TDA 1100x/01x/02x H (Mono versions)
12
AUDOUT/AMOUT
CVBSO/PIP
64
Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
Application Note AN10236-01
P0.3/I2SCLK
P0.1/I2SDO1
P0.2/I2SDO2
VDDP(3.3V)
VDDC1(1.8)
P2.5/PWM4
P2.4/PWM3
P2.3/PWM2
P2.2/PWM1
P2.1/PWM0
P0.0/I2SDI1
P0.4/I2SWS
P3.3/ADC3
P3.2/ADC2
P3.1/ADC1
P3.0/ADC0
P2.0/PWM
DECV1V8
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
VSSP2 VSSC4 VDDC4 VDDA3(3.3V) VREF_POS_LSL VREF_NEG_LSL+LSR VREF_POS_LSR+HPL VREF_NEG_HPL+HPR VREF_POS_HPR XTALIN XTALOUT VSSA1 VGUARD/SWIO DECDIG VP1 PH2LF PH1LF GND1 SECPLL DECBG AVL/EWD VDRB VDRA VIFIN1 VIFIN2 VSC IREF GNDIF DVBIN1/SIFIN1 DVBIN2/SIFIN2 AGCOUT EHTO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
o
97 96 95 94 93 92 91 90 89 88 87 86 85 84 83
INT0/P0.5
P1.2/INT2
P1.0/INT1
P1.7/SDA
P1.6/SCL
VSSC1/P
P1.4/RX
P1.5/TX
VDDC3
VDDC2
P1.3/T1
P1.1/T0
VSSC3
VSSC2
VDDadc(1.8) VSSadc VDDA2(3.3V) VDDA(1.8V) GNDA VREFAD VREFAD_POS VREFAD_NEG VDDA1(3.3V) BO GO RO BLKIN BCLIN VP3 GND3 B/Pb-3 G/Y-3 R/Pr-3 INSSW3 VOUT(SWO1) UOUT(INSW-2) YOUT YSYNC YIN(G/Y-2/CVBS/Y-X) UIN(B/Pb-2) VIN(R/Pr-2/C-X) VDDcomb VSScomb HOUT FBISO/CSY SVM
TDA 1200x/01x/02x/03x H
82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63 AUDOUTHPR
AMOUT/QSSO/AUDEEM
DECSDEM
DVBO/IFVO/FMRO
DVBO/FMRO
SIFAGC/DVBAGC
VCC8V
AUDIOOUTSR
AVL/SWO/SSIF/REFIN/ REFOUT
AUDOUTLSR
AUDIOIN5R
AUDIOIN4R
AUDIOIN2R
AUDIOIN3R
GND2
VP2
C4
CVBS4/Y4
CVBS2/Y2
CVBS3/Y3
PLLIF
C2/C3
AUDIOOUTSL
Figure Pin configuration TDATDA1200x/01x/02x/03x H 2: Pin configuration of of 1200x/01x/02x/03x H (Full stereo versions)
[Full stereo versions]
SVO/IFOUT/CVBSI
13
AUDOUTHPL
AUDIOIN5L
AUDIOIN4L
AUDIOIN2L
AUDIOIN3L
AUDOUTLSL
CVBO/PIP
AGC2SIF
64
Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
Application Note AN10236-01
VDDP(3.3V)
VDDC1(1.8)
P2.5/PWM4
P2.4/PWM3
P2.3/PWM2
P2.2/PWM1
P2.1/PWM0
P3.3/ADC3
P3.2/ADC2
P3.1/ADC1
P3.0/ADC0
P2.0/PWM
DECV1V8
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. XTALIN XTALOUT VSSA1 VGUARD/SWIO DECDIG VP1 PH2LF PH1LF GND1 SECPLL DECBG AVL/EWD VDRB VDRA VIFIN1 VIFIN2 VSC IREF GNDIF DVBIN1/SIFIN1 DVBIN2/SIFIN2 AGCOUT EHTO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
97 96 95 94 93 92 91 90 89 88 87 86 85 84 83
INT0/P0.5
P1.2/INT2
P1.0/INT1
P1.7/SDA
P1.6/SCL
VSSC1/P
P1.4/RX
P1.5/TX
P1.3/T1
P1.1/T0
P0.0
P0.1
P0.2
P0.3
P0.4
n.c.
n.c.
n.c.
n.c.
VDDadc(1.8) VSSadc n.c. n.c. n.c. n.c. n.c. n.c. VDDA1(3.3V) BO GO RO BLKIN BCLIN VP3 GND3 B/Pb-3 G/Y-3 R/Pr-3 INSSW3 VOUT(SWO1) UOUT(INSW-2) YOUT YSYNC YIN(G/Y-2/CVBS/Y-X) UIN(B/Pb-2) VIN(R/Pr-2/C-X) VDDcomb VSScomb HOUT FBISO/CSY SVM
TDA 1205x/6X/7X H
82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AUDIOIN4R
AUDIOIN5R
AUDIOIN2R
AUDIOIN3R
SIFAGC/DVBAGC
AUDIOOUTSR
AMOUT/QSSO/AUDEEM
AVL/SWO/SSIF/REFIN/ REFOUT
DVBO/IFVO/FMRO
SVO/IFOUT/CVBSI
Figure 3: Pin configuration of TDA 1205x/6x/7x H (AV Stereo versions)
Pin configuration of TDA 1205x/6x/7x H [AV Stereo versions]
AUDIOOUTSL
14
AUDOUTLSR
DVBO/FMRO
AUDIOIN3L
AUDIOIN4L
AUDIOIN2L
AUDIOIN5L
AUDOUTLSL
CVBSO/PIP
PLLIF
n.c.
n.c.
DECSDEM
VCC8V
GND2
CVBS4/Y4
CVBS2/Y2
CVBS3/Y3
C2/C3
VP2
n.c.
C4
Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
2.2 2.2.1 2.2.2 QIP90 General Features (differences of QIP90 with respect to QFP128)
Application Note AN10236-01
Features Analogue Video Processing (all versions) · DVB/VSB IF circuit for preprocessing of digital TV signals with single ended output only.
·
Video switch with 2 in stead of 3 external CVBS inputs. All CVBS inputs can be used as Y-input for Y/C signals. However, only 1 in stead of 2 Y/C sources can be selected because the circuit has 1 chroma input. It is not possible to add an additional CVBS(Y)/C input (CVBS/YX and CX) when the YUV interface and the RGB/YPRPB input are not needed as there is no YUV interface. Additional CVBSx input available only in AV+ version. YUV interface not available.
·
Features Analogue Video Processing (stereo versions) · The low-pass filtered `mixed down' I signal is available via a single ended output stage only, not via a balanced output stage. Features Sound Demodulation (all versions) Audio Interfaces and switching (stereo versions with Audio DSP) · Audio switch circuit with 3 instead of 4 stereo inputs, a stereo output for SCART/CINCH, 1 stereo output for HEADPHONE. For AV+ version also 1 mono input available. The headphone channel has an analogue volume control circuit for the L and R channel. Finally 1 stereo SPEAKER output with digital controls. · No digital audio input interface (stereo I2S input interface) · No digital audio output interface (stereo I2S output interface) · Un-used audio inputs can be used as IO/PWM. Audio interfaces and switching (AV stereo versions without Audio DSP) · Audio switch circuit with 3 in stead of 4 stereo inputs, a stereo output for SCART/CINCH and a stereo SPEAKER output with analogue volume control. · Audio switch circuit with 3 in stead of 4 external audio (mono) inputs and a volume controlled output · AVL circuit FM radio · Full stereo/AV versions: - 10.7MHz mono/stereo available - FM radio eco mode mono/stereo available - RDS available · Mono versions - 10.7MHz mono available - FM radio eco mode mono available µ-Controller 15
Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
· · 2.2.3
Application Note AN10236-01
Not 24 but 12 general-purpose I/O pins Not 5 but 1 PWM (6-bits) outputs for analogue control functions Sound specification and Dolby
Input level (Vrms) Supply (V) 1.3 5 1.4 8 Audio3, 4 0.65 5 0.7 8 Table 1: Allowed specified audio input level Note: limited input level for Audio 3,4 due to shared pin function. Audio input and uproc I/O pins UOCIII QIP90 package is not Dolby pro logic compliant due to missing I2S outputs. VDS license is pending.
Audio inputs Audio2
16
Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
Application Note AN10236-01
3
IF
3.1 VIF & SIF input The Video IF input (pin VIFIN1, VIFIN2) and the Sound IF input (pin SIFIN1, SIFIN2) have these characteristics: - Frequency range is 32-60MHz - Impedance is 2k in parallel with 3pF. This matches the required load for commonly used SAW-filters. DC coupling is allowed, thus no series capacitors between SAW-filter and VIF & SIF inputs. For optimal IF& SIF performance (even for asymmetric tuners) it is advised to: · Make the signal path from tuner to the VIF-input pins as short and symmetrical as possible. · Make sure that the supply line of the used pre-amplifier is clean. · Supply ripple will be AM demodulated. · To prevent overloading these inputs, check: Tuner AGC alignment Type of SAW-filter The table below gives an example of possible SAW-filters: Table 2: Epcos SAW-filter combinations Type Mode Standard K2955M Intercarrier B/G, D/K K2960M Intercarrier B/G, D/K K2962M Intercarrier B/G G1985M Intercarrier B/G M1971M Intercarrier M/N M1865D Intercarrier M/N K3953M QSS - Video B/G, D/K, L/L' K9356M QSS - Sound B/G, I, D/K/L or L'NICAM G3962M QSS - Video B/G G9353M QSS Sound B/G-Nicam K9354D QSS Sound B/G, I, D/K, L X7251D DVB-T X6876M FM eco radio FM radioSXFM eco radio FM radio 7262BKB -VBOS Remarks (soundshelf and IF frequency) -20dB, IF=38.9 -14dB, IF=38.9 -15dB, IF=38.9 -14dB, IF=38.9 -14dB, IF=45.75, for FCC EIA/IS-31 -13dB, IF=45.75, for FCC EIA/IS-31, SIP5D Double Nyquist Slope (38.9 and 33.9) Pin 1= L', pin 2= B/G, I, D/K, L This SAW-filter needs ASYM tuner! IF=38.9 Single bandpass Broad single bandpass, SIP5D Switch able, SIP5D Centre freq: 37.5 MHz Centre freq: 37.5 MHz Supplier: Murata
Quasi Split Sound (QSS) gives better sound performance and is obligatory for stereo sound applications. This is due to the extra selectivity and lower soundcarrier suppression generated by the use of an additional SIF SAW-filter. See example below.
17
Philips Semiconductors
Release 4.0 March 2005
TDA110xxH/TDA120xxH TV-processor + µP with Teletext
-10dB -6dB VIDE O SOUND K2960M SAW PC SC -6dB PC SC -14dB -6dB -24dB
Application Note AN10236-01
PC/SC ratio : 18dB
-10dB
VIDE O K3953M SAW
-6dB
-10dB PC/SC ratio : 4dB
-0dB PC SC SOUND G9353M SAW PC SC
Figure 4: SAW-filter losses Conclusion: Using QSS, the soundcarrier level is 14dB higher compared to an intercarrier application that uses a SAW-filter with e.g. 14dB soundshelf. 3.2 AGC
3.2.1 IFAGC The IFAGC time constant is automatically adapted for positive and negative modulation. For negative modulation the IFAGC time constant is a factor 10 faster. The AGC speed can be adjusted with AGC1, 0 for: Table 3: AGC speed settings AGC1, 0 AGC Function speed 00 0.7 x norm Slow AGC action, reserved if required in the field 01 Norm Standard recommended setting, optimal for both positive and negative modulation 10 3 x norm Faster AGC for negative modulation as to improve airplane flutter performance 11 6 x norm Fastest AGC for negative modulation as to improve airplane flutter performance When IFAGC is set at maximum speed, it can get stuck when sync fails. SW can solve this by checking the IVWF status bit and reduce IFAGC speed when IVWF = 0. Optimal IF performance is achieved with gating signals derived from the horizontal oscillator. They become automatically active once the coincidence detector SL=1. Negative modulation The IC uses a top sync AGC. Positive modulation Depending on input selection and s