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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI Video-Controller-Text-IFAudio IC Family
Edition 12.12.2003
6251-573-1AI
VCT 49xyI, VCT 48xyI
Video-Controller-Text-IF-Audio IC Family
Contents Page Section Title
ADVANCE INFORMATION
Volume 1: General Description
1-4 1-4 1-6 1-7 1-10 1-10 1-10 1-10 1-10 1-10 1-10 1-11 1-12 1-12 1-14 1-19 1-19 1-19 1-19 1-20 1-20 1-21 1-22 1-24 1-24 1-24 1-25 1-25 1-26 1-28 1-28 1-30 1-30 1-31 1-31 1-32 1-33 1-33 1-33 1-34 1-34 1-34 1-34 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 3. 4. 4.1. 4.2. 4.3. 4.3.1. 4.3.2. 4.3.3. 4.3.4. 4.3.5. 4.3.6. 4.4. 4.5. 4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.4. 4.6.4.1. 4.6.4.2. 4.6.4.3. 4.6.4.4. 4.6.4.5. 4.6.4.6. Introduction Features Chip Architecture System Application Functional Description VCTI DRX MSP VSP DDP TVT Control Interface Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Supply Pins IF Pins Audio Pins Video Pins CRT Pins Controller Pins Pin Configuration Pin Circuits IF Pins Audio Pins Video Pins CRT Pins Controller Pins Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions General Recommended Operating Conditions Recommended Tuner Characteristics Recommended Crystal Characteristics Analog Input and Output Recommendations Characteristics Package Characteristics Standby Power Consumption Normal Power Consumption Leakage Current Test Input Reset Input/Output
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Video-Controller-Text-IF-Audio IC Family
Contents, continued Page 1-35 1-35 1-36 1-37 1-37 1-39 1-40 1-44 1-45 1-45 1-46 1-46 1-46 1-47 1-47 1-47 1-48 1-49 1-49 1-50 1-52 1-53 1-53 1-54 1-56 1-64 Section 4.6.4.7. 4.6.4.8. 4.6.4.9. 4.6.4.10. 4.6.4.11. 4.6.4.11.1. 4.6.4.11.2. 4.6.4.12. 4.6.4.13. 4.6.4.14. 4.6.4.15. 4.6.4.16. 4.6.4.17. 4.6.4.18. 4.6.4.19. 4.6.4.20. 4.6.4.21. 4.6.4.22. 4.6.4.23. 4.6.4.24. 4.6.4.25. 4.6.4.26. 4.6.4.27. 4.6.4.28. 5. 6. Title I2C Bus Interface IF Input Sound IF Output Tuner AGC Output Analog Audio Inputs and Outputs Analog Audio Performance Sound Standard Dependent Characteristics Analog Video Inputs Analog Video Outputs Horizontal Flyback Input Horizontal Drive Output Dynamic Focus Output Protection Inputs Vertical and East/West D/A Converter Output East/West PWM Output Sense A/D Converter Input Analog RGB and FB Inputs D/A Converter Reference Scan Velocity Modulation Output Analog RGB Outputs, D/A Converters CADC Input Port I/O Ports Memory Interface Memory Interface Timing Application Data Sheet History
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Contents, continued Page Section Title
ADVANCE INFORMATION
Volume 2: DRX - Analog TV IF- Demodulator
2-3 2-3 2-3 2-4 2-4 2-4 2-4 2-5 2-5 2-5 2-5 2-6 2-6 2-6 2-7 2-7 2-7 2-7 2-7 2-8 2-8 2-8 2-8 2-8 2-8 2-9 2-10 2-10 2-10 2-11 2-11 2-11 2-12 2-12 2-12 2-13 2-13 2-13 2-13 2-13 2-14 2-14 2-15 1. 1.1. 1.2. 1.3. 1.4. 1.4.1. 1.4.2. 1.4.3. 1.4.4. 1.4.5. 1.5. 1.6. 1.6.1. 1.6.2. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.8. 2.9. 2.10. 2.11. 2.12. 2.12.1. 2.12.2. 2.12.3. 2.12.4. 2.12.5. 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.3.1. 3.1.3.2. 3.1.3.3. 3.2. 3.3. 3.4. Introduction Chip Architecture Features Overview Analog TV Application SAW Filter Processing Overview Initialization for Analog TV Multistandard Configuration for B/G, L, I, D/K and M/N Multistandard Configuration for L' FM Radio Using DRX with an IF frequency other than 38.9 MHz I2C settings SAW filter considerations Functional Description Input Amplifier with TOP Setting Down Mixer Synthesizer ADC Carrier Recovery Channel Filtering and Audio/Video Splitting Video and Tuner AGC Group Delay Equalizing Peaking Video Output SIF AGC SIF Output Standard Specific Filter Curves Standard B Standard G Standard D/K, I, L/L' Standard M/N Standard FM Control Interface I2C Bus Interface Device and Subaddresses Protocol Description Proposals for General DRX I2C Telegrams Symbols Write Telegrams Read Telegrams I2C Register Block Index I2C Register Index I2C Register Subaddress Index
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Video-Controller-Text-IF-Audio IC Family
Contents, continued Page 2-16 2-20 Section 3.5. 4. Title I2C Register Description Data Sheet History
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Contents, continued Page Section Title
ADVANCE INFORMATION
Volume 3: Multistandard Sound Processor
3-4 3-4 3-5 3-6 3-7 3-8 3-8 3-8 3-8 3-8 3-9 3-9 3-10 3-10 3-11 3-11 3-11 3-11 3-11 3-11 3-11 3-12 3-12 3-12 3-12 3-12 3-13 3-13 3-13 3-13 3-14 3-14 3-14 3-14 3-15 3-15 3-15 3-15 3-15 3-16 3-16 3-17 3-18 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.2.1. 2.2.2. 2.2.2.1. 2.2.2.2. 2.2.2.3. 2.2.2.3.1. 2.2.2.4. 2.3. 2.3.1. 2.3.2. 2.3.3. 2.3.4. 2.3.4.1. 2.3.4.2. 2.3.4.3. 2.3.4.3.1. 2.3.4.3.2. 2.3.4.3.3. 2.3.4.4. 2.3.4.5. 2.3.4.6. 2.3.4.7. 2.3.5. 2.3.6. 2.4. 2.4.1. 2.4.2. 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.5. 3.1.6. 3.1.7. Introduction Chip Architecture MSP Features Application Fields Functional Description Architecture of the MSP Demodulator Overview on Sound Standards Demodulator Features Standard Selection Carrier Detection/Mute Automatic Sound Select (ASS) Configuration of Automatic Sound Select STATUS Change Interrupt to Controller Audio Baseband Processing (DSP) Preprocessing of Demodulator Signals Preprocessing for Analog Inputs Source Selection and Output Channel Matrix Features for Loudspeaker Outputs Automatic Volume Correction (AVC) Subwoofer Output Micronas BASS (MB) Dynamic Amplification Adding Harmonics Micronas BASS Parameters SRS WOW BBE High Definition Sound Micronas VOICE (MV) Virtual Surround Sound Headphone Outputs Quasi-Peak Detector Channel Analog Section Analog Configuration Setup Analog Input/Output Selection Control Interface I2C Bus Register and Interface Description Reset of MSP and DRX via I2C (Soft-Reset) I2C Bus Response Time Internal Hardware Error Handling FBL-Status Protocol Description Description of CONTROL Register Generalized I2C Telegrams
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Video-Controller-Text-IF-Audio IC Family
Contents, continued Page 3-18 3-18 3-18 3-18 3-18 3-19 3-19 3-20 3-23 3-37 3-37 3-37 3-37 3-37 3-37 3-38 3-38 3-38 3-38 3-38 3-38 3-38 3-39 3-40 3-40 3-41 3-42 3-42 3-43 3-44 3-46 Section 3.1.7.1. 3.1.7.2. 3.1.7.3. 3.1.7.4. 3.2. 3.3. 3.4. 3.5. 3.6. 3.7. 3.7.1. 3.7.2. 3.7.3. 3.7.4. 3.7.5. 3.7.5.1. 3.7.5.2. 3.7.5.3. 3.7.5.4. 3.7.5.5. 3.8. 3.8.1. 3.8.2. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 5. Title Symbols Write Telegrams Read Telegrams Examples Start-Up Sequence: Power-Up and I2C-Controlling I2C Register Block Index I2C Bit Slices Index I2C Register Subaddress Index I2C Bit Slice Description Application and Programming Tips Analog Power Configuration Setup Define Analog Input to DSP and AOUT1/2 Demodulator Setup Loudspeaker and SCART Channel Setup Examples for Minimum Initialization Codes TV-Standard B/G (A2 or NICAM) TV-Standard M/N (BTSC,EIA-J, A2-Korea) BTSC-SAP with SAP at Loudspeakers FM-Stereo Radio Automatic Standard Detection for D/K, applying STATUS-Change Interrupt Manual Demodulator Programming Facilities Source Channel Assigment if Automatic Sound Select is not applied Manual Tuning Appendix: Overview of (TV) Sound Standards NICAM 728 A2 Systems M/N-BTSC-Sound System M-Japanese FM Stereo System (EIA-J) FM-Stereo Radio and RDS Differences between the MSP part of VCTI and MSP 34/44xyG Stand-Alone Products Data Sheet History
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Contents, continued Page Section Title
ADVANCE INFORMATION
Volume 4: Video Processor
4-4 4-4 4-5 4-6 4-6 4-6 4-6 4-8 4-9 4-10 4-10 4-12 4-12 4-12 4-12 4-13 4-13 4-14 4-15 4-16 4-17 4-17 4-17 4-18 4-18 4-18 4-18 4-18 4-19 4-19 4-20 4-20 4-20 4-22 4-22 4-22 4-24 4-24 4-24 4-25 4-25 4-25 4-25 1. 1.1. 1.2. 2. 2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5. 2.2.6. 2.2.7. 2.2.8. 2.2.9. 2.3. 2.3.1. 2.3.2. 2.3.3. 2.3.4. 2.3.5. 2.3.6. 2.3.6.1. 2.3.6.2. 2.3.6.3. 2.3.7. 2.4. 2.4.1. 2.4.2. 2.4.3. 2.4.4. 2.4.5. 3. 3.1. 3.2. 3.3. 3.4. 3.5. 3.6. Introduction Chip Architecture Video Features Functional Description Source Select Analog Source Select Digital Source Select Signal Magnitudes and Gain Control Clamping CVBS Frontend Comb Filter Color Decoder IF-Compensation Chrominance Filter Automatic Standard Recognition (ASR) Color Saturation Control Color Killer Luminance Processing Synchronization RGB Frontend Signal Magnitudes and Gain Control Clamping Digital Prefiltering RGB/YPbPr to YCrCb Matrix Component YCrCb Control Soft Mix Static Switch Mode Static Mixer Mode Dynamic Mixer Mode Fast Blank Activity and Overflow Detection Picture Measurement and Horizontal Scaler Noise Measurement Letter Box Detection Horizontal Prescaler Horizontal Postscaler Panorama Mode Control Interface I2C Bus Interface I2C Bus Format I2C Register Types I2C Register Domains Update of I2C Write Registers .Update of I2C Read Registers
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Video-Controller-Text-IF-Audio IC Family
Contents, continued Page 4-26 4-26 4-28 4-33 4-58 Section 3.7. 3.8. 3.9. 3.10. 4. Title I2C Register Block Index I2C Register Index I2C Register Subaddress Index I2C Register Description Data Sheet History
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Contents, continued Page Section Title
ADVANCE INFORMATION
Volume 5: Display and Deflection Processor
5-4 5-4 5-4 5-5 5-6 5-6 5-7 5-8 5-9 5-9 5-10 5-10 5-11 5-11 5-12 5-12 5-13 5-13 5-13 5-14 5-15 5-16 5-16 5-16 5-16 5-18 5-18 5-18 5-18 5-19 5-19 5-19 5-19 5-20 5-21 5-21 5-21 5-21 5-22 5-22 5-22 5-23 5-23 1. 1.1. 1.2. 1.3. 2. 2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.3.1. 2.1.3.2. 2.1.4. 2.1.5. 2.1.5.1. 2.1.5.2. 2.1.5.3. 2.1.6. 2.1.7. 2.1.8. 2.1.9. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5. 2.3. 2.3.1. 2.3.2. 2.3.3. 2.3.4. 2.3.5. 2.3.6. 2.3.7. 2.3.8. 2.3.9. 2.3.10. 2.3.11. 3. 3.1. 3.2. 3.3. 3.4. Introduction Chip Architecture Features Overview Functional Description Display Processing Dynamic Contrast Improvement (DCI) Black Level Expander/Compressor (BLEC) Luma Sharpness Enhancer (LSE) Dynamic Peaking Luma Transient Improvement (LTI) Chrominance Transition Improvement (CTI) Pixel Mixer Picture Frame Generator Window Generator Test Pattern Generator Contrast, Brightness, Saturation and Tint Programmable Inverse Matrix Non-linear Colorspace Enhancer (NCE) Scan Velocity Modulation Analog Component Back-End Analog RGB Insertion Fast Blank Monitor Reduced Contrast Control CRT Measurement and Control Average Beam Current Limiter Synchronization and Deflection Line-Locked Clock Generator Output Data Controller (ODC) Output Sync Controller (OSC) Deflection Processing Soft Start/Stop of Horizontal Drive Vertical Synchronization Vertical and East/West Deflection Vertical Zoom EHT Compensation Protection Circuitry General Purpose D/A Converter Control Interface I2C Bus Interface I2C Bus Format I2C Register Types I2C Register Domains
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Video-Controller-Text-IF-Audio IC Family
Contents, continued Page 5-23 5-23 5-24 5-25 5-25 5-26 5-29 5-39 5-39 5-40 5-45 5-50 Section 3.5. 3.6. 3.7. 3.8. 3.9. 3.10. 3.11. 3.12. 3.13. 3.14. 3.15. 4. Title Update of I2C Write Registers Update of I2C Read Registers XDFP Control and Status Registers I2C Register Block Index I2C Register Index I2C Register Subaddress Index I2C Register Description XDFP Register Block Index XDFP Register Index XDFP Register Subaddress Index XDFP Register Description Data Sheet History
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Contents, continued Page Section Title
ADVANCE INFORMATION
Volume 6: Controller, OSD and Text Processing
6-7 6-7 6-8 6-9 6-9 6-10 6-10 6-10 6-10 6-11 6-11 6-11 6-11 6-11 6-11 6-11 6-12 6-12 6-12 6-12 6-12 6-12 6-13 6-13 6-13 6-13 6-13 6-13 6-14 6-14 6-15 6-15 6-15 6-16 6-21 6-24 6-24 6-24 6-25 6-25 6-25 6-25 6-26 6-26 1. 1.1. 1.2. 1.3. 1.4. 2. 2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.2. 2.2.1. 2.2.2. 2.2.2.1. 2.2.2.2. 2.2.2.3. 2.2.2.4. 2.2.2.5. 2.2.2.6. 2.2.2.7. 2.2.2.8. 2.2.3. 2.2.4. 2.2.4.1. 2.2.4.2. 2.2.4.3. 2.2.4.4. 2.2.4.5. 2.2.5. 2.2.6. 2.2.6.1. 2.2.6.2. 2.2.6.3. 2.2.6.4. 2.3. 2.3.1. 2.3.2. 2.3.3. 2.3.3.1. 2.3.4. 2.3.5. 2.3.5.1. 2.3.6. Introduction Chip Architecture Features Overview Block Diagram Functional Description Clock System General Function System Clock Pixel Clock Register Description Microcontroller Architecture CPU-Hardware Instruction Decoder Program Control Section Internal Data RAM Arithmetic/Logic Unit (ALU) Boolean Processor Program Status Word Register (PSW) Stack Pointer (SP) Data Pointer Register (DPTR) CPU Timing Addressing Modes Register Addressing Direct Addressing Register-Indirect Addressing Immediate Addressing Base Register plus Index Register-Indirect Addressing Ports and I/O-Pins Instruction Set Notes on Data Addressing Modes Notes on Program Addressing Modes Instruction Set Description Instruction Opcodes in Hexadecimal Order Interrupts Interrupt System Interrupt Sources Enabling Interrupts Interrupt Enable Registers (IEN0, IEN1, IEN2, IEN3) Interrupt Source Registers Interrupt Priority Interrupt Priority Registers (IP0 IP1) Interrupt Vectors
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Video-Controller-Text-IF-Audio IC Family
Contents, continued Page 6-26 6-26 6-26 6-26 6-27 6-28 6-28 6-28 6-28 6-30 6-30 6-30 6-30 6-30 6-31 6-31 6-31 6-31 6-31 6-31 6-31 6-31 6-31 6-31 6-31 6-31 6-31 6-31 6-32 6-32 6-32 6-32 6-32 6-33 6-33 6-33 6-33 6-34 6-34 6-34 6-34 6-34 6-36 6-36 6-36 6-36 6-36 Section 2.3.7. 2.3.8. 2.3.9. 2.3.10. 2.3.11. 2.3.12. 2.3.13. 2.3.14. 2.3.15. 2.4. 2.4.1. 2.4.2. 2.4.3. 2.4.4. 2.4.5. 2.5. 2.5.1. 2.5.2. 2.5.3. 2.5.4. 2.5.5. 2.5.6. 2.5.7. 2.5.8. 2.5.9. 2.5.10. 2.5.10.1. 2.5.10.2. 2.6. 2.6.1. 2.6.2. 2.6.3. 2.6.4. 2.6.5. 2.6.5.1. 2.6.5.2. 2.6.5.3. 2.6.5.4. 2.6.5.5. 2.6.5.6. 2.7. 2.7.1. 2.8. 2.8.1. 2.8.1.1. 2.8.1.2. 2.8.1.3. Title Interrupt and Memory Extension Interrupt Handling Interrupt Latency Interrupt Flag Clear Interrupt Return Interrupt Nesting External Interrupts Extension of Standard 8051 Interrupt Logic Interrupt Task Function Power Saving Modes Power-Save Mode Registers Idle Mode Power-Down Mode Power-Save Mode Slow-Down Mode Reset Reset Sources Reset Filtering Reset Duration Registers Functional Blocks RAMs Analog Blocks Processor Ports Initialization Phase Acquisition Display Memory Organization Program Memory Internal Data RAM CPU RAM Extended Data RAM (XRAM) Memory Extension Memory Banking for LJMP Instruction Memory Banking for MOVC Instruction Memory Banking for MOVX Instruction Memory Banking for Interrupts Application Examples ROM and ROMless Version Patch Modul Register Description UART Modes Mode 0 Mode 1 Mode 2
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Contents, continued Page 6-36 6-36 6-37 6-37 6-37 6-38 6-38 6-38 6-38 6-38 6-38 6-38 6-38 6-38 6-39 6-39 6-39 6-39 6-39 6-39 6-40 6-40 6-40 6-40 6-40 6-40 6-42 6-42 6-42 6-42 6-42 6-42 6-43 6-43 6-44 6-44 6-45 6-45 6-45 6-45 6-46 6-46 6-46 6-46 6-47 6-47 6-48 Section 2.8.1.4. 2.8.2. 2.9. 2.9.1. 2.9.2. 2.9.3. 2.9.4. 2.9.5. 2.10. 2.10.1. 2.10.2. 2.10.3. 2.10.3.1. 2.10.3.2. 2.10.3.3. 2.10.3.4. 2.10.3.5. 2.10.3.6. 2.10.3.7. 2.10.3.8. 2.10.3.9. 2.10.3.10. 2.10.3.11. 2.10.3.12. 2.10.4. 2.10.5. 2.11. 2.11.1. 2.11.2. 2.11.3. 2.11.4. 2.11.4.1. 2.11.4.2. 2.11.5. 2.11.6. 2.11.7. 2.12. 2.12.1. 2.12.2. 2.12.3. 2.12.4. 2.12.5. 2.12.6. 2.12.7. 2.13. 2.13.1. 2.14. Title
ADVANCE INFORMATION
Mode 3 Multiprocessor Communication General Purpose Timers/Counters Timer/Counter 0: Mode Selection Timer/Counter 1: Mode Selection Configuring the Timer/Counter Input Timer/Counter Mode Register Timer/Counter Control Register Capture Reload Timer Input Clock Reset Values Functional Description Port Pin Slow-Down Mode Run Overflow Modes Normal Capture Mode Polling Mode Capture Mode with Spike Suppression at the Start of a Telegram First Event Second Event CRT Interrupt Counter Stop Idle and Power-Down Mode Registers Pulse Width Modulation Unit Reset Values Input Clock Port Pins Functional Description 8-Bit PWM 14-Bit PWM Power Down, Idle, and Power-Save Mode Timer Control Registers Watchdog Timer Input Clock Starting WDT Refresh WDT Reset Power-Down Mode Time Period WDT as General Purpose Timer Real Time Clock (RTC) Register Description Analog Digital Converter (CADC)
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Video-Controller-Text-IF-Audio IC Family
Contents, continued Page 6-48 6-48 6-48 6-48 6-48 6-50 6-50 6-50 6-51 6-51 6-51 6-51 6-51 6-52 6-52 6-52 6-52 6-52 6-52 6-53 6-54 6-55 6-55 6-56 6-57 6-63 6-63 6-63 6-64 6-64 6-64 6-64 6-65 6-65 6-65 6-66 6-66 6-66 6-66 6-66 6-68 6-68 6-68 6-68 6-68 6-69 6-72 Section 2.14.1. 2.14.2. 2.15. 2.15.1. 2.15.2. 2.16. 2.16.1. 2.16.2. 2.16.2.1. 2.16.2.1.1. 2.16.2.1.2. 2.16.2.1.3. 2.16.2.2. 2.16.3. 2.16.4. 2.16.4.1. 2.16.4.2. 2.16.5. 2.16.5.1. 2.16.5.2. 2.16.5.3. 2.16.6. 2.16.7. 2.16.8. 2.16.9. 2.17. 2.17.1. 2.17.2. 2.17.2.1. 2.17.2.1.1. 2.17.2.1.2. 2.17.2.1.3. 2.17.2.2. 2.17.2.3. 2.17.2.4. 2.17.3. 2.17.4. 2.17.4.1. 2.17.4.1.1. 2.17.4.1.2. 2.17.4.2. 2.17.4.2.1. 2.17.4.2.2. 2.17.4.3. 2.17.4.4. 2.17.5. 2.17.5.1. Title Power Down and Wake Up Register Description I/O-Ports Port Mux Register Description Slicer and Acquisition General Function Slicer Architecture Distortion Processing Noise Frequency Attenuation Group Delay Data Separation H/V-Synchronization Acquisition Interface Framing Code Check Interrupts Software Interface and Algorithms VBI Buffer and Memory Organization Register Description Recommended Parameter Settings ACQ Register Block Index ACQ Register Index ACQ Register Address Index ACQ Register Description Display Generator Display Features Display Sync System Screen Resolution Blacklevel Clamping Area Border Area Character Display Area Display Sync Interrupts Sync Register Description Vertical Field Detection Display Memory Character Display Word (CDW) Access of Characters Address Range from 0d to 767d Address Range from 768d to 1023d Flash Flash for ROM and 1-Bit DRCS Characters Flash for 2-Bit and 4-Bit DRCS Characters Character Individual Double Height Character Individual Double Width Global Display Word (GDW) Character Addressing
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Contents, continued Page 6-73 6-73 6-74 6-74 6-75 6-76 6-77 6-77 6-77 6-77 6-80 6-80 6-81 6-81 6-81 6-84 6-84 6-85 6-85 6-85 6-85 6-86 6-96 6-96 6-96 6-98 6-101 6-118 1 Section 2.17.5.2. 2.17.5.3. 2.17.5.4. 2.17.5.5. 2.17.5.6. 2.17.5.7. 2.17.5.8. 2.17.5.8.1. 2.17.5.8.2. 2.17.5.8.3. 2.17.5.9. 2.17.5.10. 2.17.5.11. 2.17.6. 2.17.6.1. 2.17.7. 2.17.7.1. 2.17.7.2. 2.17.7.3. 2.17.7.4. 2.17.7.5. 2.17.8. 3. 3.1. 3.2. 3.3. 3.4. 4. 5. Title Character Display Area Resolution Cursor Border Color Full Screen Double Height Flash Rate Control Transparency of Boxes CLUT CLUT Access for ROM and 1-bit DRCS Characters CLUT Access for 2-Bit DRCS Characters CLUT Access for 4-Bit DRCS Characters Character Resolution Shadowing Progressive Scan DRCS Characters Memory Organization of DRCS Memory Organization Character Display Area CLUT Area Global Display Word/Cursor 1-Bit/2-Bit/4-Bit DRCS Character Overview of the SFR Registers On-Chip ROM Characters Special Function Register (SFR) SFR Register Block Index SFR Register Index SFR Register Address Index SFR Register Description Data Sheet History VCT 49xxI Data Sheet History
ADVANCE INFORMATION
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI Volume 1: General Description
Volume 1: General Description
Edition 12.12.2003
6251-573-1-1AI
VCT 49xyI, VCT 48xyI
Volume 1: General Description
Contents Page 1-4 1-4 1-6 1-7 1-10 1-10 1-10 1-10 1-10 1-10 1-10 1-11 1-12 1-12 1-14 1-19 1-19 1-19 1-19 1-20 1-20 1-21 1-22 1-24 1-24 1-24 1-25 1-25 1-26 1-28 1-28 1-30 1-30 1-31 1-31 1-32 1-33 1-33 1-33 1-34 1-34 1-34 1-34 1-35 1-35 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 3. 4. 4.1. 4.2. 4.3. 4.3.1. 4.3.2. 4.3.3. 4.3.4. 4.3.5. 4.3.6. 4.4. 4.5. 4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.4. 4.6.4.1. 4.6.4.2. 4.6.4.3. 4.6.4.4. 4.6.4.5. 4.6.4.6. 4.6.4.7. 4.6.4.8. Title Introduction Features Chip Architecture System Application Functional Description VCTI DRX MSP VSP DDP TVT Control Interface Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Supply Pins IF Pins Audio Pins Video Pins CRT Pins Controller Pins Pin Configuration Pin Circuits IF Pins Audio Pins Video Pins CRT Pins Controller Pins Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions General Recommended Operating Conditions Recommended Tuner Characteristics Recommended Crystal Characteristics Analog Input and Output Recommendations Characteristics Package Characteristics Standby Power Consumption Normal Power Consumption Leakage Current Test Input Reset Input/Output I2C Bus Interface IF Input
ADVANCE INFORMATION
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Volume 1: General Description
Contents, continued Page 1-36 1-37 1-37 1-39 1-40 1-44 1-45 1-45 1-46 1-46 1-46 1-47 1-47 1-47 1-48 1-49 1-49 1-50 1-52 1-53 1-53 1-54 1-56 1-63 1-64 Section 4.6.4.9. 4.6.4.10. 4.6.4.11. 4.6.4.11.1. 4.6.4.11.2. 4.6.4.12. 4.6.4.13. 4.6.4.14. 4.6.4.15. 4.6.4.16. 4.6.4.17. 4.6.4.18. 4.6.4.19. 4.6.4.20. 4.6.4.21. 4.6.4.22. 4.6.4.23. 4.6.4.24. 4.6.4.25. 4.6.4.26. 4.6.4.27. 4.6.4.28. 5. 6. 7. Title Sound IF Output Tuner AGC Output Analog Audio Inputs and Outputs Analog Audio Performance Sound Standard Dependent Characteristics Analog Video Inputs Analog Video Outputs Horizontal Flyback Input Horizontal Drive Output Dynamic Focus Output Protection Inputs Vertical and East/West D/A Converter Output East/West PWM Output Sense A/D Converter Input Analog RGB and FB Inputs D/A Converter Reference Scan Velocity Modulation Output Analog RGB Outputs, D/A Converters CADC Input Port I/O Ports Memory Interface Memory Interface Timing Application Glossary of Abbreviations Data Sheet History
Micronas
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VCT 49xyI, VCT 48xyI
Volume 1: General Description
General Description Release Note: This data sheet describes functions and characteristics of the VCT 49xyI, VCT 48xyIC4. 1.1. Features
ADVANCE INFORMATION
The VCT 49xyI, VCT 48xyI family offers a rich feature set, covering the whole range of state-of-the-art 50/ 60 Hz TV applications. PSSDIP88-1/-2 package
1. Introduction The VCT 49xyI, VCT 48xyI is an IC family of high-quality single-chip TV processors. Modular design and deep-submicron technology allow the economic integration of features in all classes of single-scan TV sets. The VCT 49xyI, VCT 48xyI family is based on functional blocks contained and approved in existing products like DRX 396xA, MSP 34x5G, VSP 94x7B, DDP 3315C, and SDA 55xx. Each member of the family contains the entire IF, audio, video, display, and deflection processing for 4:3 and 16:9 50/60-Hz mono and stereo TV sets. The integrated microcontroller is supported by a powerful OSD generator with integrated Teletext & CC acquisition including on-chip page memory.
PMQFP144-2 package Submicron CMOS technology Low-power standby mode Single 20.25 MHz reference crystal 8-bit 8051 instruction set compatible CPU Up to 256 kB on-chip program ROM WST, PDC, VPS, and WSS acquisition Closed Caption and V-chip acquisition Up to 10 pages on-chip teletext memory Multi-standard QSS IF processing with single SAW FM Radio and RDS with standard TV tuner TV-sound demodulation: · all A2 standards · all NICAM standards · BTSC/SAP with MNR (DBX optional) · EIA-J Baseband sound processing for loudspeaker channel: · volume and balance · bass/treble or equalizer · loudness and spatial effect (e.g. pseudo stereo) · Micronas AROUND (virtual Dolby optional) · Micronas BASS and Subwoofer output · further optional and licence requiring sound enhancements as BBE, SRS Wow and Micronas VOICE CVBS, S-VHS, YCrCb and RGB inputs 4H adaptive comb filter (PAL/NTSC) multi-standard color decoder (PAL/NTSC/SECAM)
Video & Sound IF DRX 396xA
Audio Processing MSP 34x5G
Video Processing VSP 94x7B
VCT 49xyI VCT 48xyI
Display & Deflection DDP 3315C
Control, OSD, Text SDA 55xx
Nonlinear horizontal scaling "panorama vision" Luma and chroma transient improvement (LTI, CTI) Non-linear color space enhancement (NCE)
Fig. 11: Single-chip VCT 49xyI, VCT 48xyI
Dynamic black level expander (BLE) Scan velocity modulation output Soft start/stop of H-drive Vertical angle and bow correction Average and peak beam current limiter Nonlinear and dynamic EHT compensation Black switch off procedure (BSO)
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Table 11: VCT 49xyI, VCT 48xyI Family
4x21
4x22
4923
4924
4931
4932
4933
4934
4x41
4x42
4943
4944
4x46
4947
4948
4951
4952
4953
4954
4956
4957
4958
4962
4963
4964
4966
4967
4968
4972
4973
4974
4976
4977
4978
4982
4983
4986
4987
4992
4993
4996
4997
y y y y y y
Global analog stereo decoder A2, EIA-J, BTSC (dbx), FM Radio + auto. stand. detect., STATUS-reg., auto. sound sel., fm-hdev
y
y y y y y y y y y y y y y y y
y
y
y
y
y
y
y
y
y
y
y
y
y y y y y y y y y y y y y y y y y y y y y y y
y y y y y y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y y
y
ADVANCE INFORMATION
Radio Data System (RDS/RBDS) NICAM stereo decoder
y
y y y y y y y y y y y y y y y
y
Eco stereo feature pack bass, treble, loudness, balance, spatial effects, beeper
y y y y y y y y y y y y y y
y
y
y
y
y
y
y
y
Basic stereo feature pack Micronas BASS, subwoofer, Micronas AROUND virtual, equalizer
opt
y y y y y y y y y y y y y
opt
opt
opt
opt
opt
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y opt opt opt opt opt y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y opt opt opt opt opt opt opt opt y y y y y y y y opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt y y y y y y y y opt opt opt opt opt opt opt opt opt opt opt opt opt y y y y y y y y opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt y y y y y y y y y y y y y
y opt opt opt opt opt y y y y y y y y y opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt
y
y
y
y
y opt opt opt opt opt y y y y y y y y y opt opt opt opt opt y y y y y y y y y opt opt opt opt opt y y y y y y y y y
y opt opt opt opt opt y y y y y y y y y opt opt opt opt opt y y y y y y y y y opt opt opt opt opt y y y y y y y y y
y opt opt opt opt opt y y y y y y y y y
y opt opt opt opt opt y y y y y y y y y
Virtual Dolby Surround® (VDS) Micronas VOICE
opt opt opt opt opt y y y y y opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt
opt
opt
opt
opt opt opt opt opt y y y y y y y y y
®
opt
opt
opt
Volume 1: General Description
opt
opt
opt
opt
opt
opt
opt
opt
opt
y
y y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y y y y
y y y y y y y y y y y y y y y y y y y y y y y y y y y
y
y
y
y
y
y
y
y
y
y
y
y
y y
y JE JE JE JE IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
SRS (3D-Audio) SRS® TruBass SRS® WOW (SRS&TruBass&Focus) BBETM (High Definition Sound) 4H adaptive comb filter Panorama scaler 2nd RGB/YCrCb input Softmix 2nd RGB via fastblank CTI, LTI, histogram Dynamic EHT compensation Scan velocity modulation (SVM) Dynamic focus control ITU-656 Input or Output Teletext, VPS, PDC, WSS On-chip program memory
PY PZ PY PZ PY PZ PY PZ PY PZ XM PY PZ XM PY PZ XM PY PZ XM PY PZ XM PY PZ XM PY PZ XM PY PZ XM PY PZ XM PY PZ XM PY PZ XM PY PZ XM PY PZ XM PY PZ XM
PY PZ XM PY PZ XM PY PZ XM PY PZ XM PY PZ XM PY PZ XM PY PZ XM PY PZ XM PY PZ XM PY PZ XM
JE
JE
JE
JE
IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG
IFG
Packages Flash: E = 128 kB; F = 256 kB; G = 512 kB;
PY PZ
PY PZ
PY PZ
PY PZ
PY PZ XM
PY PZ XM
XM
XM
XM
XM
XM
XM
XM
XM
XM
Memory/Package Definition: Common Features: IF Processing:
ROM: J = 128 kB; I = 256 kB;
PY = PSSDIP88-1; PZ = PSSDIP88-2 (mirrored); XM = PMQFP144-2; =
Audio Processing:
Color Decoder:
VCT 49xyI, VCT 48xyI
Video Processing: Display Processing: Deflection: Controller: Miscellaneous:
global alignment-free quasi split sound video and sound IF with single SAW, SIF-out (alternativ vely to AIN1_R) global mono audio, mono FM radio, standard selection, automatic volume control, volume, 1 sp peaker out PSSDIP88: 2/3 line in, 2/1 line out (switchable); PMQFP144: 3 line in, 2 line out , 4xy1 versions in PSSDIP88: 3 line in, 1 line out 11 CVBS/YC/RGB/YCrCb inputs, 3 CVBS outputs, 1H NTSC comb filter, blackline detector 49xy: global color decoder; 48xy: NTSC only color decoder contrast, saturation, tint, peaking, brightness, gamma, black and blue stretch, programmable R RGB matrix analog RGB inputs, cutoff and white balance control, beamcurrent limiter H, V and E/W deflection, H and V EHT compensation, soft start/stop, black switch off, angle and bow, protection circuit d CC, V-Chip, ROM, RAM, OSD, DAC, ADC, RTC, timer, watchdog, interrupt controller, UART, I2C bus, Flash version, patch modul one crystal, few external components, alignment-free
49xy
y y y y
Micronas
Basic CRT
Basic 16/9 CRT Emu LCD
Typical TV Application:
Eco CRT
Features in VCT49xy Versions:
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VCT 49xyI, VCT 48xyI
Volume 1: General Description
1.2. Chip Architecture
ADVANCE INFORMATION
IFIN+ IFIN-
IF Frontend
IF Processor
SIF
Sound Demodulator
Audio Processor
PROT HOUT HFLB
SPEAKER
TAGC
AOUT
AIN
CVBS in YCrCb in RGB in CVBS out
Video Frontend
Comb Filter
Color Decoder
VERT
Component Interface
Panorama Scaler
Display & Deflection Processor
EW
Video Backend
SVM RGB out RGB in SENSE RSW
Slicer
Bus Arbiter
Display Generator
I2C Master/ Slave Timer CRT PWM ADC UART Watchdog RTC I/O-Ports
I2C
24kB Char ROM
CPU 8051
Reset & Test Logic
RESETQ TEST
20kB XRAM
256kB Prog ROM
Memory Interface
Clock Generator
XTAL1 XTAL2
ADB, DB, PSENQ, PSWEQ, WRQ, RDQ
Pxy
Fig. 12: Block diagram of the VCT 49xyI, VCT 48xyI
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Volume 1: General Description
1.3. System Application
20.25 MHz
AOUT1 AIN1 RGB/FB/C1 VOUT1 CVBS1/Y1
SAW
IFIN+ IFIN-
Tuner
AV1
TAGC I2C ID1
4:3/16:9 CRT
AOUT2 AIN2 C2 VOUT2 CVBS2/Y2 H/V/EW
VCT 49xyI VCT 48xyI
RGB/SVM SENSE
AV2
ID2
Loudspeaker
SPEAKER C3 CVBS3/Y3 AIN3 separate AIN3 only available in PMQFP package S-Video Video L - Audio - R
Headphone
Fig. 13: Stereo TV set with VCT 49xyI, VCT 48xyI
Micronas
AV3
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VCT 49xyI, VCT 48xyI
Volume 1: General Description
ADVANCE INFORMATION
20.25 MHz
VOUT2 VOUT1 AOUT1
SAW
IFIN+ IFIN-
Tuner
Mon
S-Video
Video
L - Audio - R YCrCb
TAGC I2C
DVD
Y
Cb
Cr C1 CVBS1/Y1 AIN1 H/V/EW
4:3/16:9 CRT
AV1
VCT 49xyI VCT 48xyI
S-Video Video L - Audio - R C2 CVBS2/Y2 AIN2
RGB/SVM SENSE
AV2
Loudspeaker
S-Video Video L - Audio - R C3 CVBS3/Y3 AIN3 separate AIN3 only available in QFP package SPEAKER
Headphone
AOUT2
AV3
S-Video
Video
L - Audio - R
Fig. 14: Stereo TV set with VCT 49xyI, VCT 48xyI
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Volume 1: General Description
CE#
1 MByte Flash (e.g. Am29LV800B)
A[19-0] DQ[7-0]
OE# WE#
PSENQ PSWEQ
DB[7-0]
VCT 49xyI VCT 48xyI
ADB[19-0]
WRQ RDQ
OE# WE#
A[19-0] DQ[7-0]
CE#
1 MByte SRAM (e.g. TC55VBM316)
Fig. 15: VCT 49xyI, VCT 48xyI application with external program and teletext memory
Micronas
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VCT 49xyI, VCT 48xyI
Volume 1: General Description
2. Functional Description
The functional description of the VCT 49xyI, VCT 48xyI is split up into several volumes:
ADVANCE INFORMATION
2.1. VCTI
Volume 1: General Description (this document)
2.2. DRX
Volume 2: DRX - Analog TV IF- Demodulator
2.3. MSP
Volume 3: Multistandard Sound Processor
2.4. VSP
Volume 4: Video Processor
2.5. DDP
Volume 5: Display and Deflection Processor
2.6. TVT
Volume 6: Controller, OSD and Text Processing
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Volume 1: General Description
3. Control Interface Table 31: I2C Slave Device Addresses Block Write
DRX MSP VSP DDP TVT h'8E h'8C h'B0 h'BC h'D0
8-bit Device Address Read
h'8F h'8D h'B1 h'BD h'D1 programmable via SFR
VCT 49xyI
IOPort
TVT 8051 I2C M/S Interface
DRX
MSP
VSP
int. I2C-Bus
DDP Buffer
ext. I2C-Bus
Computer
Tuner
NVM
MSP
DPL
PIP
Fig. 31: I2C Environment
Micronas
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VCT 49xyI, VCT 48xyI
Volume 1: General Description
4. Specifications 4.1. Outline Dimensions
ADVANCE INFORMATION
Fig. 41: PSSDIP88-1: Plastic Staggered Shrink Dual In-line Package, 88 leads, 750 mil Ordering code: PY or PZ Weight approximately 9.46 g
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Volume 1: General Description
Fig. 42: PMQFP144-2: Plastic Metric Quad Flat Package, 144 leads, 28 × 28 × 3.4 mm3, 21 × 21 mm2 heat slug Ordering code: XM Weight approximately 10.1 g
Micronas
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VCT 49xyI, VCT 48xyI
Volume 1: General Description
4.2. Pin Connections and Short Descriptions
NC = not connected LV = if not used, leave vacant OBL = obligatory; connect as described in circuit diagram IN = Input Pin OUT = Output Pin SUPPLY = Supply Pin
ADVANCE INFORMATION
Pin No.
PMQFP144-2 PSSDIP88-1 PSSDIP88-2
Pin Name
Type
Connection
(If not used)
Short Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62
128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 10
GND VSUP5.0BE TEST / SUBW VERT+ VERTEW RSW2 RSW1 SENSE GNDM FBIN RIN GIN BIN SVMOUT ROUT GOUT BOUT VRD XREF VSUP3.3BE GND GND VSUP3.3IO
SUPPLY SUPPLY IN OUT OUT OUT OUT OUT OUT IN IN IN IN IN IN OUT OUT OUT OUT
OBL OBL GND GND GND GND LV LV GND GND GND GND GND GND VSUP5.0BE VSUP5.0BE VSUP5.0BE VSUP5.0BE OBL OBL
Ground Platform Supply Voltage Analog Video Back-end, 5.0 V Test Input, reserved for Test Subwoofer Output Differential Vertical Sawtooth Output Differential Vertical Sawtooth Output Vertical Parabola Output Range Switch 2 Output Range Switch 1 Output Sense ADC Input Reference Ground for Sense ADC Fast Blank Input, Back-end Analog Red Input, Back-end Analog Green Input, Back-end Analog Blue Input, Back-end Scan Velocity Modulation Output Analog Red Output Analog Green Output Analog Blue Output Reference Voltage for RGB DACs Reference Current for RGB DACs Supply Voltage Analog Video Back-end, 3.3 V Ground Platform Ground Platform Supply Voltage I/O Ports, 3.3 V Supply Voltage Video DACs, 3.3 V Ground Video DACs Safety Input
SUPPLY SUPPLY SUPPLY SUPPLY
OBL OBL OBL OBL OBL OBL GND
VSUP3.3DAC SUPPLY GNDDAC SAFETY SUPPLY IN
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Volume 1: General Description
Pin No.
PMQFP144-2 PSSDIP88-1 PSSDIP88-2
Pin Name
Type
Connection
(If not used)
Short Description
28 29 30 - - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
61 60 59 - - 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
11 12 13 37 38 39 40 41 42 43 44 45 46 47 48 49 50 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
HFLB HOUT VPROT PWMV DFVBL SDA SCL P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 VSUP3.3FE GND GND VSUP1.8FE VOUT3 VOUT2 VOUT1 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 VIN9
IN OUT IN OUT OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT SUPPLY SUPPLY SUPPLY SUPPLY OUT OUT OUT IN IN IN IN IN IN IN IN IN
HOUT LV GND LV LV OBL OBL LV LV LV LV LV LV LV LV LV LV OBL OBL OBL OBL LV LV LV GND GND GND GND GND GND GND GND GND
Horizontal Flyback Input Horizontal Drive Output Vertical Protection Input PWM Vertical Output Dynamic Focus Vertical Blanking Output I2C Bus Data Input/Output I2C Bus Clock Input/Output Port 2, Bit 1 Input/Output Port 2, Bit 0 Input/Output Port 1, Bit 7 Input/Output Port 1, Bit 6 Input/Output Port 1, Bit 5 Input/Output Port 1, Bit 4 Input/Output Port 1, Bit 3 Input/Output Port 1, Bit 2 Input/Output Port 1, Bit 1 Input/Output Port 1, Bit 0 Input/Output Supply Voltage Analog Video Front-end, 3.3 V Ground Platform Ground Platform Supply Voltage Analog Video Front-end, 1.8 V Analog Video 3 Output Analog Video 2 Output Analog Video 1 Output Analog Video 1 Input Analog Video 2 Input Analog Video 3 Input Analog Video 4 Input Analog Video 5 Input Analog Video 6 Input Analog Video 7 Input Analog Video 8 Input Analog Video 9 Input
Micronas
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VCT 49xyI, VCT 48xyI
Volume 1: General Description
Pin No.
PMQFP144-2 PSSDIP88-1 PSSDIP88-2
ADVANCE INFORMATION
Pin Name
Type
Connection
(If not used)
Short Description
59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 - - - - 80 81 82 83 84 85
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - - 9 8 7 6 5 4
69 70 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 - - 121 122 123 124
VIN10 VIN11 P23 P22 XTAL2 XTAL1 VSUP1.8DIG GND GND VSUP3.3DIG VSUP5.0IF VSUP5.0FE RESETQ IFIN+ IFINVREFIF TAGC AIN1R / SIF AIN1L AIN2R AIN2L AIN3R AIN3L AOUT2R AOUT2L AIN3R / AOUT2R AIN3L / AOUT2L AOUT1R AOUT1L SPEAKERR SPEAKERL
IN IN IN/OUT IN/OUT OUT IN SUPPLY SUPPLY SUPPLY SUPPLY SUPPLY SUPPLY IN/OUT IN IN
GND GND LV LV OBL OBL OBL OBL OBL OBL OBL OBL OBL VREFIF VREFIF OBL
Analog Video 10 Input Analog Video 11 Input Port 2, Bit 3 Input/Output Port 2, Bit 2 Input/Output Analog Crystal Output Analog Crystal Input Supply Voltage Digital Core, 1.8 V Ground Platform Ground Platform Supply Voltage Digital Core, 3.3 V Supply Voltage IF ADC, 5.0 V Supply Voltage Analog IF Front-end, 5.0 V Reset Input/Output Differential IF Input Differential IF Input Reference Voltage, IF ADC Tuner AGC Output Analog Audio 1 Input, Right Analog 2nd Sound IF Output Analog Audio 1 Input, Left Analog Audio 2 Input, Right Analog Audio 2 Input, Left Analog Audio 3 Input, Right Analog Audio 3 Input, Left Analog Audio 2 Output, Right Analog Audio 2 Output, Left Analog Audio 3 Input, Right Analog Audio 2 Output, Right Analog Audio 3 Input, Left Analog Audio 2 Output, Left Analog Audio 1 Output, Right Analog Audio 1 Output, Left Analog Loudspeaker Output, Right Analog Loudspeaker Output, Left
OUT IN/OUT IN IN IN IN IN OUT OUT IN / OUT IN / OUT OUT OUT OUT OUT
LV GND GND GND GND GND GND LV LV LV LV LV LV LV LV
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Volume 1: General Description
Pin No.
PMQFP144-2 PSSDIP88-1 PSSDIP88-2
Pin Name
Type
Connection
(If not used)
Short Description
86 87 88 - - - - - - - - - - - - - - - - - - - - - - -
3 2 1 - - - - - - - - - - - - - - - - - - - - - - -
125 126 127 71 72 73 74 75 76 77 78 79 80 81 82 83 31 21 19 22 23 18 17 26 14 96
VREFAU VSUP8.0AU GND P37 / 656IO7 P36 / 656IO6 P35 / 656IO5 P34 / 656IO4 P33 / 656IO3 GNDEIO VSUP3.3EIO P32 / 656IO2 P31 / 656IO1 P30 / 656IO0 P26 / 656VIO P25 / 656HIO P24 / 656CLKIO ADB19 ADB18 ADB17 ADB16 ADB15 ADB14 ADB13 ADB12 ADB11 ADB10 SUPPLY SUPPLY IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT SUPPLY SUPPLY IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
OBL OBL OBL LV LV LV LV LV OBL OBL LV LV LV LV LV LV LV LV LV LV LV LV LV LV LV LV
Reference Voltage, Audio Supply Voltage Analog Audio, 8.0 V Ground Platform Port 3, Bit 7 Input/Output Digital 656 Bus 7 Input/Output Port 3, Bit 6 Input/Output Digital 656 Bus 6 Input/Output Port 3, Bit 5 Input/Output Digital 656 Bus 5 Input/Output Port 3, Bit 4 Input/Output Digital 656 Bus 4 Input/Output Port 3, Bit 3 Input/Output Digital 656 Bus 3 Input/Output Ground Extended I/O Ports Supply Voltage Extended I/O Ports, 3.3 V Port 3, Bit 2 Input/Output Digital 656 Bus 2 Input/Output Port 3, Bit 1 Input/Output Digital 656 Bus 1 Input/Output Port 3, Bit 0 Input/Output Digital 656 Bus 0 Input/Output Port 2, Bit 6 Input/Output Digital 656 Vsync Input/Output Port 2, Bit 5 Input/Output Digital 656 Hsync Input/Output Port 2, Bit 4 Input/Output Digital 656 Clock Input/Output Address Bus 19 Output Address Bus 18 Output Address Bus 17 Output Address Bus 16 Output Address Bus 15 Output Address Bus 14 Output Address Bus 13 Output Address Bus 12 Output Address Bus 11 Output Address Bus 10 Output
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VCT 49xyI, VCT 48xyI
Volume 1: General Description
Pin No.
PMQFP144-2 PSSDIP88-1 PSSDIP88-2
ADVANCE INFORMATION
Pin Name
Type
Connection
(If not used)
Short Description
- - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - -
15 16 27 28 29 30 84 85 86 87 88 89 90 91 92 93 94 95 32 33 34 35 36 97 20 51 52 24 25
ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 ADB3 ADB2 ADB1 ADB0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 RDQ WRQ OCF ALE RSTQ PSENQ PSWEQ XROMQ EXTIFQ STOPQ ENEQ
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT OUT OUT OUT OUT OUT OUT OUT IN IN IN IN
LV LV LV LV LV LV LV LV LV LV LV LV LV LV LV LV LV LV LV LV LV LV LV LV LV OBL LV LV LV
Address Bus 9 Output Address Bus 8 Output Address Bus 7 Output Address Bus 6 Output Address Bus 5 Output Address Bus 4 Output Address Bus 3 Output Address Bus 2 Output Address Bus 1 Output Address Bus 0 Output Data Bus 0 Input/Output Data Bus 1 Input/Output Data Bus 2 Input/Output Data Bus 3 Input/Output Data Bus 4 Input/Output Data Bus 5 Input/Output Data Bus 6 Input/Output Data Bus 7 Input/Output Data Read Enable Output Data Write Enable Output Opcode Fetch Output Address Latch Enable Output Internal CPU Reset Output Program Store Enable Output Program Store Write Enable Output External ROM Enable Input Enable External Interface Input Stop CPU Input Enable Emulation Input
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Micronas
ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
lines to the power supply. Decoupling capacitors from VSUPxx to GND have to be placed as closely as possible to these pins. It is recommended to use more than one capacitor. By choosing different values, the frequency range of active decoupling can be extended.
Volume 1: General Description
4.3. Pin Descriptions 4.3.1. Supply Pins VSUP1.8DIG - Supply Voltage 1.8 V This pin is main and standby supply for the digital core logic of controller, video, display and deflection processing. VSUP1.8FE - Supply Voltage 1.8 V This pin is main and standby supply for the analog video front-end. VSUP3.3FE - Supply Voltage 3.3 V This pin is main and standby supply for the analog video front-end. VSUP3.3IO - Supply Voltage 3.3 V This pin is main and standby supply for the digital I/Oports. VSUP3.3DIG - Supply Voltage 3.3 V This pin is main supply for the digital core logic of IF and audio processing and digital video back-end. VSUP3.3BE - Supply Voltage 3.3 V This pin is main supply for the analog video back-end. VSUP5.0FE - Supply Voltage 5.0 V This pin is main supply for the analog IF front-end. VSUP5.0IF - Supply Voltage 5.0 V This pin is main supply for the IF ADC. VSUP5.0BE - Supply Voltage 5.0 V This pin is main supply for the analog video back-end. VSUP8.0AU - Supply Voltage 8.0 V This pin is main supply for the analog audio processing. GND - Ground Platform This pin is main ground for all above supplies. VSUP3.3DAC - Supply Voltage 3.3 V This pin is main supply for the video DACs. GNDDAC - Ground for 3.3 V Video DAC Supply VSUP3.3EIO - Supply Voltage 3.3 V This pin is main and standby supply for the extended digital I/O-ports available in QFP package only. It is internally connected to VSUP3.3IO. GNDEIO - Ground for 3.3 V Extended I/O Supply It is internally connected to GND. Application Note: All GND pins must be connected to a low-resistive ground plane underneath the IC. All supply pins must be connected separately with short and low-resistive
4.3.2. IF Pins VREFIF - Reference Voltage for analog IF (Fig. 48) This pin must be connected to GND via a circuitry according to the application circuit. Low inductance caps are necessary. IFIN+, IFIN- - Balanced IF Input (Fig. 46) These pins must be connected to the SAW filter output. The SAW filter has to be placed as close as possible. The layout of the IF input should be symmetrical with respect to GND. SIF - 2nd Sound IF Output (Fig. 49) Output level is set via I2C-Bus. An appropriate sound processor (e.g. MSP) can be connected to this pin. This pin is also configurable as audio input (see Fig. 410). TAGC - Tuner AGC Output (Fig. 47) This pin controls the delayed tuner AGC. As it is a noise-shaped-I-DAC output, it has to be connected according to the application circuit.
4.3.3. Audio Pins VREFAU Reference Voltage for Analog Audio (Fig. 414) This pin serves as the internal ground connection for the analog audio circuitry. It must be connected to the GND pin with a 3.3 µF and a 100 nF capacitor in parallel. This pins shows a DC level of typically 3.77 V. AIN1 R/L Audio 1 Inputs (Fig. 410) The analog input signals for audio 1 are fed to these pins. Analog input connection must be AC coupled. The AIN1 R pin is also configurable as sound IF output (see Fig. 49). AIN2 R/L Audio 2 Inputs (Fig. 410) The analog input signals for audio 2 are fed to these pins. Analog input connection must be AC coupled. AIN3 R/L Audio 3 Inputs (Fig. 410) The analog input signals for audio 3 are fed to these pins. Analog input connection must be AC coupled. AOUT1 R/L Audio 1 Outputs (Fig. 411) Output of the analog audio 1 signal. Connections to these pins are intended to be AC coupled.
Micronas
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VCT 49xyI, VCT 48xyI
Volume 1: General Description
AOUT2 R/L Audio 2 Outputs (Fig. 411) Output of the analog audio 2 signal. Connections to these pins are intended to be AC coupled. SPEAKER R/L Loudspeaker Outputs (Fig. 413) Output of the loudspeaker signal. A 1 nF capacitor to GND must be connected to these pins. Connections to these pins are intended to be AC-coupled. SUBW Subwoofer Outputs (Fig. 413) Output of the subwoofer signal. A 1 nF capacitor and a 10 k resistor to GND must be connected to this pin. Connections to this pin are intended to be AC-coupled.
ADVANCE INFORMATION
XREF - DAC Current Reference (Fig. 420) External reference resistor for DAC output currents, typical 1 k to adjust the output current of the D/A converters. (see recommended operating conditions). This resistor has to be connected to ground as closely as possible to the pin.
4.3.5. CRT Pins HOUT - Horizontal Drive Output (Fig. 421) This open source output supplies the drive pulse for the horizontal output stage. An external pulldown resistor has to be used. The polarity and gating with the flyback pulse are selectable by software. HFLB - Horizontal Flyback Input (Fig. 422) Via this pin the horizontal flyback pulse is supplied to the VCT 49xyI, VCT 48xyI. VPROT - Vertical Protection Input (Fig. 422) The vertical protection circuitry prevents the picture tube from burn-in in the event of a malfunction of the vertical deflection stage. If the peak-to-peak value of the sawtooth signal from the vertical deflection stage is too small, the RGB output signals are blanked. SAFETY - Safety Input (Fig. 422) This input has two thresholds. A signal between the lower and upper threshold means normal function. A signal below the lower threshold or above the upper threshold is detected as malfunction and the RGB signals will be blanked. VERT+, VERT- - Vertical Sawtooth Output (Fig. 423) These pins supply the symmetrical drive signal for the vertical output stage. The drive signal is generated with 15-bit precision. The analog voltage is generated by a 4 bit current-DAC with an external resistor of 6.8 k and uses digital noise shaping. EW - East-West Parabola Output (Fig. 424) This pin supplies the parabola signal for the East-West correction. The drive signal is generated with 15 bit precision. The analog voltage is generated by a 4 bit current-DAC with an external resistor of 6.8 k and uses digital noise shaping. PWMV - PWM Vertical Output (Fig. 421) This pin provides an adjustable vertical parabola with 7 bit resolution and approx. 79.4 kHz PWM frequency. DFVBL - Dynamic Focus Vertical Blanking (Fig. 421) This pin supplies the blank pulse for dynamic focus during vertical blanking period or a free programmable horizontal pulse for horizontal dynamic focus generation. Alternatively it can be programmed as FIELD output, delivering even/odd field information. SENSE - Measurement ADC Input (Fig. 427) This is the input of the analog to digital converter for
4.3.4. Video Pins VIN 111 - Analog Video Input (Fig. 415) These are the analog video inputs. A CVBS, S-VHS, YCrCb or RGB/FB signal is converted using the luma, chroma and component AD converters. The input signals must be AC-coupled by 100nF. In case of an analog fast blank signal carrying alpha blending information the input signal must be DC-coupled. VOUT 1-3 - Analog Video Output (Fig. 416) The analog video inputs that are selected by the video source select matrix are output at these pins. RIN, GIN, BIN - Analog RGB Input (Fig. 417) These pins are used to insert an external analog RGB signal, e.g. from a SCART connector which can be switched to the analog RGB outputs with the fast blank signal. Separate brightness and contrast settings for the external analog signals are provided. FBIN - Fast Blank Input (Fig. 418) This pin is used to switch the RGB outputs to the external analog RGB inputs. The active level (low or high) can be selected by software. ROUT, GOUT, BOUT - Analog RGB Output (Fig. 4 19) These pins are the analog Red/Green/Blue outputs of the back-end. The outputs are current sinks. SVMOUT - Scan Velocity Modulation Output (Fig. 4 19) This output delivers the analog SVM signal. The D/A converter is a current sink like the RGB D/A converters. At zero signal the output current is 50% of the maximum output current. VRD - DAC Reference Decoupling (Fig. 420) Via this pin the RGB-DAC reference voltage is decoupled by an external capacitor. The DAC output currents depend on this voltage, therefore a pulldown transistor can be used to shut off all beam currents. A decoupling capacitor of 4.7 µF in parallel to 100 nF (low inductance) is required.
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
ADB0-ADB19 - Address Bus Output (Fig. 435) These 20 lines provide the CPU address bus output to access external memory. DB0-DB7 - Data Bus Input/Output (Fig. 436) These 8 lines provide the bidirectional CPU data bus to access external memory. WRQ - Data Write Enable Output (Fig. 435) This pin controls the direction of data exchange between the CPU and the external data memory device (SRAM). RDQ - Data Read Enable Output (Fig. 435) This pin is used to enable the output driver of the external data memory device (SRAM) for read access. PSENQ - Program Store Enable Output (Fig. 435) This pin is used to enable the output driver of the external program memory device (ROM/FLASH) for read access. PSWEQ - Program Store Write Enable Output (Fig. 4 35) This pin is used to write into the external program flash memory device. XROMQ - External ROM Enable Input (Fig. 437) This pin must be pulled low to access the external program memory. XROMQ has an internal pull-up resistor. EXTIFQ - Enable External Memory Interface Input (Fig. 437) This pin must be pulled low to enable the external memory interface. EXTIFQ has an internal pull-up resistor. STOPQ - Stop CPU Input (Fig. 437) Applying a low level during the input phase freezes the real-time relevant internal peripherals such as timers and interrupt controller. STOPQ has an internal pull-up resistor. ENEQ - Enable Emulation Input (Fig. 437) Only if this pin is set to low level, STOPQ and OCF are operational. ENEQ has an internal pull-up resistor. ALE - Address Latch Enable Output (Fig. 435) This signal indicates changes on the address bus. OCF - Opcode Fetch Output (Fig. 435) A high level driven by the CPU during output phase indicates the beginning of a new instruction. RSTQ - Internal CPU Reset Input/Output (Fig. 438) This pin is used for emulation purpose only. A low level on this pin resets the CPU. It also indicates an internal reset of the CPU. RSTQ has an internal pull-up resistor.
Volume 1: General Description
the picture and tube measurement. Three measurement ranges are selectable with RSW1 and RSW2.
GNDM - Measurement ADC Reference Input This is the reference ground for the measurement A/D converter. Connect this pin to GND. RSW1 - Range Switch1 for Measuring ADC (Fig. 4 25) These pin is an open drain pull-down output. During cutoff and white drive measurement the switch is off. During the rest of time it is on. The RSW1 pin can be used as second measurement ADC input for picture beam current measurement. RSW2 - Range Switch2 for Measuring ADC (Fig. 4 26) These pin is an open drain pull-down output. During cutoff measurement the switch is off. During white drive measurement the switch is on. Also during the rest of time it is on. It is used to set the range for white drive current measurement.
4.3.6. Controller Pins XTAL1 - Crystal Input and XTAL2 Crystal Output (Fig. 428) These pins connect a 20.25 MHz crystal to the internal oscillator. An external clock can be fed into XTAL2. RESETQ - Reset Input/Output (Fig. 429) A low level on this pin resets the VCT 49xyI, VCT 48xyI. The internal CPU can pull down this pin to reset external devices connected to this pin. TEST - Test Input (Fig. 430) This pin enables factory test modes. For normal operation, it must be connected to ground. Alternatively this pins serves as subwoofwer output. SCL - I2C Bus Clock (Fig. 431) This pin delivers the I2C bus clock line. The signal can be pulled down by external slave ICs to slow down data transfer. SDA - I2C Bus Data (Fig. 431) This pin delivers the I2C bus data line. P10-P13, P20-P23 - I/O Port (Fig. 432) These pins provide CPU controlled I/O ports. P14-P17 - I/O Port (Fig. 433) These pins provide CPU controlled I/O ports. Additionally they can be used as analog inputs for the controller ADC. P24-P26, P30-P37 - I/O Port (Fig. 434) These pins provide CPU controlled I/O ports.
Micronas
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VCT 49xyI, VCT 48xyI
Volume 1: General Description
4.4. Pin Configuration
ADVANCE INFORMATION
GND VSUP1.8FE VOUT3 VOUT2 VOUT1 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 VIN9 VIN10 VIN11 P23 P22 XTAL2 XTAL1 VSUP1.8DIG GND GND VSUP3.3DIG VSUP5.0IF VSUP5.0FE RESETQ IFIN+ IFINVREFIF TAGC SIF / AIN1R AIN1L AIN2R AIN2L AIN3R / AOUT2R AIN3L / AOUT2L AOUT1R AOUT1L SPEAKERR SPEAKERL VREFAU VSUP8.0AU GND
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
GND VSUP3.3FE P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 SCL SDA VPROT HOUT HFLB SAFETY GNDDAC VSUP3.3DAC VSUP3.3IO GND GND VSUP3.3BE XREF VRD BOUT GOUT ROUT SVMOUT BIN GIN RIN FBIN GNDM SENSE RSW1 RSW2 EW VERTVERT+ TEST / SUBW VSUP5.0BE GND
GND VSUP3.3FE P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 SCL SDA VPROT HOUT HFLB SAFETY GNDDAC VSUP3.3DAC VSUP3.3IO GND GND VSUP3.3BE XREF VRD BOUT GOUT ROUT SVMOUT BIN GIN RIN FBIN GNDM SENSE RSW1 RSW2 EW VERTVERT+ TEST / SUBW VSUP5.0BE GND
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
GND VSUP1.8FE VOUT3 VOUT2 VOUT1 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 VIN9 VIN10 VIN11 P23 P22 XTAL2 XTAL1 VSUP1.8DIG GND GND VSUP3.3DIG VSUP5.0IF VSUP5.0FE RESETQ IFIN+ IFINVREFIF TAGC SIF / AIN1R AIN1L AIN2R AIN2L AIN3R / AOUT2R AIN3L / AOUT2L AOUT1R AOUT1L SPEAKERR SPEAKERL VREFAU VSUP8.0AU GND
VCT 49xyI, VCT 48xyI PY
Fig. 43: PSSDIP88-1 package
Fig. 44: PSSDIP88-2 package (pinning mirrored)
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VCT 49xyI, VCT 48xyI PZ
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Volume 1: General Description
ADB3 P24 / 656CLKIO P25 / 656HIO P26 / 656VIO P30 / 656IO0
P31 / 656IO1 P32 / 656IO2 VSUP3.3EIO
GNDEIO P33 / 656IO3
76 75
98
97
96
92
91
90
88
86
84
81
102
101
105
104
103
100
99
95
94
93
89
87
85
83
82
80
79
78
108
107
106
77
74
IFIN+ IFINVREFIF TAGC AIN1R / SIF AIN1L AIN2R AIN2L AIN3R AIN3L AOUT2R AOUT2L AOUT1R AOUT1L SPEAKERR SPEAKERL VREFAU VSUP8.0AU GND GND VSUP5.0BE TEST / SUBW VERT+ VERTEW RSW2 RSW1 SENSE GNDM FBIN RIN GIN BIN SVMOUT ROUT GOUT
73
P34 / 656IO4 P35 / 656IO5
VSUP3.3DIG
VSUP1.8DIG
VSUP5.0FE
VSUP5.0IF
RESETQ
P23 PSENQ
ADB10 DB7 DB6
XTAL1 XTAL2
DB3 DB2 DB1 DB0 ADB0 ADB1 ADB2
GND
GND
DB5 DB4
P22
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
P36 / 656IO6 P37 / 656IO7 VIN11 VIN10 VIN9 VIN8 VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VOUT1 VOUT2 VOUT3 VSUP1.8FE GND GND VSUP3.3FE EXTIFQ XROMQ P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 SCL SDA DFVBL / FIELD PWMV
VCT 49xyI, VCT 48xyI
XM
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
10
11
12
13
14
15
16
17
18
19
20
21
24
25
26
27
30
31
33
34
35
22
23
28
29
GNDDAC SAFETY
32
6
VSUP3.3BE
VSUP3.3DAC
PSWEQ ADB18 ADB16 ADB15
STOPQ
ENEQ ADB12 ADB7 ADB6 ADB5
ADB4 ADB19 RDQ
VSUP3.3IO
VPROT ADB11 ADB9 ADB8
ADB13 ADB14
Fig. 45: PMQFP144-2 package
Micronas
ADB17
BOUT
HOUT
OCF ALE RSTQ
GND
GND
HFLB
VRD
XREF
WRQ
36
1
2
3
4
5
7
8
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Volume 1: General Description
4.5. Pin Circuits 4.5.1. IF Pins 4.5.2. Audio Pins
ADVANCE INFORMATION
VSUP8.0AU VSUP5.0FE
2k 30 k 3.75 V
+ -
GND
Fig. 410: Input Pins: AIN1-3 R/L
GND
Fig. 46: Input Pins: IFIN+, IFIN-
3.4 pF 120 k
VSUP8.0AU
VSUP5.0FE
3.75 V
300
N
GND
Fig. 411: Output Pins: AOUT1 R/L
GND
Fig. 47: Output Pin: TAGC
6.6 pF
VSUP5.0FE
VSUP8.0AU
1.2k - 478k
125 k 2.5 V 3.75 V
300
GND
Fig. 48: Supply Pin: VREFIF
GND
Fig. 412: Output Pins: AOUT2 R/L
VSUP8.0AU
54 pF
VSUP8.0AU
3.8k - 60k
GND
300 3.75 V
Fig. 49: Output Pin: SIF
GND
Fig. 413: Output Pins: SPEAKER R/L, SUBW
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Volume 1: General Description
VSUP8.0AU
VSUP5.0BE
125 k 3.75 V
VREF GND
GND
Fig. 414: Supply Pin: VREFAU
Fig. 418: Input Pin: FBIN
VSUP5.0BE
4.5.3. Video Pins
N
VSUP3.3FE
to ADC
GND
GND
Fig. 419: Output Pins: ROUT, GOUT, BOUT, SVMOUT
Fig. 415: Input Pins: VIN 1-11
VSUP3.3BE VSUP3.3FE VINx + V=1 150
VRD int. ref. voltage + XREF ref. current
GND
GND
Fig. 416: Output Pins: VOUT 1-3
Fig. 420: Supply Pins: XREF, VRD
VSUP5.0BE
4.5.4. CRT Pins
VSUP3.3IO
P/N
Clamping
P/N
P
VCM GND N GND
Fig. 417: Input Pins: RIN, GIN, BIN
Fig. 421: Output Pins: HOUT, FIELD, DFVBL, PWMV
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VCT 49xyI, VCT 48xyI
Volume 1: General Description
ADVANCE INFORMATION
VSUP3.3IO VREF GND N
VSUP5.0BE
Fig. 422: Input Pins: SAFETY, VPROT, HFLB
GND
Fig. 426: Output Pin: RSW2
VSUP5.0BE P P P
Flyback
VSUP5.0BE P N VERT+ GND
VERT-
N GND
Fig. 427: Input Pin: SENSE
Fig. 423: Output Pins: VERT+, VERT4.5.5. Controller Pins
VSUP5.0BE VSUP3.3IO P P P
XTAL1
N P
XTAL2
N GND
N P GND
Fig. 424: Output Pin: EW
Fig. 428: Input/Output Pins: XTAL1, XTAL2
VSUP5.0BE
47k
VSUP3.3IO
P
to ADC
N N GND
N GND
Fig. 429: Input/Output Pin: RESETQ
Fig. 425: Input/Output Pin: RSW1
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Volume 1: General Description
VSUP5.0BE P
VSUP3.3IO
GND
N GND
Fig. 430: Input Pin: TEST
Fig. 435: Output Pins: ADB0-ADB19, WRQ, RDQ, PSENQ, PSWEQ, ALE, OCF
VSUP3.3IO VSUP3.3IO N GND P
Fig. 431: Input/Output Pins: SDA, SCL
N GND
VSUP3.3IO P
Fig. 436: Input/Output Pins: DB0-DB7
VSUP3.3IO
47k
N GND
Fig. 432: Input/Output Pins: P10-P13, P20-P23
GND VSUP3.3IO P VSUP3.3IO to ADC N GND
47k
Fig. 437: Input Pins: XROMQ, EXTIFQ, STOPQ, ENEQ
Fig. 433: Input/Output Pins: P14-P17
N GND
VSUP3.3EIO P
Fig. 438: Input/Output Pin: RSTQ
N GNDEIO
Fig. 434: Input/Output Pins: P24-P26, P30-P37
Micronas
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VCT 49xyI, VCT 48xyI
Volume 1: General Description
4.6. Electrical Characteristics Abbreviations:
tbd = to be defined vacant = not applicable positive current values mean current flowing into the chip
ADVANCE INFORMATION
4.6.1. Absolute Maximum Ratings
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit. All voltages listed are referenced to ground (list voltages = 0 V) except where noted. ??? All GND pins must be connected to a low-resistive ground plane close to the IC.
Table 41: Absolute Maximum Ratings Symbol Parameter Pin Name Min.
TA1) Ambient Operating Temperature PSSDIP88-1/-2 PMQFP144-2 Case Operating Temperature PSSDIP88-1/-2 PMQFP144-2 Storage Temperature Maximum Power Dissipation PSSDIP88-1/-2 PMQFP144-2 Supply Voltage 8.0 V Supply Voltage 5.0 V Supply Voltage 3.3 V Supply Voltage 1.8 V Voltage differences within supply domains VSUP8.0AU VSUP5.0x VSUP3.3x VSUP1.8x ??? 0 0 tbd
Limit Values Max.
652) 652) tbd
Unit
°C °C °C
TC
TS PMAX
-40 - - -0.3 -0.3 -0.3 -0.3 -0.5
125 2600 2600 9.0 6.0 3.6 2.0 0.5
°C mW mW V V V V V
VSUP8.0 VSUP5.0 VSUP3.3 VSUP1.8 VSUP
1)
Measured on Micronas typical 2-layer (1s1p) board based on JESD - 51.2 Standard with maximum power consumption allowed for this package A power-optimized board layout is recommended. The Case Operating Temperature mentioned in the "Absolute Maximum Ratings" must not be exceeded at worst case conditions of the application.
2)
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ADVANCE INFORMATION
VCT 49xyI, VCT 48xyI
Volume 1: General Description
Table 41: Absolute Maximum Ratings, continued Symbol Parameter Pin Name Min.
VI II VO IO
1)
Limit Values Max.
VSUPx+0.31)
Unit
Input Voltage Input Current Output Voltage Output Current Refer to Pin Circuits section 4.5. on page 24
-0.3
V mA
-0.3
VSUPx+0.31)
V mA
Micronas
15.12.2003; 6251-573-1-1AI
29
VCT 49xyI, VCT 48xyI
Volume 1: General Description
4.6.2. Recommended Operating Conditions
ADVANCE INFORMATION
Functional operation of the device beyond those indicated in the "Recommended Operating Conditions/Characteristics" is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device. All voltages listed are referenced to ground (list voltages = 0 V) except where noted. ??? All GND pins must be connected to a low-resistive ground plane close to the IC. Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. For power up/down sequences, see the instructions in volume 6.
4.6.2.1. General Recommended Operating Conditions Symbol Parameter Pin Name Min.
TA Ambient Operating Temperature PSSDIP88-1/-2 PMQFP144-2 Case Operating Temperature PSSDIP88-1/-2 PMQFP144-2 Maximum Power Dissipation PSSDIP88-1/-2 PMQFP144-2 Clock Frequency Supply Voltage 8.0 V (Range = 8 V) Supply Voltage 8.0 V (Range = 5 V) VSUP5.0 VSUP3.3 VSUP1.8 VSUP VIL VIH RV
1)
Limit Values Typ.
- -
Unit Max.
651) 651) tbd °C °C °C
0 0 tbd
TC
PMAX
26002) 26002) XTAL1/2 VSUP8.0AU - 7.6 4.75 VSUP5.0x VSUP3.3x VSUP1.8x ??? 4.75 3.15 1.71 -0.5 20.25 8.0 5.0 5.0 3.3 1.8 0 - 8.7 5.25 5.25 3.45 1.89 0.5
mW mW MHz V V V V V V V V V
fXTAL VSUP8.0
Supply Voltage 5.0 V Supply Voltage 3.3 V Supply Voltage 1.8 V Voltage differences within supply domains Input Voltage Lo