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CDX-715
SERVICE MANUAL
US Model Canadian Model AEP Model UK Model E Model
Model Name Using Similar Mechanism CD Drive Mechanism Type Optical Pick-up Name
NEW MG-250B-137 KSS-521A/J2N
SPECIFICATIONS
System Laser diode properties Compact disc digital audio system Material: GaAlAs Wavelength: 780 nm Emission Duration: Continuous Laser out-put Power: Less than 44.6 µW* * This output is the value measured at a distance of 200 mm from the objective lens surface on the Optical Pick-up Block. 10 20,000 Hz Below the measurable limit 94 dB BUS control output (8 pins) Analog audio output (RCA pin) Currnet drain Operating temperature Dimensions 800 mA (during CD playback) 800 mA (during loading or ejecting a disc) 10°C to +55°C (14°F to 131°F) Approx. 262 × 90 × 181.5 mm (10 3/8 × 3 5/8 × 7 1/4 in.) (w/h/d) not incl. projecting parts and controls Approx. 2.1 kg (4 lb. 10 oz.) 12 V DC car battery (negative ground) Disc magazine (1) Parts for installation and connections (1 set)
Frequency response Wow and flutter Signal-to-noise ratio Outputs
Mass Power requirement Supplied accessories
Design and specifications subject to change without notice.
COMPACT DISC CHANGER
MICROFILM
CDX-715
7-3. SCHEMATIC DIAGRAM RF Section
· See page 25 for Note on Schematic Diagram. · See page 39 for Waveforms. · See page 41 and 42 for IC Block Diagrams.
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CDX-715
7-5. SCHEMATIC DIAGRAM MAIN Section MAIN Board (1/2) · See page 39 and 40 for Waveforms. · See page 42 to 44 for IC Block Diagrams.
· See page 45 and 46 for IC Pin Function Description.
· See page 36 for Note on Schematic Diagram.
· See page 29 to 32 for Printed Wiring Board.
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CDX-715
MAIN Section MAIN Board (2/2) · See page 40 for Waveforms. · See page 43 and 44 for IC Block Diagrams. · See page 29 to 32 for Printed Wiring Board.
Note on Schematic Diagram: · All capacitors are in µF unless otherwise noted. pF: µµF 50 WV or less are not indicated except for electrolytics and tantalums. · All resistors are in and 1/4 W or less unless otherwise specified. ¢ · : internal component. · U : B+ Line. · H : adjustment for repair. · Power voltage is dc 14.4 V and fed with regulated dc power supply from CD changer controller. · Voltages and waveforms are dc with respect to ground under no-signal conditions. no mark : PLAY : Impossible to measure · Voltages are taken with a VOM (Input impedance 10 M). Voltage variations may be noted due to normal production tolerances. · Waveforms are taken with a oscilloscope. Voltage variations may be noted due to normal production tolerances. · Circled numbers refer to waveforms. · Signal path. J : CD
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CDX-715
7-6. PRINTED WIRING BOARD JACK Section
7-7. SCHEMATIC DIAGRAM JACK Section
Note on Schematic Diagram: · All capacitors are in µF unless otherwise noted. pF: µµF 50 WV or less are not indicated except for electrolytics and tantalums. · All resistors are in and 1/4 W or less unless otherwise specified. · C : panel designation. · U : B+ Line. · Signal path. J : CD · Abbreviation G : German model.
Note on Printed Wiring Board: · X : parts extracted from the component side. · p : parts mounted on the conductor side. r · : Through hole. · b : Pattern from the side which enables seeing. (The other layers' patterns are not indicated.) Caution: Pattern face side: (Conductor Side) Parts face side: (Component Side)
Parts on the pattern face side seen from the pattern face are indicated. Parts on the parts face side seen from the parts face are indicated.
· Abbreviation G : German model.
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· Waveforms RF Board MAIN Board (1/2)
1 IC11 1 (FEO) 500 mV/DIV, 500 nsec/DIV 1 IC101 @¶ MDP
2.5 Vp-p
1.4 ±0.3 Vp-p
3.8 µs
2 IC11 2 (FEI) 50 mV/DIV, 1 µsec/DIV 2 IC101 $ª WDCK
Approx. 110 mVp-p
5 Vp-p
3 IC11 $¶ (TEI) 200 mV/DIV, 500 µsec/DIV
11.4 µs
3 IC101 %º LRCK
Approx. 280 mVp-p
5 Vp-p
22.5 µs
4 IC101 %¢ BCKO
6 Vp-p
472 ns
5 IC101 ^TM RFCK
5 Vp-p
136.5 µs
39
6 IC101 &¢ WFCK
!¡ IC102 0 BCKO
5 Vp-p
5.3 Vp-p
137 µs
7 IC101 *ª XTAI
472 ns
!TM IC102 !¡ LRCKO
4.5 Vp-p
5.3 Vp-p
59 ns
8 IC201 #¡ EXTAL
22.6 µs
MAIN Board (2/2)
!£ IC601 ! XI
3.3 Vp-p
2.9 Vp-p
124.5 ns
9 IC401 !¶ BCK
59 ns
5.9 Vp-p
472 ns
0 IC401 !ª LRCK
5.8 Vp-p
22.8 µs
40
· IC Block Diagrams IC11 CXA1992BR (RF BOARD)
RF_M RF_O RFTC RF_I PD2 PD1 CC1 CC2 FOK 27 PD CP CB 30 LD 36 VEE
+
39
38
37
35
34
33
32
31
29
28
+
PD2 IV AMP FE_BIAS 40
APC VEE
+
F 41
LASER POWER CONTROL F IV AMP
+ +
E 42
+
VCC
FE AMP
+ +
E IV AMP EI 43 BAL1 BAL2 BAL3 BAL4
+ + +
IFB4
IFB2
IFB3
IFB5
IFB1
IFB6
TOG1
TOG2
TOG3
TOG4
VEE 44
VEE
TGFL
VEE
+
FO. BIAS WINDOW COMP.
TEO 45
+
+
TRK. GAIN WINDOW COMP.
+
MIRR
LPCL
TGFL
LPC
CC1
LPFI 46
+
+
E-F BALANCE WINDOW COMP.
DFCT1
LDON
TEI 47
+
ATSC 48
+
FOH FOL TGH TGL BALH BALL ATSC TZC FZC
ATSC WINDOW COMP.
+
TZC 49
TZC COMP. TDFCT 50 VCC
DFCT TM1
TG1
TRACKING PHASE COMPENSATION
VC 51
VCC FZC 52
+
VEE
VEE FS2 Charge up TG2 FSET DFCT
+
VEE
FZC COMP. FS4 VEE 1 FEO 2 FEI 3 FDFCT 4 FGD 5 FLB 6 FE_O 7 FE_M 8 SRCH
9 TGU
10 TG2
11 FSET
12 TA_M
13 TA_O
41
+
FOCUS PHASE COMPENSATION
+
+
VCC
+
+
+ +
PD1 IV AMP
+ + +
RF SUMMING AMP
+
26 SENS2
VCC
+
IIL TTL
25 SENS1
VCC
24 C. OUT
VEE
+
+
DFCT
23 XRST
VEE LEVEL S
FOK
+ +
VEE 22 DATA
+ +
VCC
MIRR
IIL TTL
TTL IIL
21 XLT
20 CLK
IIL DATA REGISTER INPUT SHIFT REGISTER ADDRESS DECODER SENS SELECTOR OUTPUT DECODER VCC
19 LOCK
18 VCC
DFCTO
IFB1-6 BAL1-4 TOG1-4
FS1-4
TG1-2
TM1-7
PS1-4 ISET 17 ISET
VCC TM4 TM6
VCC 16 SL_O
15 SL_M VCC FS1 TM7 TM3 TM5 14 SL_P TM2
+
IC52, 301
OUT1 1
BA6287F (RF BOARD, MAIN BOARD)
8 GND
VM 2
7 OUT2
DRIVER TSD
DRIVER
VCC 3
CONTROL LOGIC
6 VREF
POWER SAVE FIN 4 5 RIN
IC101 CXD2530Q (MAIN BOARD)
MNT0 MNT1 MNT3 XROF C2PO RFCK GFS XPCK XUGF GTOP VDD VSS TES4 BCK TES3 PCMD TES9 WFCK TES5 EMPH TES6 VDD VSS EXCK SBSO SCOR DOUT C4M FSTT XTSL
80 79 78 77 76 75 74 73 72
71 70 69 68
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC VSS VDD NC TES7 NC VSS XVDD XTAI XTAO XVSS VSS NC TES8 NC VDD VSS NC NC XRST
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50 LRCK 49 WDCK 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 ASYE ASYO ASYI BIAS RF AVDD CLTV AVSS FILI FILO PCO VCTL V16M VCKI VPCO1 VPCO2 TES1 TES0
ERROR CORRECTOR EFM DEMODULATOR
D/A INTERFACE
ASYMMETRY CORRECTOR
16K RAM
DIGITAL OUT
DIGITAL PLL
SUB CODE PROCESSOR
OSC
CLOCK GENERATOR TIMING LOGIC SERVO AUTO SEQUENCER
CPU INTERFACE
DIGITAL CLV
1 2 3 4 5 6
VDD VSS LMUT RMUT TES2 CKOUT
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
XLTO CLKO SPOA SPOB SPOC SPOD XLON FOK VDD VSS MON MDP MDS LOCK PWMI SQCK SQSO SENS DATA XLAT CLOK SEIN CNIN DATO
IC102 SM5852FS-E2 (MAIN BOARD)
LRCI 1 BCKI 2 DI 3
INPUT INTERFACE
DIGITAL SIGNAL PROCESSOR
16 15 14 13
DB/DS MOD2 MOD1 OPT
CLK 4 VSS 5 RSTN 6 TESTN 7 MUTEN 8
SYSTEM CLOCK
12 VDD
SEQUENTIAL CONTROL MUTE CONTROL
OUTPUT INTERFACE
11 LRCO 10 BCKO 9 DOUT
MODE CONTROL
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IC202
AT24C16N-10SI-TR (MAIN BOARD)
START CYCLE START/ STOP LOGIC CONTROL LOGIC
LOAD INC
IC302
VCC 8 NC 7 6
BA8272F-E2 (MAIN BOARD)
DATA OUT LINK OFF CLK OUT DATA IN BUS ON RESET
14
VCC
H.V. GENERATOR TIMING & CONTROL
13
12
11
10
9
8
SCL X DECODER EEPROM 128 x 16 x 8
SLAVE ADDRESS REGISTER & COMPARATOR A0 1 A1 2 A2 3
RESET SWITCH
4
16
16
BUS CLK
BUS ON OUT
BUS ON IN
VREF
BUS DATA
DEVICE ADDRESS BITS
4 R/W
Y DECODER 8 CK 8
4 VSS D OUT ACK
D IN
D OUT DATA REGISTER
SDA
5
IC401
CXD2522Q (MAIN BOARD)
XEMP SDTO XSOE SCK SDTI XLT XRDE XWRE SPSL A4 A5 A6 A7 A8 XOE XCAS D2 OSCE VSS
51 50 49 48 47 46 45 44 43
42
41
40 39 38 37 36 35 34 33
XWIH AM4 AM3 AM2 AM1 AM0 VDD XQOK
52 53 54 55 56 57 58 59
CPU I/F
ADDRESS MONITOR WRITE BASE COUNTER READ BASE COUNTER VWA DRAM I/F
32 31 30 29 28 27 26 25 24 23 22
D3 D0 D1 XWE XRAS A9 VDD A0 A1 A2 A3
SELECTOR TIMING GEN. GSCR 60 SCOR 61 NC 62 NC 63 NC 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 DATA LINKING CONTROL DSP I/F
21 C176
DAC I/F
DIGITAL OUT
20 DOUT
GRST XRST WFCK DIN C4M XROI RFCK GTOP
BCKI VSS DATI LRCI WDCI TEST XTAO
XTAI
BCK DATA LRCK
43
BUS RESET
GND
WORD ADDRESS COUNTER
1
2
3
4
5
6
7
IC402
MB814400C-70PFTN
CLOCK OSC D1 1 D2 2 INPUT BUFFER XWE 3 XRAS 4 A9 5 NC 6 NC 7 NC 8 A0 9 ADDRESS BUFFER A1 10 A2 11 A3 12 VDD 13 ROW DECODER SENSE REFRESH AMP INPUT/OUTPUT CONTROL SWITCH OUTPUT BUFFER A0A9 COLUMN DECODER 26 GND 25 D4 24 D3 23 XCAS 22 XOE 21 NC 20 NC 19 NC 18 A8 17 A7 16 A6 15 A5 14 A4
A0A9
MEMORY CELL
IC601 TC9464FN-EL (MAIN BOARD)
(EMP) SH LRCK DATA GNDX ZD (SM) ATT (BS) LA BCK HS MCK GNDD VDX XO XI
24 23 22
21
20
19
18
17
16
15
14 13
INTERFACE CIRCUIT
MICROCOMPUTER INTERFACE CIRCUIT
OSC
DIGITAL FILTER CIRCUIT ATTENUATOR OPERATIONAL CIRCUIT DEEMPHASIS FILTER CIRCUIT D- MODULATION CIRCUIT
TIMING GENERATOR
TEST CIRCUIT
OUTPUT CIRCUIT ANALOG FILTER
OUTPUT CIRCUIT ANALOG FILTER
1
VDD
2
T1
3 4
P/S VDA
5
RO
6
GNDA
7
VR
8
GNDA
9
LO
10 11 12
VDA
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7-8. IC PIN FUNCTION DESCRIPTION
· MAIN BOARD IC201 CXP84332-088Q (SYSTEM CONTROLLER) Pin No. 1 to 3 4 5 6 7 8 9 10 11 12 13 to 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Pin Name -- CH.F CH.R LOAD2 LOAD1 SENS2 LIM.SW EE.INIT EE.CLK EE.DATA -- SINGLE XRST FOK SENS GFS GRSRT XQOK SDTI XSOE ESPXLT RST EXTAL XTAL VSS TX TEX AVSS AVREF MCK EHS H.TEMP XRDE XWRE A.MUTE EMP ML GRSCOR D/A.RESET I/O O O O I I I I I O I/O O I O I I I O O I O O I I O -- O I -- I I I I O O O O O I O Not used (open) Motor drive signal (load chucking direction) output to the chucking motor drive (IC52) *1 Motor drive signal (save direction) output to the chucking motor drive (IC52) *1 Chucking end detect switch (SW11) input "L": When completion of the disc chucking operation Save end detect switch (SW12) input "L": When completion of the disc chucking operation Internal status signal (sense signal) input from the CXA1992AR (IC11) Sled limit in detect switch (SW1) input "L": When the optical pick-up is inner position Initialize signal input for the EEPROM (IC202) "H": format Fixed at "L" in this set Serial data transfer clock signal output to the EEPROM (IC202) Two-way data bus with the EEPROM (IC202) Not used (open) Setting terminal for the single disc/multiple discs mode "L": single mode, "H": multiple discs mode (fixed at "H") System reset signal output to the CXA1992AR (IC11), CXD2530Q (IC101) and SM5852FS (IC102) "L": reset Focus OK signal input from the CXA1992AR (IC11) "L": NG, "H": OK Internal status signal (sense signal) input from the CXD2530Q (IC101) Guard frame sync signal input from the CXD2530Q (IC101) "L": NG, "H": OK Reset signal output to the CXD2522Q (IC401) "L": reset Subcode Q OK pulse signal output to the CXD2522Q (IC401) "L" active ESP status signal input from the CXD2522Q (IC401) ESP status read enable signal output to the CXD2522Q (IC401) "L" active ESP latch pulse signal output to the CXD2522Q (IC401) "L" active System reset signal input from the SONY bus interface (IC302) and reset signal generator (IC304) "L": reset For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H" Main system clock input terminal (8 MHz) Main system clock output terminal (8 MHz) Ground terminal Sub system clock output terminal Not used (open) Sub system clock input terminal Not used (fixed at "L") Ground terminal (for A/D converter) Reference voltage (+5V) input terminal (for A/D converter) Input of signal for the fine adjustment (linear position sensor adjustment; RV201) of elevator position (A/D input) Elevator height position detect input from the RV202 (elevator height sensor) (A/D input) High temperature sensor input terminal Not used (open) D-RAM read enable signal output to the CXD2522Q (IC401) "L" active D-RAM write enable signal output to the CXD2522Q (IC401) "L" active Audio line muting on/off control signal output terminal "H": muting on Emphasis mode output to the D/A converter (IC601) "H": emphasis on Fast speed dubbing control signal output to the D/A converter (IC601) "L": fast speed Subcode sync (S0+S1) detection signal input from the CXD2522Q (IC401) Reset signal output terminal "L": reset Not used (open) Function
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Pin No. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Pin Name SCK SI SO SCLK SUBQ -- C.OUT BUS.ON A/D.SW MGLK ELV.F -- MAG.SW BU.CHK W.UP SCOR EJECT CD.CLK CD.XLT CD.DATA CD.ON ELV.ON ELV.R -- VDD NC (VDD) MODE1 MODE2 REQ CCCLK CSI CSO ADJ
I/O I I O O I O I I O I O O I I I I I O O O O O O O -- -- O O O O O O O
Function Serial data transfer clock signal input from the SONY bus interface (IC302) Serial data input from the SONY bus interface (IC302) Serial data output to the SONY bus interface (IC302) Subcode Q data reading clock signal output to the CXD2530Q (IC101) Subcode Q data input from the CXD2530Q (IC101) Not used (open) Track number count signal input from the CXA1992AR (IC11) Bus on/off control signal input from the SONY bus interface (IC302) "H": bus on Analog/digital out selection signal output terminal "L": digital out Not used (open) Magazine eject operation completion detect switch (SW201) input "L": eject completed Motor drive signal (elevator up direction) output to the elevator motor drive (IC301) *2 Not used (open) Magazine in/out detect switch (SW202) input "L": magazine detected Battery detection signal input terminal "H": battery on Bus on or eject switch (SW301) input terminal "H": bus on or eject switch pushing Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101) Eject switch (SW301) input terminal "H" active Serial data transfer clock signal output to the CXD2530Q (IC101) and CXD2522Q (IC401) Serial data latch pulse signal output to the CXD2530Q (IC101) Serial data output to the CXD2530Q (IC101) and CXD2522Q (IC401) D/A converter and servo section power supply on/off control signal output "H": power on Mechanism deck section power supply on/off control signal output "H": power on Motor drive signal (elevator down direction) output to the elevator motor drive (IC301) *2 Not used (open) Power supply terminal (+5V) Connected to the power supply (+5V) D-BASS control signal output to the SM5852FS (IC102) "L" active D-BASS control signal output to the SM5852FS (IC102) "L" active Data request signal output terminal Not used (open) Command clock signal output terminal Not used (open) Command data input terminal Not used (open) Command data output terminal Not used (open) Auto adjust selection terminal Not used (open)
*1 chucking motor (M103) control MODE STOP TERMINAL CH.F (pin 4) CH.R (pin 5) "H" "H"
LOAD CHUCKING "L" "H"
SAVE "H" "L"
BRAKE "L" "L"
*2 elevator motor (M104) control MODE STOP TERMINAL ELV.F (pin %·) ELV.R (pin &º) "H" "H"
ELEVATOR ELEVATOR UP DOWN "L" "H" "H" "L"
BRAKE "L" "L"
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