Text preview for : CDX-600.pdf part of Sony CDX-600 CDX-600
Back to : CDX-600.rar | Home
CDX-600/606/626
SERVICE MANUAL
US Model
CDX-600/606
Canadian Model AEP Model UK Model
CDX-600
E Model
CDX-626
Photo: CDX-600
Model Name Using Similar Mechanism CD Drive Mechanism Type Optical Pick-up Name
CDX-505RF MG-250C-137 KSS-521A/J2N
SPECIFICATIONS
COMPACT DISC CHANGER
MICROFILM
CDX-600/606/626
7-3.
SCHEMATIC DIAGRAM RF Section
· See page 18 for Waveforms.
· See page 31 for IC Block Diagrams.
(Page 27)
The components identified by mark ! or dotted line with mark ! are critical for safety. Replace only with part number specified.
Les composants identifiés par une marque ! sont critiques pour la sécurité. Ne les remplacer que par une piéce portant le numéro spécifié.
21
22
CDX-600/606/626
7-6. SCHEMATIC DIAGRAM MAIN Section (1/2) · See page 18 for Waveforms. · See page 33 for IC Block Diagrams.
(Page 22)
27
28
CDX-600/606/626
7-7. SCHEMATIC DIAGRAM MAIN Section (2/2) · See page 18 for Waveforms. · See page 33 for IC Block Diagrams.
29
30
· IC Block Diagrams RF Board IC11 CXA1992BR
RFTC RF M PD1 RF O CC1 PD2 PD CP CB CC2 LD FOK RF I
IC52
OUT1 1
BA6287F
8 GND
39
38
37
36
35
34
33 32
31 30
29
28
27
VM 2 7 OUT2
PD 2 I-V AMP
PD 1 I-V AMP
PD AMP
LD AMP
RF SUMMING AMP
DRIVER
DRIVER
FOCUS OK COMPARATOR
VCC 3
TSD
VCC
CONTROL LOGIC
6 VREF
IFB1 IFB6
LASER POWER CONTROL PEAK/BOTTOM HOLD MIRR COMPARATOR DEFECT AMP IIL TTL
POWER SAVE FIN 4 5 RIN
FE 40 BIAS FOCUS BIAS WINDOW COMPARATOR FOH FOL
PEAK/BOTTOM HOLD
LDON
LPCL
TGFL
MIRR
DFCT1
VEE F 41 F I-V AMP E I-V AMP TGFL
FOCUS ERROR AMP
LPC
CC1
E 42 EI 43 VEE 44 TEO 45
TRACKING GAIN WINDOW COMPARATOR
TGH TGL BALH BALL ATSC IIC DATA REGISTER, INPUT SHIFT REGISTER, ADDRESS DECODER, SENSE SELECTOR, OUTPUT DECODER
IIL TTL
26 SENS2 25 SENS1 24 C. OUT
MAIN Board IC101 CXD2530Q
MNT0 MNT1 MNT3 XROF C2PO RFCK GFS XPCK XUGF GTOP VDD VSS TES4 BCK TES3 PCMD TES9 WFCK TES5 EMPH TES6 VDD VSS EXCK SBSO SCOR DOUT C4M FSTT XTSL
VEE TOG1 TOG4 BAL1 BAL4
TTL IIL
23 22 21 20 19
XRST DATA XLT CLK LOCK
80 79 78 77 76 75 74 73 72 E-F BALANCE WINDOW COMPARATOR ATSC WINDOW COMPARATOR TZC COMPARATOR TM1 TZC FZC
71 70 69 68
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
TG1 TG2
IFB1 IFB6 BAL1 BAL4 TOG1 TOG4
TM1 TM7
PS1 PS4
FS1 FS4
DFCTO
LPFI 46 TEI 47 ATSC 48
VCC VCC ISET
18 VCC NC VSS VDD NC TES7 NC VSS XVDD XTAI XTAO XVSS VSS NC TES8 NC VDD VSS NC NC XRST 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 LRCK 49 WDCK 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 ASYE ASYO ASYI BIAS RF AVDD CLTV AVSS FILI FILO PCO VCTL V16M VCKI VPCO1 VPCO2 TES1 TES0
TM6
17 ISET
TZC 49
16 SL O 15 SL M TRACKING PHASE COMPENSATION
ERROR CORRECTOR EFM DEMODULATOR
D/A INTERFACE
ASYMMETRY CORRECTOR
DFCT TDFCT 50 TG1
VCC CENTER VOLTAGE GENERATOR FZC COMPARATOR FOCUS PHASE COMPENSATION VCC VEE CHARGE UP FS1
TM5
14 SL P TM2
16K RAM
DIGITAL OUT
DIGITAL PLL
VEE VCC TM7 TM4
VC 51 FZC 52
DFCT
FS4
FS2 FSET
VDD VSS LMUT RMUT TES2 CKOUT
VEE 1 FEO 2 FEI 3 FDFCT 4 FGD 5 FLB 6 FE O 7 FE M 8 SRCH 9 TGU 10 TG2 11 FSET 12 TA M
VEE 13 TA O
31
XLTO CLKO SPOA SPOB SPOC SPOD XLON FOK VDD VSS MON MDP MDS LOCK PWMI
SQCK SQSO SENS DATA XLAT
CLOK SEIN CNIN DATO
TG2
TM3
+ +
SUB CODE PROCESSOR
OSC
CLOCK GENERATOR TIMING LOGIC SERVO AUTO SEQUENCER
CPU INTERFACE
DIGITAL CLV
1 2 3 4 5 6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
32
IC204
BUS ON VCC
BA8272F-E2
DATA OUT LINK OFF CLK OUT DATA IN RESET
IC301
OUT1 1
BA6287F
8 GND
14
13
12
11
10
9
8
RESET SWITCH
VM 2
7 OUT2
DRIVER TSD
1 2 3 4 5 6 7
DRIVER
BUS CLK
BUS ON OUT
BUS ON IN
VREF
BUS DATA
BUS RESET
GND
VCC 3
CONTROL LOGIC
6 VREF
POWER SAVE FIN 4 5 RIN
IC401
LRCK
TC9464FN-EL
(EMP) SH DATA GNDX ZD (SM) ATT (BS) LA BCK HS MCK GNDD VDX XO
16
24 23 22
21
20
19
18
17
15
XI VDA
14 13
INTERFACE CIRCUIT
MICROCOMPUTER INTERFACE CIRCUIT
OSC
DIGITAL FILTER CIRCUIT ATTENUATOR OPERATIONAL CIRCUIT DEEMPHASIS FILTER CIRCUIT D- MODULATION CIRCUIT
TIMING GENERATOR
TEST CIRCUIT
OUTPUT CIRCUIT ANALOG FILTER
OUTPUT CIRCUIT ANALOG FILTER
1
2
3 4
5
6
7
8
9
10 11 12
GNDA
GNDA
VDD
P/S VDA
RO
VR
LO
T1
33
7-8. IC PIN FUNCTION DESCRIPTION
· MAIN BOARD IC302 CXP84124-080Q (SYSTEM CONTROLLER) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 to 23 24 25 to 29 30 31 32 33 34 35 36 37 38 39 40 41 to 47 48 49 50 51 52 53 54 55 Pin Name LIM.SW BUSON EJECT LOAD1 LOAD2 A.MUTE EMPH CH.R CH.F -- ELV.R ELV.ON CD RST CDON -- AUTO ON/OFF -- RESET EXTAL XTAL VSS TX TEX AVSS AVREF ATRIBT MCK EHS -- SCK SI SO SQCLK SUBQ -- -- MGLK I/O I I I I I O O O O O O O O O O I O I I O -- O I -- I I I I O I I O O I O I I Function Sled limit in detect switch (SW1) input terminal "L": When the optical pick-up is inner position Bus on/off control signal input from the SONY bus interface (IC204) "H": bus on Eject switch (SW303) input terminal "H" active Save end detect switch (SW12) input terminal "L": When completion of the disc chucking operation Chucking end detect switch (SW11) input terminal "L": When completion of the disc chucking operation Audio line muting on/off control signal output terminal "H": muting on Emphasis mode output to the D/A converter (IC401) "L": emphasis on Motor drive signal (save direction) output to the chucking motor drive (IC52) "H" active *1 Motor drive signal (load chucking direction) output to the chucking motor drive (IC52) "H" active *1 Not used (open) Motor drive signal (elevator down direction) output to the elevator motor drive (IC301) "L" active *2 Mechanism deck section power supply on/off control signal output "H": power on System reset signal output to the CXA1992BR (IC11) and CXD2530Q (IC101) "L": reset D/A converter and servo section power supply on/off control signal output "H": power on Not used (open) Setting terminal for the automatic adjustment "L": automatic adjustment, "H": manual adjustment (fixed at "L" in this set) Not used (open) System reset signal input from the reset signal generator (IC202) and SONY bus interface (IC204) "L": reset For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H" Main system clock input terminal (8 MHz) Main system clock output terminal (8 MHz) Ground terminal Sub system clock output terminal Not used (open) Sub system clock input terminal Not used (fixed at "L") Ground terminal (for A/D converter) Reference voltage (+5V) input terminal (for A/D converter) Selection input of the custom file, D-BASS, etc. Input of signal for the fine adjustment (linear position sensor adjustment; RV301) of elevator position (A/D input) Elevator height position detect input from the RV302 (elevator height sensor) (A/D input) Not used (open) Serial data transfer clock signal input from the SONY bus interface (IC204) Serial data input from the SONY bus interface (IC204) Serial data output to the SONY bus interface (IC204) Subcode Q data reading clock signal output to the CXD2530Q (IC101) Subcode Q data input from the CXD2530Q (IC101) Not used (open) Not used (fixed at "H") Magazine eject operation completion detect switch (SW301) input terminal "L": eject completed
34
Pin No. 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 to 80
Pin Name SCOR SENS2 PWM -- MAG.SW BUCHECK W.UP C.OUT EEDATA EECLK EEINIT -- SINGLE FOK GFS SENS1 VDD NC (VDD) CDCLK CDXLT CDDATA --
I/O I I O O I I I I I/O O I O I I I I -- -- O O O O
Function Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101) Internal status signal (sense signal) input from the CXA1992BR (IC11) Motor drive signal (elevator up direction) output to the elevator motor drive (IC301) "L" active *2 Not used (open) Magazine in/out detect switch (SW302) input terminal "L": magazine detected Battery detection signal input terminal "H": battery on Bus on or eject switch (SW303) input terminal "H": bus on or eject switch pushing Track number count signal input from the CXA1992BR (IC11) Two-way data bus with the EEPROM Not used (open) Serial clock signal output to the EEPROM Not used (open) Initialize signal input for the EEPROM "H": format Fixed at "L" in this set Not used (open) Setting terminal for the single disc/multiple discs mode "L": single mode, "H": multiple discs mode (fixed at "H") Focus OK signal input from the CXA1992BR (IC11) "L": NG, "H": OK Guard frame sync signal input from the CXD2530Q (IC101) "L": NG, "H": OK Internal status signal (sense signal) input from the CXD2530Q (IC101) Power supply terminal (+5V) Connected to the power supply (+5V) Serial data transfer clock signal output to the CXD2530Q (IC101) Serial data latch pulse signal output to the CXD2530Q (IC101) Serial data output to the CXD2530Q (IC101) Not used (open)
*1 chucking motor (M103) control Mode Terminal CH.F (pin 9) CH.R (pin 8) STOP "L" "L" LOAD CHUCKING "H" "L" SAVE "L" "H" BRAKE "H" "H"
*2 elevator motor (M104) control Mode Terminal PWM (pin %·) ELV.R (pin !¡) STOP "H" "H" ELEVATOR ELEVATOR UP DOWN "L" "H" "H" "L" BRAKE "L" "L"
35