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TV signal processor-Teletext
decoder with embedded m-Cont
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INTEGRATED CIRCUITS
DEVICE SPECIFICATION DATA SHEET
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TDA935X/6X/8X series TV signal processor-Teletext decoder with embedded µ-Controller
Preliminary Device Specification File under Integrated Circuits, Version: 1.3 1999 Sep 28 Previous date: 1999 Aug 26
Philips Semiconductors
Preliminary Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
GENERAL DESCRIPTION The various versions of theTDA935X/6X/8X series combine the functions of a TV signal processor together with a µ-Controller and US Closed Caption decoder. Most versions have a Teletext decoder on board. The Teletext decoder has an internal RAM memory for 1or 10 page text. The ICs are intended to be used in economy television receivers with 90° and 110° picture tubes. The ICs have supply voltages of 8 V and 3.3 V and they are mounted in S-DIP envelope with 64 pins. The features are given in the following feature list. The differences between the various ICs are given in the table on page 4.
TDA935X/6X/8X series
FEATURES TV-signal processor · Multi-standard vision IF circuit with alignment-free PLL demodulator · Internal (switchable) time-constant for the IF-AGC circuit · A choice can be made between versions with mono intercarrier sound FM demodulator and versions with QSS IF amplifier. · The mono intercarrier sound versions have a selective FM-PLL demodulator which can be switched to the different FM sound frequencies (4.5/5.5/6.0/6.5 MHz). The quality of this system is such that the external band-pass filters can be omitted. · Source selection between `internal' CVBS and external CVBS or Y/C signals · Integrated chrominance trap circuit · Integrated luminance delay line with adjustable delay time · Asymmetrical `delay line type' peaking in the luminance channel · Black stretching for non-standard luminance signals · Integrated chroma band-pass filter with switchable centre frequency · Only one reference (12 MHz) crystal required for the µ-Controller, Teletext- and the colour decoder · PAL/NTSC or multi-standard colour decoder with automatic search system · Internal base-band delay line 1999 Sep 28 2 · RGB control circuit with `Continuous Cathode Calibration', white point and black level off set adjustment so that the colour temperature of the dark and the light parts of the screen can be chosen independently. · Linear RGB or YUV input with fast blanking for external RGB/YUV sources. The Text/OSD signals are internally supplied from the µ-Controller/Teletext decoder · Contrast reduction possibility during mixed-mode of OSD and Text signals · Horizontal synchronization with two control loops and alignment-free horizontal oscillator · Vertical count-down circuit · Vertical driver optimized for DC-coupled vertical output stages · Horizontal and vertical geometry processing · Horizontal and vertical zoom function for 16 : 9 applications · Horizontal parallelogram and bow correction for large screen picture tubes · Low-power start-up of the horizontal drive circuit
Philips Semiconductors
Preliminary Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
µ-Controller · 80C51 µ-controller core standard instruction set and timing · 1 µs machine cycle · 32 - 128Kx8-bit late programmed ROM · 3 - 12Kx8-bit Auxiliary RAM (shared with Display and Acquisition) · Interrupt controller for individual enable/disable with two level priority · Two 16-bit Timer/Counter registers · WatchDog timer · Auxiliary RAM page pointer · 16-bit Data pointer · IDLE and Power Down (PD) mode · 14 bits PWM for Voltage Synthesis Tuning · 8-bit A/D converter · 4 pins which can be programmed as general I/O pin, ADC input or PWM (6-bit) output Data Capture · Text memory for 1 or 10 pages · In the 10 page versions inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT) and Subtitle Page Table (SPT) · Data Capture for US Closed Caption · Data Capture for 525/625 line WST, VPS (PDC system A) and Wide Screen Signalling (WSS) bit decoding · Automatic selection between 525 WST/625 WST · Automatic selection between 625 WST/VPS on line 16 of VBI · Real-time capture and decoding for WST Teletext in Hardware, to enable optimized µ-processor throughput · Automatic detection of FASTEXT transmission · Real-time packet 26 engine in Hardware for processing accented, G2 and G3 characters · Signal quality detector for video and WST/VPS data types · Comprehensive teletext language coverage · Full Field and Vertical Blanking Interval (VBI) data capture of WST data Display
TDA935X/6X/8X series
· Teletext and Enhanced OSD modes · Features of level 1.5 WST and US Close Caption · Serial and Parallel Display Attributes · Single/Double/Quadruple Width and Height for characters · Scrolling of display region · Variable flash rate controlled by software · Enhanced display features including overlining, underlining and italics · Soft colours using CLUT with 4096 colour palette · Globally selectable scan lines per row (9/10/13/16) and character matrix [12x10, 12x13, 12x16 (VxH)] · Fringing (Shadow) selectable from N-S-E-W direction · Fringe colour selectable · Meshing of defined area · Contrast reduction of defined area · Cursor · Special Graphics Characters with two planes, allowing four colours per character · 32 software redefinable On-Screen display characters · 4 WST Character sets (G0/G2) in single device (e.g. Latin, Cyrillic, Greek, Arabic) · G1 Mosaic graphics, Limited G3 Line drawing characters · WST Character sets and Closed Caption Character set in single device
1999 Sep 28
3
FUNCTIONAL DIFFERENCE BETWEEN THE VARIOUS IC VERSIONS
1999 Sep 28 4
Philips Semiconductors
TV signal processor-Teletext decoder with embedded µ-Controller
IC VERSION (TDA) TV range Mono intercarrier multi-standard sound demodulator (4.5 - 6.5 MHz) with switchable centre frequency Audio switch Automatic Volume Levelling Automatic Volume Levelling or subcarrier output (for comb filter applications) QSS sound IF amplifier with separate input and AGC circuit AM sound demodulator without extra reference circuit PAL decoder SECAM decoder NTSC decoder Horizontal geometry (E-W) Horizontal and Vertical Zoom ROM size User RAM size Teletext Closed captioning
9350 9351 9352 9353 9360 9361 9362 9363 9364 9365 9366 9367 9380 9381 9382 9383 9384 9385 9386 9387 9388 90° 90° 90° 110° 90° 90° 110° 110° 110° 110° 90° 90° 90° 90° 90° 110° 110° 110° 110° 90° 110°
32- 32- 32- 32- 32- 32- 64- 64- 64- 64- 64- 64- 16- 16- 16- 16- 16- 16- 16- 16- 1664 k 64 k 64 k 64 k 64 k 64 k 128k 128k 128k 128k 128k 128k 64 k 64 k 64 k 64 k 64 k 64 k 64 k 64 k 64 k 1k 1k 1k 1k 2k 2k 2k 2k 2k 2k 2k 2k 1k 1k 1k 1k 1k 1k 1k 1k 1k 1 1 1 1 10 10 10 10 10 10 10 10 page page page page page page page page page page page page
TDA935X/6X/8X series
Preliminary Device Specification
Philips Semiconductors
Preliminary Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
QUICK REFERENCE DATA SYMBOL Supply VP IP Input voltages ViVIFrms) ViSIF(rms) ViAUDIO(rms) ViCVBS(p-p) ViCHROMA(p-p) ViRGB(p-p) ViYIN(p-p) ViUVIN(p-p) Vo(IFVO)(p-p) Vo(QSSO)(rms) video IF amplifier sensitivity (RMS value) QSS sound IF amplifier sensitivity (RMS value) external audio input (RMS value) external CVBS/Y input (peak-to-peak value) external chroma input voltage (burst amplitude) (peak-to-peak value) RGB inputs (peak-to-peak value) luminance input signal (peak-to-peak value) U/V input signal (peak-to-peak value) - - - - - - - - - - - 0 - 10 1 1.2 supply voltages supply current - - PARAMETER
TDA935X/6X/8X series
MIN.
TYP. - - - - - - - - -
MAX.
UNIT
8.0/3.3 tbf
V mA µV µV mV V V V V V
35 60 500 1.0 0.3 0.7 1.4
1.33/1.05 - 2.5 100 500 - 2.0 - - - - - - 5 - - - -
Output signals demodulated CVBS output (peak-to-peak value) sound IF intercarrier output in QSS versions (RMS value) V mV mV mA V mA mA mA
Vo(AMOUT)(rms) demodulated AM sound output in QSS versions (RMS value) Io(AGCOUT) VoRGB(p-p) IoHOUT IoVERT IoEWD tuner AGC output current range RGB output signal amplitudes (peak-to-peak value) horizontal output current vertical output current (peak-to-peak value) EW drive output current
1999 Sep 28
5
SNDIF
RESET
VPE
LED OUT (2x) SCL SDA
VST OUT
AUDEXT
AUDOUT
Philips Semiconductors
TUNERAGC 10/11 (20) 29 28 (32) 35 1+62-64 DEEMPHASIS ENHANCED 1/10 PAGE MEMORY 80C51 CPU VST PWM-DAC I/O PORTS AUDIO SWITCH (AVL) VOLUME CONTROL I2C-BUS TRANSCEIVER 5-8 (32) 31 60 55 59 58 57 3 4 9 44 2 12 54 56 61
27
37
38
23
IFIN
24
VISION IF ALIGNMENT-FREE PLL DEMOD. AGC/AFC VIDEO AMP.
ADC IN (4x)
I/O PORTS (4x)
1999 Sep 28
+3.3 V H CVBS ROM/RAM ACQUISITION V TELETEXT TELETEXT/OSD DISPLAY AGC CIRCUIT NARROW BAND PLL DEMODULATOR SYNC REF BASE-BAND DELAY LINE LUMA DELAY PEAKING BLACK STRETCH COR R G B BL CONTR/BRIGHTN OSD/TEXT INSERT CCC WHITE-P. ADJ. R G B H-DRIVE V-DRIVE + V (EW GEOMETRY) GEOMETRY U V 34 16 33 25 26 22 21 36 (20) 46 47 48 45 2nd LOOP H H-SHIFT RGB/YUV INSERT Y RGB/YUV MATRIX SATURATION YUV/RGB MATRIX 51 52 53 49 50 RO GO B0 BCLIN BLKIN HOUT V-DRIVE EHTO EWD R/V G/Y B/U BL
BLOCK DIAGRAM
SOUND TRAP
40
VIDEO SWITCH
CVBS/Y
42
VIDEO IDENT.
CHROMA 43
VIDEO FILTERS
REF
TV signal processor-Teletext decoder with embedded µ-Controller
6
13
PAL/SECAM/NTSC DECODER (32)
30
41
18
+8V
39
H/V SYNC SEP.
14
H-OSC. + PLL
19
15
17
TDA935X/6X/8X series
Preliminary Device Specification
Fig. 1 Block diagram TDA935X/6X8X with mono intercarrier sound demodulator
AUDEXT
SIFIN
RESET
VPE
LED OUT (2x) SCL SDA
VST OUT
QSSOUT/AMOUT
AMOUT
Philips Semiconductors
TUNERAGC (20) 10/11 (35) 44 (32) 31 60 55 59 1+62-64 58 57 3 4 9 ENHANCED 10 PAGE MEMORY 80C51 CPU VST PWM-DAC I/O PORTS I2C-BUS TRANSCEIVER 5-8 (35) QSS SOUND IF AGC QSS MIXER AM DEMODULTOR REF LUMA DELAY PEAKING ROM/RAM ACQUISITION BLACK STRETCH SYNC REF BASE-BAND DELAY LINE CVBS TELETEXT V H TELETEXT/OSD DISPLAY 28 29 2 12 54 56 61
27
37
38
23
IFIN
24
VISION IF ALIGNMENT-FREE PLL DEMOD. AGC/AFC VIDEO AMP.
40
VIDEO SWITCH
CVBS/Y
42
VIDEO IDENT.
CHROMA 43
VIDEO FILTERS
ADC IN (4x)
I/O PORTS (4x)
1999 Sep 28
+3.3 V COR R G B BL CONTR/BRIGHTN OSD/TEXT INSERT CCC WHITE-P. ADJ. R G B H-DRIVE V-DRIVE + V EW GEOMETRY GEOMETRY U V 34 16 33 25 26 22 21 36 (20) 2nd LOOP H H-SHIFT RGB/YUV INSERT Y RGB/YUV MATRIX SATURATION YUV/RGB MATRIX 46 47 48 45 51 52 53 49 50 RO GO BO BCLIN BLKIN HOUT V-DRIVE EHTO EWD R/V G/Y B/U BL
SOUND TRAP
TV signal processor-Teletext decoder with embedded µ-Controller
7
13
PAL/SECAM/NTSC DECODER (32)
30
41
18
+8V
39
H/V SYNC SEP.
14
H-OSC. + PLL
19
15
17
TDA935X/6X/8X series
Preliminary Device Specification
Fig. 2 Block diagram TDA 936X with QSS IF sound channel
Philips Semiconductors
Preliminary Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
PINNING SYMBOL P1.3/T1 P1.6/SCL P1.7/SDA P2.0/TPWM P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 VSSC/P P0.5 P0.6 VSSA SECPLL VP2 DECDIG PH2LF PH1LF GND3 DECBG AVL/EWD (1) VDRB VDRA IFIN1 IFIN2 IREF VSC TUNERAGC AUDEEM/SIFIN1(1) DECSDEM/SIFIN2(1) GND2 SNDPLL/SIFAGC(1) AVL/SNDIF/REF0/ AMOUT(1) HOUT FBISO AUDEXT/ QSSO/AMOUT(1) EHTO PLLIF IFVO/SVO VP1 CVBSINT GND1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
TDA935X/6X/8X series
DESCRIPTION port 1.3 or Counter/Timer 1 input port 1.6 or I2C-bus clock line port 1.7 or I2C-bus data line port 2.0 or Tuning PWM output port 3.0 or ADC0 input port 3.1 or ADC1 input port 3.2 or ADC2 input port 3.3 or ADC3 input digital ground for µ-Controller core and periphery port 0.5 (8 mA current sinking capability for direct drive of LEDs) port 0.6 (8 mA current sinking capability for direct drive of LEDs) analog ground of Teletext decoder and digital ground of TV-processor SECAM PLL decoupling 2nd supply voltage TV-processor (+8V) decoupling digital supply of TV-processor phase-2 filter phase-1 filter ground 3 for TV-processor bandgap decoupling Automatic Volume Levelling /East-West drive output vertical drive B output vertical drive A output IF input 1 IF input 2 reference current input vertical sawtooth capacitor tuner AGC output audio deemphasis or SIF input 1 decoupling sound demodulator or SIF input 2 ground 2 for TV processor narrow band PLL filter /AGC sound IF Automatic Volume Levelling / sound IF input / subcarrier reference output /AM output (non controlled) horizontal output flyback input/sandcastle output external audio input /QSS intercarrier out /AM audio output (non controlled) EHT/overvoltage protection input IF-PLL loop filter IF video output / selected CVBS output main supply voltage TV-processor (+8 V) internal CVBS input ground 1 for TV-processor
1999 Sep 28
8
Philips Semiconductors
Preliminary Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
SYMBOL CVBS/Y CHROMA AUDOUT /AMOUT(1) INSSW2 R2/VIN G2/YIN B2/UIN BCLIN BLKIN RO GO BO VDDA VPE VDDC OSCGND XTALIN XTALOUT RESET VDDP P1.0/INT1 P1.1/T0 P1.2/INT0 Note PIN 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
TDA935X/6X/8X series
DESCRIPTION external CVBS/Y input chrominance input (SVHS) audio output /AM audio output (volume controlled) 2nd RGB / YUV insertion input 2nd R input / V (R-Y) input 2nd G input / Y input 2nd B input / U (B-Y) input beam current limiter input/V-guard input black current input Red output Green output Blue output analog supply of Teletext decoder and digital supply of TV-processor (3.3 V) OTP Programming Voltage digital supply to core (3.3 V) oscillator ground supply crystal oscillator input crystal oscillator output reset digital supply to periphery (+3.3 V) port 1.0 or external interrupt 1 input port 1.1 or Counter/Timer 0 input port 1.2 or external interrupt 0 input
1. The function of pin 20, 28, 29, 31, 32, 35 and 44 is dependent on the IC version (mono intercarrier FM demodulator / QSS IF amplifier and East-West output or not) and on some software control bits. The valid combinations are given in table 1. Table 1 Pin functions for various versions FM-PLL version QSS version
IC version
East-West Y/N N Y N Y CMB1/CMB0 bits 00 01/10/11 00 01/10/11 00 01/10/11 00 01/10/11 AM bit - - - - - 0 1 - 0 1 Pin 20 AVL EWD AVL EWD Pin 28 AUDEEM SIFIN1 Pin 29 DECSDEM SIFIN2 Pin 31 SNDPLL SIFAGC REFO AMOUT REFO Pin 32 SNDIF(1) REFO AVL/SNDIF(1) REFO AMOUT Pin 35 AUDEXT AUDEXT QSSO AMOUT AUDEXT QSSO AMOUT Pin 44 AUDOUT controlled AM or audio out Note 1. When additional (external) selectivity is required for FM-PLL system pin 32 can be used as sound IF input. This function is selected by means of SIF bit in subaddress 21H.
1999 Sep 28
9
Philips Semiconductors
Preliminary Device Specification
TV signal processor-Teletext decoder with embedded µ-Controller
TDA935X/6X/8X series
P1.3/T1
handbook, halfpage
1 2 3 4 5 6 7 8 9 10 11 12
64 63 62 61 60 59 58 57 56 55 54 53
P1.2/INT0 P1.1/T0 P1.0/INT1 VDDP RESET XTALOUT XTALIN OSCGND VDDC VPE VDDA BO GO RO BLKIN BCLIN B2/UIN G2/YIN R2/VIN INSSW2 AUDOUT/AMOUT CHROMA CVBS/Y GND1 CVBSINT VP1 IFVO/SVO PLLIF EHTO AUDEXT/QSSO/ AMOUT FBISO HOUT
P1.6/SCL P1.7/SDA P2.0/TPMW P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 VSSC/P P0.5 P0.6 VSSA SECPLL VP2 DECDIG PH2LF PH1LF GND3 DECBG AVL/EWD VDRB VDRA IFIN1 IFIN2 IREF VSC TUNERAGC AUDEEM/SIFIN1 DECSDEM/SIFIN2 GND2 SNDPLL/SIFAGC AVL/SNDIF/ REFO/AMOUT
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TDA935X/6X/8X
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
MXXxxx
XXX
Fig. 3 Pin configuration (SDIP 64)
1999 Sep 28
10
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
TDA 935X/6X/8X series
FUNCTIONAL DESCRIPTION OF THE MICRO-CONTROLLER/TEXT DECODER
Block Diagram
I2C, General I/O
TV Control and Interface
Program ROM (16K to 128K)
Micro Processor (80C51)
SRAM 256 Bytes
DISP/AUX DRAM (3K to 12K)
Memory Interface
R Data Capture G Display B VDS
CVBS
CVBS
Data Capture Timing
Display Timing
V H
Figure 4
Top level architecture
1999 Sep 28
11
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
Microcontroller
TDA 935X/6X/8X series
The functionality of the microcontroller used on the device is described here with reference to the industry standard 80C51 microcontroller. A full description of its functionality can be found in the "80C51 Based 8-Bit Microcontrollers - Philips Semiconductors (ref. IC20)" (Reference [1]) Memory Organisation The device has the capability of a maximum of 128K PROGRAM ROM and 12K DATA RAM internally. ROM BANK SWITCHING Devices with up to 64K Program ROM have a continuous address space. Devices with over 64K Program ROM use ROM bank switching. The 128K version is arranged in four banks of 32K. One of the 32K banks is common and is always addressable. The other three banks(Bank0,Bank1,Bank2) can be accessed by selecting the right bank via the SFR ROMBK bits 1/0.
FFFFH Bank0 32K
FFFFH Bank1 32K
FFFFH Bank2 32K
8000H
8000H
8000H
7FFFH
Common 32K
0000H Figure 5 ROM Bank Switching memory map 0 to 32K Common Common Common Reserved 32K to 64K Bank0 Bank1 Bank2 Reserved
ROMBK<2:0> 00 01 10 11 Table 2
ROM Bank Selection
1999 Sep 28
12
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
Security Bits - Program and Verify
TDA 935X/6X/8X series
TDA935X/6X/8X devices have three sets of security bits, one set for each of the three One Time Programmable memories, i.e. Program ROM, Character ROM and Packet 26 ROM. The security bits are used to prevent the ROM from being overwritten once programmed, and also the contents being verified once programmed. The security bits are one-time programmable and cannot be erased. The TDA935X/6X/8X memory and security bits are structured as shown in Figure 6. The security bits are set as shown in Figure 7 for production programmed devices and are set as shown in Figure 8 for production blank devices.
handbook, full pagewidth MEMORY
SECURITY BITS INTERACTION
USER ROM PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE)
PROGRAM ROM
User Rom USER ROM (128K x 8-Bit) (128K x 12-BIT)
CHARACTER ROM USER ROM PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE)
User Rom USER ROM (9K x 12-Bit) (128K x 12-BIT)
PACKET 26 ROM USER ROM PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE)
User Rom USER ROM (4K x x 12-BIT) (128K 8-Bit)
MBK953
Figure 6
Memory and security bit structures
handbook, full pagewidth MEMORY
SECURITY BITS SET
USER ROM PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE) ENABLED
PROGRAM ROM
DISABLED
CHARACTER ROM
DISABLED
ENABLED
PACKET 26 ROM
DISABLED
ENABLED
MBK954
Figure 7
Security bits for production devices
1999 Sep 28
13
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
TDA 935X/6X/8X series
handbook, full pagewidth MEMORY
SECURITY BITS SET
USER ROM PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE) ENABLED
PROGRAM ROM
ENABLED
CHARACTER ROM
ENABLED
ENABLED
PACKET 26 ROM
ENABLED
ENABLED
MBK955
Figure 8
Security bits for production blank devices
RAM ORGANISATION The Internal Data RAM is organised into two areas, Data Memory and Special Function Registers (SFR's) as shown in Figure 9.
Data Memory
The Data memory is 256 x 8 bits wide (byte) and occupies the address range 00h to 255h when using indirect addressing and 00h to 127h when using Direct addressing. The SFRs occupy the address range 128 to 255 and are accessible using Direct addressing only.
FFH Upper 128 80H 7FH Lower 128 Accessible by Direct and Indirect Addressing 00H Data Memory Special Function Registers Accessible by Indirect Addressing only Accessible by Direct Addressing only
Figure 9
Internal Data Memory
The lower 128 Bytes of Data memory are mapped as shown in Figure 10. The lowest 24 bytes are grouped into 4 banks of 8 registers, the next 16 bytes above the register banks form a block of bit addressable memory space. 1999 Sep 28 14
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
TDA 935X/6X/8X series
7FH
2FH Bank Select Bits in PSW 20H 1FH 11 = BANK3 10 = BANK2 18H 17H 10H 01 = BANK1 0FH 08H 07H 00H 4 Banks of 8 Registers R0 - R7 Bit Addressable Space (Bit Addresses 0-7F)
00 = BANK0
Figure 10
Lower 128 Bytes of Internal RAM
The upper 128 bytes is not allocated for any special area or functions.
SFR Memory
The Special Function Register (SFR) space is used for Port latches, timer, peripheral control, acquisition control, display control, etc. These register can only be accessed by direct addressing. Sixteen of the addresses in the SFR space are both byte and bit-addressable. The bit-addressable SFR's are those whose address ends in 0H or 8H. A summary of the SFR map in address order is shown in Table 3..
ADD
80H 81H 82H 83H 87H 88H 89H 8AH 8BH
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W P0 SP
Names
BIT7
SP<7> DPL<7> DPH<7> 0 TF1 GATE TL0<7> TL1<7>
BIT6
P0<6> SP<6> DPL<6> DPH<6> ARD TR1 C/T TL0<6> TL1<6>
BIT5
P0<5> SP<5> DPL<5> DPH<5> RFI TF0 M1 TL0<5> TL1<5>
BIT4
SP<4> DPL<4> DPH<4> WLE TR0 M0 TL0<4> TL1<4>
BIT3
SP<3> DPL<3> DPH<3> GF1 IE1 GATE TL0<3> TL1<3>
BIT2
SP<2> DPL<2> DPH<2> GF0 IT1 C/T TL0<2> TL1<2>
BIT1
SP<1> DPL<1> DPH<1> PD IE0 M1 TL0<1> TL1<1>
BIT0
SP<0> DPL<0> DPH<0> IDL IT0 M0 TL0<0> TL1<0>
DPL DPH PCON TCON TMOD TL0 TL1
Table 3 1999 Sep 28
SFR Map 15
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
ADD
8CH 8DH 90H 96H 97H 98H 9EH 9FH A0H A6H A7H A8H B0H B2H B3H B4H
TDA 935X/6X/8X series
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Names
TH0 TH1 P1 P0CFGA P0CFGB SADB P1CFGA P1CFGB P2 P2CFGA P2CFGB IE P3 TXT18 TXT19 TXT20
BIT7
TH0<7> TH1<7> P1<7> 0 P1CFGA<7> P1CFGB<7> EA NOT<3> TEN DRCS ENABLE DISP LINE<1> 0 0 0
BIT6
TH0<6> TH1<6> P1<6> P0CFGA<6> P0CFGB<6> 0 P1CFGA<6> P1CFGB<6> EBUSY NOT<2> TC<2> OSD PLANES DISP LINES<0> 0 PBUSY FORCE ACQ<1> 0
BIT5
TH0<5> TH1<5> P0CFGA<5> P0CFGB<5> 0 ES2 NOT<1> TC<1> 0
BIT4
TH0<4> TH1<4> DC COMP ECC NOT<0> TC<0> 0
BIT3
TH0<3> TH1<3> P1<3> SAD<3> P1CFGA<3> P1CFGB<3> ET1 P3<3> 0 0 OSD LANG ENABLE 0
BIT2
TH0<2> TH1<2> P1<2> SAD<2> P1CFGA<2> P1CFGB<2> EX1 P3<2> 0 0 OSD LAN<2> CC ON
BIT1
TH0<1> TH1<1> P1<1> SAD<1> P1CFGA<1> P1CFGB<1> ET0 P3<1> BS<1> TS<1> OSD LAN<1> I2C PORT0
BIT0
TH0<0> TH1<0> P1<0> SAD<0> P1CFGA<0> P1CFGB<0> P2<0> P2CFGA<0> P2CFGB<0> EX0 P3<0> BS<0> TS<0> OSD LAN<0> CC/TXT
B5H
R/W
TXT21
CHAR SIZE<1> 0 PES2 FORCE ACQ<0> 0
CHAR SIZE<0> CS<4> PCC FORCE DISP<1> WSS<3:0> ERROR WSS<7:4> ERROR WSS<11>
B7H B8H B9H
R/W R/W R/W
CCLIN IP TXT17
CS<3> PT1 FORCE DISP<0> WSS<3>
CS<2> PX1 SCREEN COL<2> WSS<2>
CS<1> PT0 SCREEN COL<1> WSS<1>
CS<0> PX0 SCREEN COL<0> WSS<0>
BAH
R
WSS1
0
BBH
R
WSS2
0
0
0
WSS<7>
WSS<6>
WSS<5>
WSS<4>
BCH
R
WSS3
WSS<13:11> ERROR X24 POSN
WSS<13>
WSS<12>
WSS<10:8> ERROR P3CFGA<3> P3CFGB<3> DISPLAY STATUS ROW ONLY FULL FIELD REQ<0>
WSS<10>
WSS<9>
WSS<8>
BEH BFH C0H
R/W R/W R/W
P3CFGA P3CFGB TXT0
DISPLAY X24
-
DISABLE HEADER ROLL X26 OFF
P3CFGA<2> P3CFGB<2> -
P3CFGA<1> P3CFGB<1> VPS ON
P3CFGA<0> P3CFGB<0> INV ON
C1H
R/W
TXT1
EXT PKT OFF (Reserved) 0 OSD BANK ENABLE
8 BIT
ACQ OFF
-
-
-
C2H
R/W
TXT2
REQ<3>
REQ<2>
REQ<1>
SC<2>
SC<1>
SC<0>
C3H C4H
W R/W
TXT3 TXT4
QUAD WIDTH ENABLE BKGND IN
EAST/WEST
PRD<4> DISABLE DOUBLE HEIGHT CORB IN
PRD<3> B MESH ENABLE
PRD<2> C MESH ENABLE
PRD<1> TRANS ENABLE
PRD<0> SHADOW ENABLE
C5H
R/W
TXT5
BKGND OUT BKGND OUT
CORB OUT
TEXT OUT
TEXT IN
PICTURE ON OUT PICTURE ON OUT
PICTURE ON IN PICTURE ON IN
C6H
R/W
TXT6
BKGND IN
CORB OUT
CORB IN
TEXT OUT
TEXT IN
Table 3 1999 Sep 28
SFR Map 16
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
ADD
C7H
TDA 935X/6X/8X series
R/W
R/W
Names
TXT7
BIT7
STATUS ROW TOP (Reserved) 0 CURSOR FREEZE 0 D<7> 525/625 SYNC
BIT6
CURSOR ON FLICKER STOP ON CLEAR MEMORY 0 D<6> SPANISH
BIT5
REVEAL
BIT4
BOTTOM/ TOP DISABLE SPANISH R<4>
BIT3
DOUBLE HEIGHT PKT 26 RECEIVED R<3>
BIT2
BOX ON 24
BIT1
BOX ON 123 WSS ON
BIT0
BOX ON 0
C8H
R/W
TXT8
(Reserved) 0 A0
WSS RECEIVED R<2>
(Reserved) 0 R<0>
C9H
R/W
TXT9
R<1>
CAH CBH CCH
R/W R/W R
TXT10 TXT11 TXT12
C<5> D<5> ROM VER<3>
C<4> D<4> ROM VER<2>
C<3> D<3> ROM VER<1>
C<2> D<2> ROM VER<0>
C<1> D<1> 1
C<0> D<0> VIDEO SIGNAL QUALITY PAGE<0>
CDH
R/W
TXT14
0
0
0
(Reserved) 0 (Reserved) 0 RS1 TD<4> TD<12> PW0V<4> PW1V<4> CCD1<4> STO STAT<1> DAT<4> ADR<3> PW3V<4> ACC<4> PW2V<4> CCD2<4> ST B<4> WKEY<4> 525 TEXT
PAGE<3>
PAGE<2>
PAGE<1>
CEH
R/W
TXT15
0
0
0
BLOCK<3>
BLOCK<2>
BLOCK<1>
BLOCK<0>
D0H D2H D3H D5H D6H D7H D8H D9H DAH DBH DCH E0H E4H E7H E8H F0H F7H F8H
R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R R/W R/W W R/W
PSW TDACL TDACH PWM0 PWM1 CCDAT1 S1CON S1STA S1DAT S1ADR PWM3 ACC PWM2 CCDAT2 SAD B WDTKEY TXT13
C TD<7> TPWE PW0E PW1E CCD1<7> CR<2> STAT<4> DAT<7> ADR<6> PW3E ACC<7> PW2E CCD2<7> VHI B<7> WKEY<7> VPS RECEIVED XRAMP<7> STANDBY WDV<7>
AC TD<6> 1 1 1 CCD1<6> ENSI STAT<3> DAT<6> ADR<5> 1 ACC<6> 1 CCD2<6> CH<1> B<6> WKEY<6> PAGE CLEARING XRAMP<6> 0 WDV<6>
F0 TD<5> TD<13> PW0V<5> PW1V<5> CCD1<5> STA STAT<2> DAT<5> ADR<4> PW3V<5> ACC<5> PW2V<5> CCD2<5> CH<0> B<5> WKEY<5> 525 DISPLAY XRAMP<5> 0 WDV<5>
RS0 TD<3> TD<11> PW0V<3> PW1V<3> CCD1<3> SI STAT<0> DAT<3> ADR<2> PW3V<3> ACC<3> PW2V<3> CCD2<3> SAD<7> B<3> WKEY<3> 625 TEXT
OV TD<2> TD<10> PW0V<2> PW1V<2> CCD1<2> AA 0 DAT<2> ADR<1> PW3V<2> ACC<2> PW2V<2> CCD2<2> SAD<6> B<2> WKEY<2> PKT 8/30
TD<1> TD<9> PW0V<1> PW1V<1> CCD1<1> CR<1> 0 DAT<1> ADR<0> PW3V<1> ACC<1> PW2V<1> CCD2<1> SAD<5> B<1> WKEY<1> FASTEXT
P TD<0> TD<8> PW0V<0> PW1V<0> CCD1<0> CR<0> 0 DAT<0> GC PW3V<0> ACC<0> PW2V<0> CCD2<0> SAD<4> B<0> WKEY<0> (Reserved) 0 XRAMP<0> ROMBK<0> WDV<0>
FAH FBH FFH
R/W R/W R/W
XRAMP ROMBK WDT
XRAMP<4> 0 WDV<4>
XRAMP<3> 0 WDV<3>
XRAMP<2> 0 WDV<2>
XRAMP<1> ROMBK<1> WDV<1>
Table 3
SFR Map
1999 Sep 28
17
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
TDA 935X/6X/8X series
The description of each of the SFR bits is shown in Table 4, The table has the SFR's in alphabetical order.
Names
ACC ACC<7:0> B B<7:0> CCDAT1 CCD1<7:0> CCDAT2 CCD2<7:0> CCLIN CS<4:0> DPH DPH<7:0> DPL DPL<7:0> IE EA EBUSY ES2 ECC ET1 EX1 ET0 EX0 IP PBUSY PES2 PCC PT1 PX1 PT0 PX0 P0 P0<6:5> P1 P1<7:6,3:0> P2 P2<0>
BIT7
ACC<7> Accumulator value B<7> B Register value CCD1<7>
BIT6
ACC<6>
BIT5
ACC<5>
BIT4
ACC<4>
BIT3
ACC<3>
BIT2
ACC<2>
BIT1
ACC<1>
BIT0
ACC<0>
RESET
00H
B<6>
B<5>
B<4>
B<3>
B<2>
B<1>
B<0>
00H
CCD1<6>
CCD1<5>
CCD1<4>
CCD1<3>
CCD1<2>
CCD1<1>
CCD1<0>
00H
Closed Caption first data byte CCD2<7> CCD2<6> CCD2<5> CCD2<4> CCD2<3> CCD2<2> CCD2<1> CCD2<0> 00H
Closed Caption second data byte 0 0 0 CS<4> CS<3> CS<2> CS<1> CS<0> 15H
Closed caption Slice line using 525 line number. DPH<7> DPH<6> DPH<5> DPH<4> DPH<3> DPH<2> DPH<1> DPH<0> 00H
Data Pointer High byte, used with DPL to address auxiliary memory DPL<7> DPL<6> DPL<5> DPL<4> DPL<3> DPL<2> DPL<1> DPL<0> 00H
Data pointer low byte, used with DPH to address auxiliary memory EA EBUSY ES2 ECC ET1 EX1 ET0 EX0 00H
Disable all interrupts (0), or use individual interrupt enable bits (1) Enable BUSY interrupt Enable I2C interrupt Enable Closed Caption interrupt Enable Timer 1 interrupt Enable external interrupt 1 Enable Timer 0 interrupt Enable External interrupt 0 0 PBUSY PES2 PCC PT1 PX1 PT0 PX0 00H
Priority EBUSY interrupt Priority ES2 Interrupt Priority ECC interrupt Priority Timer 1 interrupt Priority External Interrupt 1 Priority Timer 0 interrupt Priority External Interrupt 0 P0<6> P0<5> FFH
Port 0 I/O register connected to external pins P1<7> P1<6> P1<3> P1<2> P1<1> P1<0> FFH
Port 1 I/O register connected to external pins P2<0> FFH
Port 2 I/O register connected to external pins
Table 4 1999 Sep 28
SFR Bit description 18
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names
P3 P3<3:0> P0CFGA P0CFGB
TDA 935X/6X/8X series
BIT7
-
BIT6
-
BIT5
-
BIT4
-
BIT3
P3<3>
BIT2
P3<2>
BIT1
P3<1>
BIT0
P3<0>
RESET
FFH
Port 3 I/O register connected to external ADC pins. Any combination of ADC input or PWM (P3<3:0>) output available via Software control. P0CFGA<6> P0CFGB<6> P0CFGA<5> P0CFGB<5> FFH 00H
P0CFGB/P0CFGA = 00 P0CFGB/P0CFGA = 01 P0CFGB/P0CFGA = 10 P0CFGB/P0CFGA = 11 P1CFGA P1CFGB P1CFGA<7> P1CFGB<7>
MODE 0 Open Drain MODE 1 Quasi Bi-Directional MODE2 High Impedance MODE3 Push Pull P1CFGA<6> P1CFGB<6> MODE 0 Open Drain MODE 1 Quasi Bi-Directional MODE2 High Impedance MODE3 Push Pull MODE 0 Open Drain MODE 1 Quasi Bi-Directional MODE2 High Impedance MODE3 Push Pull MODE 0 Open Drain MODE 1 Quasi Bi-directional MODE2 High Impedance MODE3 Push Pull ARD RFI WLE GF1 GF0 PD IDL 00H P3CFGA<3> P3CFGB<3> P3CFGA<2> P3CFGB<2> P3CFGA<1> P3CFGB<1> P3CFGA<0> P3CFGB<0> FFH 00H P2CFGA<0> P2CFGB<0> FFH 00H P1CFGA<3> P1CFGB<3> P1CFGA<2> P1CFGB<2> P1CFGA<1> P1CFGB<1> P1CFGA<0> P1CFGB<0> FFH 00H
P1CFGB/P1CFGA = 00 P1CFGB/P1CFGA = 01 P1CFGB/P1CFGA = 10 P1CFGB/P1CFGA = 11 P2CFGA P2CFGB P2CFGB/P2CFGA = 00 P2CFGB/P2CFGA = 01 P2CFGB/P2CFGA = 10 P2CFGB/P2CFGA = 11 P3CFGA P3CFGB -
P3CFGB/P3CFGA = 00 P3CFGB/P3CFGA = 01 P3CFGB/P3CFGA = 10 P3CFGB/P3CFGA = 11 PCON ARD RFI WLE GF1 GF0 PD IDL PSW C AC F0 -
Auxiliary RAM Disable, All MOVX instructions access the external data memory Disable ALE during internal access to reduce Radio Frequency Interference Watch Dog Timer enable General purpose flag General purpose flag Power-down activation bit Idle mode activation bit C Carry Bit Auxiliary Carry bit Flag 0, General purpose flag AC F0 RS<1> RS<0> OV P 00H
Table 4
SFR Bit description
1999 Sep 28
19
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names
RS<1:0>
TDA 935X/6X/8X series
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
Register Bank selector bits RS<1:0> = 00, Bank0 (00H - 07H) RS<1:0> = 01, Bank1 (08H - 0FH) RS<1:0> = 10, Bank2 (10H - 17H) RS<1:0> = 11, Bank3 (18H - 1FH) Overflow flag Parity bit PW0E 1 PW0V<5> PW0V<4> PW0V<3> PW0V<2> PW0V<1> PW0V<0> 40H
OV P PWM0 PW0E
0 - Disable Pulse Width Modulator 0 1 - Enable Pulse Width Modulator 0 Pulse Width Modulator high time PW1E 1 PW1V<5> PW1V<4> PW1V<3> PW1V<2> PW1V<1> PW1V<0> 40H
PW0V<5:0> PWM1 PW1E
0 - Disable Pulse Width Modulator 1 1 - Enable Pulse Width Modulator 1 Pulse Width Modulator high time PW2E 1 PW2V<5> PW2V<4> PW2V<3> PW2V<2> PW2V<1> PW2V<0> 40H
PW1V<5:0> PWM2 PW2E
0 - Disable Pulse Width Modulator 2 1 - Enable Pulse Width Modulator 2 Pulse Width Modulator high time PW3E 1 PW3V<5> PW3V<4> PW3V<3> PW3V<2> PW3V<1> PW3V<0> 40H
PW2V<5:0> PWM3 PW3E
0 - Disable Pulse Width Modulator 3 1 - Enable Pulse Width Modulator 3 Pulse Width Modulator high time Pulse Width Modulator high time STANDBY 0 0 0 0 0 ROMBK<1> ROMBK<0> 00H
PW3V<5:0> PW7V<5:0> ROMBK STANDBY
0 - Stand-by mode inactive 1 - Stand-by mode active ROM Bank selection ROMBK<1:0>=00, Bank0 ROMBK<1:0>=01, Bank1 ROMBK<1:0>=10, Bank2 ROMBK<1:0>=11, Reserved ADR<6> I2C Slave Address 0 - Disable I2C general call address 1 - Enable I2C general call address CR<2> ENSI STA STO SI AA CR<1> CR<0> 00H ADR<5> ADR<4> ADR<3> ADR<2> ADR<1> ADR<0> GC 00H
ROMBK<1:0>
S1ADR ADR<6:0> GC
S1CON CR<2:0>
Clock rate bits CR<2:0> = 000, 100KHz bit rate CR<2:0> = 001, 3.75kHz bit rate CR<2:0> = 010, 150KHz bit rate CR<2:0> = 011, 200KHz bit rate CR<2:0> = 100, 25KHz bit rate CR<2:0> = 101, 1.875KHz bit rate CR<2:0> = 110, 37.5KHz bit rate CR<2:0> = 111, 50KHz bit rate
Table 4
SFR Bit description
1999 Sep 28
20
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names
ENSI
TDA 935X/6X/8X series
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
0 - Disable I2C interface 1 - Enable I2C interface START flag. When this bit is set in slave mode, the hardware checks the I2C bus and generates a START condition if the bus is free or after the bus becomes free. If the device operates in master mode it will generate a repeated START condition. STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition detected on the I2C bus clears this bit. This bit may also be set in slave mode in order to recover from an error condition. In this case no STOP condition is generated to the I2C bus, but the hardware releases the SDA and SCL lines and switches to the not selected receiver mode. The STOP flag is cleared by the hardware Serial Interrupt flag. This flag is set and an interrupt request is generated, after any of the following events occur: -A START condition is generated in master mode. -The own slave address has been received during AA=1 -The general call address has been received while S1ADR.GC and AA=1 -A data byte has been received or transmitted in master mode (even if arbitration is lost) -A data byte has been received or transmitted as selected slave A STOP or START condition is received as selected slave receiver or transmitter While the SI flag is set, SCL remains LOW and the serial transfer is suspened.SI must be reset by software. Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following conditions -Own slave address is received. -General call address is received(S1ADR.GC=1) -A data byte is received, while the device is programmed to be a master receiver -A data byte is received, while the device is selected slave receiver When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is received. DAT<7> DAT<6> DAT<5> DAT<4> DAT<3> DAT<2> DAT<1> DAT<0> 00H
STA
STO
SI
AA
S1DAT DAT<7:0> S1STA STAT<4:0> SAD VHI
I2C Data STAT<4> I2C Interface Status VHI CH<1> CH<0> ST SAD<7> SAD<6> SAD<5> SAD<4> 00H STAT<3> STAT<2> STAT<1> STAT<0> 0 0 0 F8H
0 - Analogue input voltage less than DAC voltage 1 - Analogue input voltage greater then DAC voltage ADC Input channel select CH<1:0> = 00,ADC3 CH<1:0> = 01,ADC0 CH<1:0> = 10,ADC1 CH<1:0> = 11,ADC2 Initiate voltage comparison between ADC input Channel and SAD<7:0> value Note: Set by Software and reset by Hardware Most Significant nibble of DAC input word 0 0 0 DC COMP SAD<3> SAD<2> SAD<1> SAD<0> 00H
CH<1:0>
ST
SAD<7:4> SADB DC COMP
0 - DC Comparator mode disabled 1 - DC Comparator mode enabled Least Significant nibble of 8 bit SAD value SP<7> SP<6> SP<5> SP<4> SP<3> SP<2> SP<1> SP<0> 07H
SAD<3:0> SP SP<7> TCON TF1 TR1 TF0 TR0 IE1
Stack Pointer TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H
Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine Timer 1 Run control bit. Set/Cleared by software to turn Timer/Counter on/off Timer 0 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine Timer 0 Run control bit. Set/Cleared by software to turn Timer/Counter on/off Interrupt 1 Edge flag (both edges generate flag). Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed.
Table 4 1999 Sep 28
SFR Bit description 21
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names
IT1 IE0 IT0 TDACH TPWE
TDA 935X/6X/8X series
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
Interrupt 1 Type control bit. Set/Cleared by Software to specify edge/low level triggered external interrupts. Interrupt 0 Edge l flag. Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed. Interrupt 0 Type flag.Set/Cleared by Software to specify falling edge/low level triggered external interrupts TPWE 1 TD<13> TD<12> TD<11> TD<10> TD<9> TD<8> 40H
0 - Disable Tuning Pulse Width Modulator 1 - Enable Tuning Pulse Width Modulator Tuning Pulse Width Modulator High Byte TD<7> TD<6> TD<5> TD<4> TD<3> TD<2> TD<1> TD<0> 00H
TD<13:8> TDACL TD<7:0> TH0 TH0<7:0> TH1 TH1<7:0> TL0 TL0<7:0> TL1 TL1<7:0> TMOD
Tuning Pulse Width Modulator Low Byte TH0<7> Timer 0 high byte TH1<7> Timer 1 high byte TL0<7> Timer 0 low byte TL1<7> Timer 1 low byte GATE C/T M1 M0 GATE C/T M1 M0 00H TL1<6> TL1<5> TL1<4> TL1<3> TL1<2> TL1<1> TL1<0> 00H TL0<6> TL0<5> TL0<4> TL0<3> TL0<2> TL0<1> TL0<0> 00H TH1<6> TH1<5> TH1<4> TH1<3> TH1<2> TH1<1> TH1<0> 00H TH0<6> TH0<5> TH0<4> TH0<3> TH0<2> TH0<1> TH0<0> 00H
Timer 1
GATE C/T M1,M0 Gating Control Timer /Counter 1 Counter (1) or Timer (0) selector
Timer 0
Mode control bits M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 prescaler M1,M0 = 01, 16 bit time interval or event counter M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH1 M1,M0 = 11, stopped Gating control Timer/Counter 0 Counter (1) or Timer (0) selector Mode Control bits M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 prescaler M1,M0 = 01, 16 bit time interval or event counter M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH0 M1,M0 = 11, one 8bit time interval or event counter and one 8bit time interval counter X24 POSN DISPLAY X24 DISABLE HEADER ROLL DISPLAY STATUS ROW ONLY VPS ON INV ON 00H
GATE C/T M1,M0
TXT0
X24 POSN
0 - Store X/24 in extension memory 1 - Store X/24 in basic page memory with packets 0 to 23 0 - Display row 24 from basic page memory 1 - Display row 24 from appropriate location in extension memory 0 - Write rolling headers and time to current display page 1 - Disable writing of rolling headers and time to into memory
DISLAY X24
DISABLE HEADER ROLL
Table 4
SFR Bit description
1999 Sep 28
22
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names
DISPLAY STATUS ROW ONLY VPS ON
TDA 935X/6X/8X series
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
0 - Display normal page rows 0 to 24 1- Display only row 24 0 - VPS acquisition off 1 - VPS acquisition on 0 - Inventory page off 1 - Inventory page on EXT PKT OFF 8 BIT ACQ OFF X26 OFF FULL FIELD 0 0 0 00H
INV ON
TXT1
EXT PKT OFF
0 - Acquire extension packets X/24,X/27,8/30/X 1 - Disable acquisition of extension packets 0 - Error check and/or correct packets 0 to 24 1 - Disable checking of packets 0 to 24 written into memory 0 - Write requested data into display memory 1 - Disable writing of data into Display memory 0 - Enable automatic processing of X/26 data 1 - Disable automatic processing of X/26 data 0 - Acquire data only on VBI lines 1 - Acquire data on any TV line (Reserved) 0 REQ<3> REQ<2> REQ<1> REQ<0> SC<2> SC<1> SC<0> 00H
8 BIT
ACQ OFF
X26 OFF
FULL FIELD
TXT2
REQ<3:0> SC<2:0> TXT3 PRD<4:0> TXT4
Page request Start column of page request PRD<4> Page Request data OSD BANK ENABLE QUAD WIDTH ENABLE EAST/WEST DISABLE DBL HEIGHT B MESH ENABLE C MESH ENABLE TRANS ENABLE SHADOW ENABLE 00H PRD<3> PRD<2> PRD<1> PRD<0> 00H
OSD BANK ENABLE QUAD WIDTH ENABLE EAST/WEST
0 - Only alpha numeric OSD characters available, 32 locations 1 - Alternate OSD location available via graphic attribute, additional 32 location 0 - Disable display of Quadruple width characters 1 - Enable display of Quadruple width characters 0 - Western language selection of character codes A0 to FF 1 - Eastern character selection of character codes A0 to FF 0 - Allow normal decoding of double height characters 1 - Disable normal decoding of double height characters 0 - Normal display of black background 1 - Enable meshing of black background 0 - normal display of coloured background 1 - Enable meshing of coloured background 0 - Display black background as normal 1 - Display black background as video 0 - Disable display of shadow/fringing 1 - Display shadow/ fringe (default SE black) BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ON OUT PICTURE ON IN 03H
DISABLE DOUBLE HEIGHT B MESH ENABLE C MESH ENABLE TRANS ENABLE SHADOW ENABLE TXT5
BKGND OUT
0 - Background colour not displayed outside teletext boxes 1 - Background colour displayed outside teletext boxes
Table 4 1999 Sep 28
SFR Bit description 23
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names
BKGND IN
TDA 935X/6X/8X series
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
0 - Background colour not displayed inside teletext boxes 1 - Background colour displayed inside teletext boxes 0 - COR not active outside teletext and OSD boxes 1 - COR active outside teletext and OSD boxes 0 - COR not active inside teletext and OSD boxes 1 - COR active inside teletext and OSD boxes 0 - TEXT not displayed outside teletext boxes 1 - TEXT displayed outside teletext boxes 0 - TEXT not displayed inside teletext boxes 1 - TEXT displayed inside teletext boxes 0 - VIDEO not displayed outside teletext boxes 1 - VIDEO displayed outside teletext boxes 0 - VIDEO not displayed inside teletext boxes 1 - VIDEO displayed inside teletext boxes BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ON OUT PICTURE ON IN 03H
COR OUT
COR IN
TEXT OUT
TEXT IN
PICTURE ON OUT PICTURE ON IN
TXT6
BKGND OUT
0 - Background colour not displayed outside teletext boxes 1 - Background colour displayed outside teletext boxes 0 - Background colour not displayed inside teletext boxes 1 - Background colour displayed inside teletext boxes 0 - COR not active outside teletext and OSD boxes 1 - COR active outside teletext and OSD boxes 0 - COR not active inside teletext and OSD boxes 1 - COR active inside teletext and OSD boxes 0 - TEXT not displayed outside teletext boxes 1 - TEXT displayed outside teletext boxes 0 - TEXT not displayed inside teletext boxes 1 - TEXT displayed inside teletext boxes 0 - VIDEO not displayed outside teletext boxes 1 - VIDEO displayed outside teletext boxes 0 - VIDEO not displayed inside teletext boxes 1 - VIDEO displayed inside teletext boxes STATUS ROW TOP CURSOR ON REVEAL BOTTOM/ TOP DOUBLE HEIGHT BOX ON 24 BOX ON 123 BOX ON 0 00H
BKGND IN
COR OUT
COR IN
TEXT OUT
TEXT IN
PICTURE ON OUT PICTURE ON IN
TXT7
STATUS ROW TOP CURSOR ON
0 - Display memory row 24 information below teletext page (on display row 24) 1 - Display memory row 24 information above teletext page (on display row 0) 0 - Disable display of cursor 1 - Display cursor at position given by TXT9 and TXT10 0 - Display as spaces characters in area with conceal attribute set 1 - Display characters in area with conceal attribute set 0 - Display memory rows 0 to 11 when double height bit is set 1 - Display memory rows 12 to 23 when double height bit is set 0 - Display each characters with normal height 1 - Display each character as twice normal height. 0 - Disable display of teletext boxes in memory row 24 1 - Enable display of teletext boxes in memory row 24 0 - Disable display of teletext boxes in memory row 1 to 23 1 - Enable display of teletext boxes in memory row 1 to 23
REVEAL
BOTTOM/TOP
DOUBLE HEIGHT BOX ON 24
BOX ON 1-23
Table 4
SFR Bit description
1999 Sep 28
24
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names
BOX ON 0
TDA 935X/6X/8X series
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
0 - Disable display of teletext boxes in memory row 0 1 - Enable display of teletext boxes in memory row 0 (Reserved) 0 FLICKER STOP ON (Reserved) 0 DISABLE SPANISH PKT 26 RECEIVED WSS RECEIVED WSS ON 0 00H
TXT8
FLICKER STOP ON DISABLE SPANISH PKT 26 RECEIVED
0 - Enable `Flicker Stopper' circuitry 1 - Disable `Flicker Stopper' circuitry 0 - Enable special treatment of Spanish packet 26 characters 1 - Disable special treatment of Spanish packet 26 characters 0 - No packet 26 data has been processed 1 - Packet 26 data has been processed. Note: This flag is set by Hardware and must be reset by Software 0 - No Wide Screen Signalling data has been processed 1 - Wide Screen signalling data has been processed Note: This flag is set by Hardware and must be reset by Software. 0 - Disable acquisition of WSS data. 1 - Enable acquisition of WSS data. CURSOR FREEZE CLEAR MEMORY A0 R<4> R<3> R<2> R<1> R<0> 00H
WSS RECEIVED
WSS ON
TXT9
CURSOR FREEZE CLEAR MEMORY
0 - Use current TXT9 and TXT10 values for cursor position. 1 - Lock cursor at current position 0 - Clear memory block not requested 1 - Clear memory block pointed to by TXT15 Note: This flag is set by Software and reset by Hardware 0 - Access memory block pointed to by TXT15 1 - Access extension packet memory Current memory ROW value. Note: Valid range TXT mode 0 to 24. 0 0 C<5> C<4> C<3> C<2> C<1> C<0> 00H
A0
R<4:0>
TXT10 C<5:0>
Current memory COLUMN value. Note: Valid range TXT mode 0 to 39. D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> 00H
TXT11 D<7:0> TXT12
Data value written or read from memory location defined by TXT9, TXT10 and TXT15 625/525 SYNC Spanish ROM VER<3> ROM VER<2> ROM VER<1> ROM VER<0> 1 VIDEO SIGNAL QUALITY xxxxxx1xB
625/525 SYNC
0 - 625 line CVBS signal is being received 1 - 525 line CVBS signal is being received 0 - Spanish character set not present in device 1 - Spanish character set present in device Mask programmable identification for character set 0 - Acquisition can not be synchronised to CVBS input 1 - Acquisition can be synchronised to CVBS input VPS RECEIVED PAGE CLEARING 525 DISPLAY 525 TEXT 625 TEXT PKT 8/30 FASTEXT 0 xxxxxxx0B
Spanish
ROM VER<3:0> VIDEO SIGNAL QUALITY TXT13
VPS RECEIVED
0 - VPS data not being received 1 - VPS data being received 0 - No page clearing active 1 - Software or Power On page clear in progress
PAGE CLEARING
Table 4
SFR Bit description
1999 Sep 28
25
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names
525 DISPLAY
TDA 935X/6X/8X series
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
0 - 625 Line synchronisation for Display 1 - 525 Line synchronisation for Display 0 - 525 Line WST not being received 1 - 525 line WST being received 0 - 625 Line WST not being received 1 - 625 line WST being received 0 - No Packet 8/30/x(625) or Packet 4/30/x(525) data detected 1 - Packet 8/30/x(625) or Packet 4/30/x(525) data detected 0 - No Packet x/27 data detected 1 - Packet x/27 data detected 0 0 0 (Reserved) 0 PAGE<3> PAGE<2> PAGE<1> PAGE<0> 00H
525 TEXT
625 TEXT
PKT 8/30
FASTEXT
TXT14
PAGE<3:0> TXT15
Current Display page 0 0 0 (Reserved) 0 BLOCK<3> BLOCK<2> BLOCK<1> BLOCK<0> 00H
BLOCK<3:0> TXT17
Current Micro block to be accessed by TXT9, TXT10 and TXT11 0 FORCE ACQ<1> FORCE ACQ<0> FORCE DISP<1> FORCE DISP<0> SCREEN COL2 SCREEN COL1 SCREEN COL0 00H
FORCE ACQ<1:0>
00 - Automatic Selection 01 - Force 525 timing, Force 525 Teletext Standard 10 - Force 625 timing, Force 625 Teletext Standard 11 - Force 625 timing, Force 525 Teletext Standard 00 - Automatic Selection 01 - Force Display to 525 mode (9 lines per row) 10 - Force Display to 625 mode (10 lines per row) 11 - Not Valid (default to 625) Defines colour to be displayed instead of TV picture and black background. The bits <2:0> are equivalent to the RGB components 000 - Transparent 001 - CLUT entry 9 010 - CLUT entry 10 011- CLUT entry 11 100 - CLUT entry 12 101 - CLUT entry 13 110- CLUT entry 14 111 - CLUT entry 15 NOT<3> NOT<2> NOT<1> NOT<0> 0 0 BS<1> BS<0> 00H
FORCE DISP<1:0>
SCREEN COL<2:0>
TXT18 NOT<3:0> BS<1:0> TXT19 TEN
National Option table selection, maximum of 32 when used with East/West bit Basic Character set selection TEN TC<2> TC<1> TC<0> 0 0 TS<1> TS<0> 00H
0 - Disable Twist function 1- Enable Twist character set Language control bits (C12/C13/C14) that has Twisted character set Twist Character set selection DRCS ENABLE OSD PLANES 0 0 OSD LANG ENABLE OSD LAN<2> OSD LAN<1> OSD LAN<0> 00H
TC<2:0> TS<1:0> TXT20
DRCS ENABLE
0 - Normal OSD characters used 1 - Re-map column 8 and 9 to DRCS. 0 - Character code columns 8 and 9 defined as single plane characters (two colours per character). 1- Character code columns 8 and 9 defined as two plane characters (four colours per character).
OSD PLANES
Table 4 1999 Sep 28
SFR Bit description 26
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
Names
OSD LANG ENABLE OSD LAN<2:0> TXT21
TDA 935X/6X/8X series
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
Enable use of OSD LAN<2:0> to define language option for display, instead of C12/C13/C14
Alternative C12/C13/C14 bits for use with OSD menus DISP LINES<1> DISP LINES<0> CHAR SIZE<1> CHAR SIZE<0> 0 CC ON I2C PORT0 CC/TXT 02H
DISP LINES<1:0>
The number of display lines per character row. 00 - 10 lines per character (defaults to 9 lines in 525 mode) 01 - 13 lines per character 10 - 16 lines per character 11 - reserved Character matrix size. 00 - 10 lines per character (matrix 12x10) 01 - 13 lines per character (matrix 12x13) 10 - 16lines per character (matrix 12x16) 11 - reserved 0 - Closed Caption acquisition off 1 - Closed Caption acquisition on 0 - disable I2C PORT0 1 - enable I2C PORT0 selection (P1.7/SDA0, P1.6/SCL0) 0 - Display configured for TXT mode 1 - Display configured for CC mode WDV<7> WDV<6> WDV<5> WDV<4> WDV<3> WDV<2> WDV<1> WDV<0> 00H
CHAR SIZE<1:0>
CCON
I2C PORT0
CC/TXT
WDT WDv<7:0> WDTKEY WKEY<7:0>
Watch Dog Timer period WKEY<7> WKEY<6> WKEY<5> WKEY<4> WKEY<3> WKEY<2> WKEY<1> WKEY<0> 00H
Watch Dog Timer Key Note: Must be set to 55H to disable Watch dog timer when active 0 0 0 WSS<3:0> ERROR WSS<3> WSS<2> WSS<1> WSS<0> 00H
WSS1
WSS<3:0> ERROR WSS<3:0> WSS2
0 - No error in WSS<3:0> 1 - Error in WSS<3:0> Signalling bits to define aspect ratio (group 1) 0 0 0 WSS<7:4> ERROR WSS<7> WSS<6> WSS<5> WSS<4> 00H
WSS<7:4> ERROR WSS<7:4> WSS3
0 - No errors in WSS<7:4> 1 - Error in WSS<7:4> Signalling bits to define enhanced services (group 2) WSS<13:11< ERROR WSS<13> WSS<12> WSS<11> WSS<10:8> ERROR WSS<10> WSS<9> WSS<8> 00H
WSS<13:11> ERROR WSS<13:11> WSS<10:8> ERROR WSS<10:8> XRAMP XRAMP<7:0>
0 - No error in WSS<13:11> 1 - Error in WSS<13:11> Signalling bits to define reserved elements (group 4) 0 - No error in WSS<10:8> 1 - Error in WS<10:8> Signalling bits to define subtitles (group 3) XRAMP<7> XRAMP<6> XRAMP<5> XRAMP<4> XRAMP<3> XRAMP<2> XRAMP<1> XRAMP<0> 00H
Internal RAM access upper byte address
Table 4
SFR Bit description
1999 Sep 28
27
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
Character Set Feature Bits
TDA 935X/6X/8X series
Features available on the TDA935X/6X/8X devices are reflected in a specific area of the character ROM. These sections of the character ROM are mapped to two Special Function Registers: TXT22 and TXT12. Character ROM address 09FEH is mapped to SFR TXT22 as shown in Table 5. Character ROM address 09FFH is mapped to SFR TXT12 as shown in Table 7.
MAPPED ITEMS 11 Character ROM; X address 09FEH Mapped to TXT22 - U = Used, X = Reserved 10 X - 9 X - 8 X - 7 X 7 6 X 6 5 X 5 4 U 4 3 U 3 2 U 2 1 U 1 0 X 0
Table 5
Character Rom - TXT22 mapping
BIT 0 1 2 3 4 5 to 11
FUNCTION Reserved 1 = Text Acquisition available 0 = Text Acquisition not available 1 = Closed Caption Acquisition available 0 = Closed Caption Acquisition not available 1 = PWM0, PWM1, PWM2 and PWM3 not present 0 = PWM0, PWM1, PWM2 and PWM3 output on Port 3.0 to Port 3.3 respectively 1 = 10 page available 0 = 6 page available Reserved
Table 6
Description of Character ROM address 09FEH bits
MAPPED ITEMS 11 Character ROM; X address 09FFH Mapped to TXT2 - 4 = Used, 5 = Reserved
10 X -
9 X -
8 X -
7 X -
6 X -
5 X -
4 U 6
3 X 5
2 X 4
1 X 3
0 X 2
Table 7
Character Rom - TXT12 mapping
BIT 4 0 to 3, 5 to 11
FUNCTION 1 = Spanish character set present 0 = no Spanish character set present Reserved
Table 8
Description of Character ROM address 0X 09FFH bits
1999 Sep 28
28
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
External (Auxiliary) Memory
TDA 935X/6X/8X series
The normal 80C51 external memory area has been mapped internally to the device, this means that the MOVX instruction accesses memory internal to the device.
7FFFH
FFFFH
47FFH
8BFFH Dynamically Redefinable Characters
Display RAM for TEXT PAGES(2)
8800H 87FFH Display Registers 87F0H 871FH CLUT
2000H
8700H 845FH Display RAM for Closed Caption(3) 8000H Upper 32K bytes
07FFH Data RAM(1) 0000H Lower 32K bytes
(1) Amount of Data RAM depends on device (2) Amount of Display RAM depends on the device (3) Display RAM for Closed Caption and Text is shared
Figure 11
Auxiliary RAM allocation
1999 Sep 28
29
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
Auxiliary RAM Page Selection
TDA 935X/6X/8X series
The Auxiliary RAM page selector is used to select one of the 256 pages within the auxiliary RAM, not all pages are allocated, refer to Figure 11 for further detail. A page consists of 256 consecutive bytes.
FFH (XRAMP)=FFH 00H FFH (XRAMP)=FEH MOVX @Ri, A MOVX A, @Ri 00H
FFFFH
FF00H FEFFH
FE00H
MOVX @DPTR,A MOVX A,@DPTR
FFH (XRAMP)=01H 00H FFH (XRAMP)=00H 00H
01FFH
0100H 00FFH
0000H
Figure 12
Indirect addressing of AUX-RAM
1999 Sep 28
30
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
Power-on Reset
TDA 935X/6X/8X series
An automatic reset can be obtained when VDD is applied by connecting the RESET pin to VDDP through a 10uF capacitor, providing the VDD rise time does not exceed 1ms, and the oscillator start-up time does not exceed 10ms. To ensure correct initialisation, the RESET pin must be held high long enough for the oscillator to settle following power-up, usually a few milli-seconds. Once the oscillator is stable, a further 12 clocks are required to generate the Reset (One machine cycle of the Micro-controller). Once the above reset condition has been detected an internal reset signal is triggered which remains active for 2048 clock cycles. Reduced Power modes There are three power saving modes: Stand-by, Idle and Power Down. In all three modes the 3.3v power supplies (Vddp, Vddc & Vdda) to the device must be maintained. Power saving is achieved by clock gating on a section by section basis. STAND-BY MODE When Stand-by mode is entered both Acquisition and Display sections are disabled. The following functions remain active:· · · · · · · 80c51 Core Memory Interface I2C Timer/Counters WatchDog Timer Software A/D Pulse Width Modulators
To enter Stand-by mode, the STANDBY control bit in the ROMBANK SFR (Bit-7) must be set. It can be used in conjunction with either Idle or Power-Down to switch between power saving modes. This mode enables the 80c51 core to decode either IR Remote Commands or receive IIC commands without the need to fully power the device. The Stand-by state is maintained upon exit from Idle / Power-Down. No wake-up from Stand-by is necessary as the 80c51 core remains operational. Since the output values on RGB and VDS are maintained the teletext/OSD display must be disabled before entering this mode. IDLE MODE During Idle mode, Acquisition, Display and the CPU sections of the device are disabled. The following functions remain active:· · · Memory Interface I2C Timer/Counters
1999 Sep 28
31
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
· · WatchDog Timer Pulse Width Modulators
TDA 935X/6X/8X series
To enter Idle mode the IDL bit in the PCON register must be set. The WatchDog timer must be disabled prior to entering Idle to prevent the device being reset. Once in Idle mode, the XTAL oscillator continues to run, but the internal clock to the CPU, Acquisition and Display are gated out. However, the clocks to the Memory Interface, I2C, Timer/Counters, WatchDog Timer and Pulse Width Modulators are maintained. The CPU state is frozen along with the status of all SFRs, internal RAM contents are maintained, as are the device output pin values. Since the output values on RGB and VDS are maintained the teletext/OSD display must be disabled before entering this mode. There are three methods available to recover from Idle:· Assertion of an enabled interrupt will cause the IDL bit to be cleared by hardware, thus terminating Idle mode. The interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one after the instruction that put the device into Idle mode. A second method of exiting Idle is via an Interrupt generated by the SAD DC Compare circuit. When Painter is configured in this mode, detection of an analogue threshold at the input to the SAD may be used to trigger wake-up of the device i.e. TV Front Panel Key-press. As above, the interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one following the instruction that put the device into Idle. For further details of the SAD DC Compare mode refer to the Software A/D description within the micro-controller section. The third method of terminating Idle mode is with an external hardware reset. Since the oscillator is running, the hardware reset need only be active for one machine cycle (12 clocks at 12MHz) to complete the reset operation. Reset defines all SFRs and Display memory to a pre-defined state, but maintains all other RAM values. Code execution commences with the Program Counter set to '0000'.
·
·
POWER DOWN MODE In Power Down mode the XTAL oscillator is stopped. The contents of all SFR, and RAM is maintained, however the Auxiliary/Display memory is not maintained. The port pins maintain the values defined by the SFR's. Since the output values on RGB and VDS are maintained the teletext/OSD display must be made inoperative before entering Power Down mode. The power down mode is activated by setting the PD bit in the PCON register. The WatchDog timer must be disabled before entering Power down. There are two methods of exiting power down. Since the clock is stopped, external interrupts needs to be set to level sensitive, by changing the level of these interrupts the device can be taken out of power down. The second method of terminating the power down mode is with an external hardware reset. Reset defines all SFR's and Display memory, but maintains all other RAM values. I/O Facility I/O PORTS The device has a number of micro-controller port I/O lines, each are individually addressable. The I2C-bus ports (P1.6 and P1.7) can only be configured as Open-drain. 1999 Sep 28 32
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
PORT TYPE
TDA 935X/6X/8X series
All individual ports bits can be programmed to function in one of four modes, the mode is defined by eight Port Configuration SFR's (P0CFGA/P0CFGB, P1CFGA/P1CFGB, P2CFGA/P2CFGB and P3CFGA/P3CFGB). The modes available are Open Drain, Quasi-bidirectional, High Impedance, Push-Pull.
Open Drain
The Open drain mode can be used for bi-directional operation of a port. It requires an external pull-up resistor, the pull-up voltage has a maximum value of 5.5V, to allow connection of the device into a 5V environment.
Quasi-bidirectional
The quasi-bidirectional mode is a combination of open drain and push pull. It requires an external pull-up resistor to VDDp (nominally 3.3V). When a signal transition from 0 to 1 is output from the device, the pad is put into pushpull mode for one clock cycle (166ns) after which the pad goes into open drain mode. The mode may be used to speed up the edges of signal transitions. This is the default mode of operation of the pads after reset.
High Impedance
The high impedance mode can be used for Input only operation of the port. When using this configuration the two output transistors are turned off.
Push-Pull
The push pull mode can be used for output only. In this mode the signal is driven to either 0V or VDDp, which is nominally 3.3V. Interrupt System The device has 7 interrupt sources, each of which can be enabled or disabled. When enabled each interrupt can be assigned one of two priority levels. There are four interrupts that are common to the 80C51, two of these are external interrupts (EX0 and EX1) and the other two are timer interrupts (ET0 and ET1). In addition to the conventional 80c51, two application specific interrupts are incorporated internal to the device which have following functionality:ECC (Closed Caption Data Ready Interrupt) - This interrupt is generated when the device is configured in Closed Caption Acquisition mode. The interrupt is activated at the end of the currently selected Slice Line as defined in the CCLIN SFR. EBUSY (Display Busy Interrupt) - An interrupt is generated when the Display enters either a Horizontal or Vertical Blanking Period. i.e. Indicates when the micro-controller can update the Display RAM without causing undesired effects on the screen. This interrupt can be configured in one of two modes using the MMR Configuration Register (Address 87FF, Bit-3 [TXT/V]):· · TeXT Display Busy: An interrupt is generated on each active horizontal display line when the Horizontal Blanking Period is entered. Vertical Display Busy: An interrupt is generated on each vertical display field when the Vertical Blanking Period is entered.
1999 Sep 28
33
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
Interrupt Enable Structure
TDA 935X/6X/8X series
Each of the individual interrupt can be enable or disable by setting or clearing the relevant bit in the interrupt enable SFR called IE. All interrupt sources can also be globally disabled by clearing the EA bit (IE.7) The interrupt structure is shown in Figure 13. . H1 EX0 L1 H2 ET0 EX1 ET1 ECC ES2 EBUSY Interrupt Source Source Enable IE.0:6 Figure 13 Interrupt Enable Priority Each interrupt source can be assigned one of two priority levels. The interrupt priority are defined by the interrupt priority SFR called IP. A low priority interrupt can be interrupted by a high priority interrupt, but not by another low priority interrupt. A high priority interrupt can not be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request with the highest priority level is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level there is a second priority structure determined by the polling sequence as defined in Table 9 Global Enable IE.7 Priority Control IP.0:6 L2 H3 L3 H4 L4 H5 L5 H6 L6 H7 L7
Lowest Priority Level1 Lowest Priority Level0 Highest Priority Level0 Highest Priority Level1
Interrupt Structure
1999 Sep 28
34
Philips Semiconductors
Preliminary specification
TV signal processor-Teletext decoder with embedded µ-Controller
. Priority within level Highest Lowest
TDA 935X/6X/8X series
Source EX0 ET0 EX1 ET1 ECC ES2 EBUSY Table 9 INTERRUPT VECTOR ADDRESS
Interrupt Vector 0003H 000BH 0013H 001BH 0023H 002BH 0033H
Interrupt Priority (within same level)
The processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine. The interrupt vector addresses for each source are shown in Table 9. LEVEL/EDGE INTERRUPT The external interrupt can be programmed to be either level-activated or transition activated by setting or clearing the IT0/1 bits in the Timer Control SFR called TCON. ITx 0 1 Table 10 Level Active low INT0 = Negative Edge INT1 = Positive and Negative Edge External Interrupt Activation Edge
The external interrupt INT1 differs from the standard 80C51 in that it is activated on both edges when in edge sensitive mode. This is to allow software pulse width measurement for handling remote control inputs. Timer/Counter Two 16 bit timers/counters are incorporated Timer0 and Timer1. Both can be configured to operate as either timers or event counters. In Timer mode, the register is incremented on every machine cycle. It is therefore counting machine cycles. Since the machine cycle consists of 12 oscillator periods, the count rate is 1/12 Fosc = 1MHz. In Counter mode, the register is incremented in response to a negative transition at its corresponding external pin T0 or T1. Since the pins T0 and T1 are sampled once per machine cycle it takes two machine cycles to recognise a transition, this gives a maximum count rate of 1/24 Fosc = 0.5MHz. There are six spec