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APPLICATION NOTE KITS/BOARDS
MICRONAS
SDA 55xx TVText Pro Evaluation Board
Edition Nov. 26, 2003 6251-556-3-2AK
MICRONAS
SDA 55xx
Contents Page 1 1 2 2 2 3 6 Section 1. 1.1. 2. 2.1. 2.2. 3. 4. Title Introduction Features of the TVText Pro Evaluation Board Getting Started Jumper Settings How to Start the Demonstration Application Circuit Application Note History
APPLICATION NOTE KITS/BOARDS
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Nov. 26, 2003; 6251-556-3-2AK
Micronas
APPLICATION NOTE KITS/BOARDS
SDA 55xx
Clock: 6 MHz crystal Interfaces: Serial interface for RS232 (RS232 connector, DB9 plug) TV interface for display (SCART connector, SCART plug) Signal interface for Full Data Service Slicer (CVBS Input, BNC plug) Multifunctional interface for extension (Universal Con., 96-pin plug) Power: Only one external stable +5 V power supply unit required On-board generated +3.3 V (adjustable), +2.5 V (adj.) and +8.0 V Modules: Infrared receiver for IR remote control Sync-Separator for generating H- and V-sync from an CVBS signal Dimensions: 100 mm x 154 mm, height: 3.1 mm
TVText Pro Release Note: Revision bars indicate significant changes to the previous edition.
1. Introduction The TVText Pro Evaluation Board is a versatile tool which provides quick access to the capabilities of TVText Pro's powerful architecture. To enable applications to be developed quickly and easily, the TVText Pro Evaluation Board is fitted with a variety of peripherals for connections to the outside world. This document applies to version 2 or higher of the TVText Pro Evaluation Board. Version 2 can clearly be seen on the board by the marking B004-V002.
1.1. Features of the TVText Pro Evaluation Board CPU: TVText Pro in open top socket (MQFP100 package) Memory: FLASH/EPROM memory up to 512 k x 8 (3.3 V, PLCC32 package) SRAM 512 k x 8 (3.3 V, SO32 package) NV-Memory (3.3 V, DIP8 package, I2C controlled)
Universal Connector Reset Button
NVM RS232 Connector Infrared Decoder
SCART Connector (RGB Out)
4 Mbit SRAM Power LED Flash/Eprom +5 V Power Supply Input
CVBS IN
SyncSeparator
6 MHz Crystal
+2.5 V Adjustment +3.3 V Adjustment
Fig. 11: TVText Pro Evaluation Board
Micronas
Nov. 26, 2003; 6251-556-3-2AK
1
SDA 55xx
2. Getting Started 2.1. Jumper Settings An overview of all jumpers and switches of the TVText Pro Evaluation Board is shown in Table 21. The setting recommended in the last column "Setting" is used for running the demonstration software (P090Vxxx : 10 pages or P098Vxxx: 252 pages) with a television connected via the SCART connector.
APPLICATION NOTE KITS/BOARDS
2.2. How to Start the Demonstration After setting the jumpers to the right position, proceed through the following instructions to start the demonstration software: connect an antenna to a TV set and tune the TV (video picture on screen) connect the TV set via a SCART cable to the TVText Pro Evaluation Board connect a stable +5 V power supply unit (300 mA) to the power supply input ('POWER 5 V') of the TVText Pro Evaluation Board press the reset button on the TVText Pro Evaluation Board if the TVText Pro does not synchronize its OSD to the video, switch the TV set to AV mode.
Table 21: Overview: jumpers and switches Jumper SW100 SW101 (SYNC) SW102 (SLICER) J200 (RxD) J201 (TxD) J300 (SDA) J301 (SCL) Description Selection of sync source for the HS/SC input pin: Sandcastle (`SSC') or H-sync (`HSYNC') Selection of CVBS source for the sync separator: `BNC' connector or `SCART' connector Selection of CVBS source for TVText Pro's slicer: `BNC' connector or `SCART' connector Connect RS232-Interface Driver (RxD0) to TVText Pro Connect RS232-Interface Driver (TxD0) to TVText Pro Connect P3.4/SDA to NV-Memory Connect P3.2/SCL to NV-Memory Setting Position SSC Position SCART Position SCART don't care don't care don't care don't care
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Nov. 26, 2003; 6251-556-3-2AK
Micronas
BLANK CO/BLOUT
P4.0 C103 100n GND
21
91
74
39
WR# +3,3V +2,5V C108 33p
7
CVBS
VSSD
VSSC
VSSB
RESET P1.7
BNC 53 XTAL1
OSC.IN
SW101 SYNC
BNC
1 SW102 SLICER C104
OSC.OUT
+
CON102 BNC 2 10µ VDD33C 75 PGM OTPVDD33D 92 +3,3VMEM VDDDAC 56 VSSDAC 55 VDDADC 22 C110 100n GND +2,5VADC +2,5VDAC 2 Q100 6MHz
1 VDD33B 40 +3,3V
3. Application Circuit
C105
C106
GOUT BOUT BNCIN SW103 100n RESET VDD25B RST Group-Delay-Filter RESET 50 73 VDD25A 6 R122 8k2 C107 33p 100n
R126 22k
1
3
APPLICATION NOTE KITS/BOARDS
R124 0R
P4.3 P1.6 P4.2 R127 100 8,2µH R129 390 CVBSFIL Filter on (default) remove R132 Filter off Remove R124 and R131, set R132 TVTPRO-1 R131 OR R132 0R IC100
R125 47k
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 16 15 14 13 12 11 10 9 C109 100n GND VSSADC 23 R123 0R XROM 5 P0-7 P0-6 P0-5 P0-4 P0-3 P0-2 P0-1 P0-0
WR# RD# PSEN#
P1.4
+
CON100 UNIVERSAL
P3.5 P3.2 P3.6 +3,3V R113 68 R114 68 R115 68 27 26 25 24 P2-3 -ADCIN P2-2 -ADCIN P2-1 -ADCIN P2-0 -ADCIN
P1.2 P3.0 R111 47 R110 47
ROUT GOUT BOUT CO/BLOUT
1
3
3
FL_CE
FL_RST
FL_PGM
BLANK R108 39
1
20
EXTIF
FL_CE 95
FL_RST 80
P0.5 P0.7 P0.0 P0.3 P0.4 PSEN# P0.2 P0.1 +3,3V
VSYNC HS R104 10k
SSC
+
SCIN
SYNCOUT
BLANK RED
GREEN
BLUE
BC817
A1 B1 C1 A2 B2 C2 A3 B3 C3 A4 B4 C4 A5 B5 C5 A6 B6 C6 A7 B7 C7 A8 B8 C8 A9 B9 C9 A10 B10 C10 A11 B11 C11 A12 B12 C12 A13 B13 C13 A14 B14 C14 A15 B15 C15 A16 B16 C16 A17 B17 C17 A18 B18 C18 A19 B19 C19 A20 B20 C20 A21 B21 C21 A22 B22 C22 A23 B23 C23 A24 B24 C24 A25 B25 C25 A26 B26 C26 A27 B27 C27 A28 B28 C28 A29 B29 C29 A30 B30 C30 A31 B31 C31 A32 B32 C32 CVBS C111 C112 C113 C114 VDD33A 8 100n 100n 100n 100n R128 470 L101 150p C116 R130 10k
+3,3VUNI
C100 33n CON101
C101 100n
R100 75
3
C102 47µ
R101
1k T101 2
1
3
L100 10µH
R106 2k7 R105 10k T100 R102 1k 2 R103 5k6 R107 2k2
HSYNC SW100 3 1 2 SSC
SDA 55xx
+5VIN
BC817 1
SCART
FL_PGM72
Nov. 26, 2003; 6251-556-3-2AK
+2,5VADC
RD# P1.3 R118 100 T104 BC807 R117 T105 BC807 2 R116 100 +3,3V T102 BC817 2 +3,3V 100
P2.3 P2.2 P2.1 P2.0
P3.4 IR/P3.3 P3.1 R112 47 J100 CONP2 P3.7 P3.6 P3.5 P3.4 IR/P3.3 P3.2 P3.1 P3.0 38 37 36 35 34 33 32 31 57 GOUT BOUT 58 59 CO/BLOUT60 ROUT
HSYNC VSYNC T103 BC807
P3-7-INTX0 P3-6 P3-5 -T1 P3-4-T0 P3-3-INT1 P3-2-INT0 P3-1-INTX0 P3-0 -ODD/EVEN RED GREEN BLUE BLANK/COR
ALE OCF STOP ENE PSEN RD WR A19/P4-4 P4-3 P4-2 A18/P4-1 A17/P4-0 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 62 47 46 45 44 43 42 41 P1-7-14bit PWM P1-6-14bit PWM P1-5-8bit PWM P1-4-8bit PWM P1-3-8bit PWM P1-2-8bit PWM P1-1-8bit PWM P1-0-8bit PWM
87 19 18 17 88 65 64 67 49 48 68 70 69 71 76 78 77 85 90 83 81 79 82 84 86 89 93 94 97
ALE OCF STOP ENE PSEN# RD# WR# P4.4 P4.3 P4.2 P4.1 P4.0 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
P2.0 P2.1
BLUE GREEN RED
D7 D6 D5 D4 D3 D2 D1 D0 P4.7/VS HS/SSC
96 98 100 2 4 3 1 99 30 29
D7 D6 D5 D4 D3 D2 D1 D0 VSYNC HSYNC VSYNC HSYNC
ENE STOP
P0.6 OCF
R109 330
R119 0R
P4.4 P4.1 P4.0
Fig. 31: Circuit Diagram 1
R120 75
ROUT FL_RST FL_CE
FL_PGM
T106 BC817
2
VSSA
Micronas
SCART 3 52 XTAL2 SCART 3 ALE PSEN# RD# WR# P4.4 P4.1 P4.0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
ALE P4.1
SYNCIN
SCIN
P4.4
R121 75
P1.5
C115 10µ
+5VIN
P1.1 P3.7 P1.0
3
26
2
VCC
C223 100n C246 C225 100n R225 1k2 C242 IC201 MAX3237 R224 39k R222 R223 470 C245 470n R221 82k
12 14 15 16 17 4
100n
GND
18
19
11
+2,5VADC L207 10µH C220 + 10µ + L206 10µH C218 10µ +2,5V + C216 10µ GND
9 7 8 6 5 10
R214 2k7
13
C221 100n +2,5VDAC
U201 MC33269AJ L205 10µH 100n C217 100n
C219
+5VIN
3
VI
VO
2
IC203 TDA4691
ADJ
1
+
C206 R209 360 250 VSYNC 1n L204 +3,3VUNI L203 +3,3VMEM + C210 C211 +
100n
10µ
R208 510 P201
4
3
C215 10µH 10µH C212 C213 100n +3,3V 10µ
R212 8k2
R213 820
R216 2k7
C228 47n
R217 8k2
R218 820
C229 10n
2
C230 220n
CVBS
D203 LOCKED
U200 MC33269AJ L202 10µ + C209 100n GND SSC C208 P200 10µ 250 1n IR/P3.3 10µH
+5VIN
3
VI
VO
2
ADJ
1
+
6
7
8
D201 POWER ON D202 LL4148
+5V
5
VIN
LBI
IC204 LT1317
R204 1M L201 10µH +8V + C204 10µ 100n C227 10µ + C205 R210 100 + C203 47µ R203 110k R202 68k R205 0R
1
LBO
SW
+
SHDN#
D200 1N4001
100µ
R200 330
GND
C200
+
3
C202 3n3
(3)
GND
R201 33k
4
1
Nov. 26, 2003; 6251-556-3-2AK
+8VOUT
+3,3V
C214
10µ
R206 390
R207 510
CON200 POWER 5V
C207
+5VIN
+5VIN
L200
22µH
C201 47µ
VC
FB
2
IC202 SFH506-33
2 VDD IR 3
R211 2k7 (1) (2)
(SFH5110)
1
20
4
CON201
1 2 6 9 7 8 5 3 4
C224 100n +8V +8V
SYNCIN
+3,3V
28 27
C226 RS232 R229 ... R228 2k7 R227 1k8 R226 1k8
C1+
V+
25
C1-
V-
RS232 INTERFACE
+5VIN
100n
1
C2+
C222 22n
SDA 55xx
J201 3k3 C241 + 10µ
6 5 9 8 14
100n
3
C2-
P3.1 TXD
TXD
P3.7 RXD
24 23 20 21
T1IN T2IN R2OUT R1OUT
T2OUT T1OUT R2IN R1IN
Fig. 32: Circuit Diagram 2
C244 2n2 R220 22k R219 15k C243 470n HS R215 1k C240 10n
RXD J200
13
EN#
SHDN#
+3,3V
APPLICATION NOTE KITS/BOARDS
Micronas
R300 4k7
R301 4k7
Micronas
IC301
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# WE# OE# VDD 32 24
RD#
Fig. 33: Circuit Diagram 3
IC302
13 14 15 17 18 19 20 21
D0 D1 D2 D3 D4 D5 D6 D7
APPLICATION NOTE KITS/BOARDS
+3,3VMEM
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 G# W# VDD 31 32 24
PSEN#
13 14 15 17 18 19 20 21
D0 D1 D2 D3 D4 D5 D6 D7
22 29
WR#
A15
R304 100k C302 100n
+3,3VMEM
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A16 P4.0 P4.1 P4.4 A17 A18 A19
C301 100n
VSS 16
12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 30 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 VSS E# 16 22
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 P4.0 P4.1
12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 A17 30 A18 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
Nov. 26, 2003; 6251-556-3-2AK
68V4000B M29W040 C300 100n +3,3VMEM
+3,3V
IC300
8 VDD CS0 CS1 CS2 GND@1 4 3 2 WP SCL SDA 1 7 6 5
SCL P3.2
J301 SCL
P3.4 SDA
SDA J300
SLA24C32-D-3/P
SDA 55xx
5
SDA 55xx
4. Application Note History 1. Application Note Kits/Boards: "SDA 55XX TVText Pro", Oct. 9, 2001, 6251-556-1AN. First release of the application note kits/boards. 1. Application Note Kits/Boards: "SDA 55XX TVText Pro", Nov. 26, 2003, 6251-556-3-2AK. Second release of the application note kits/boards. Major changes: · Section 3. on page 3. Circuit diagram 1 and 2 updated, circuit diagram 3 added.
APPLICATION NOTE KITS/BOARDS
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: [email protected] Internet: www.micronas.com Printed in Germany Order No. 6251-556-3-2AK
All information and data contained in this document are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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Nov. 26, 2003; 6251-556-3-2AK
Micronas